KR0166496B1 - Redundancy apparatus of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy device of a semiconductor memory device, wherein a switch element is added between an address line and an input terminal of a redundancy sensing device so that an address is sent to a redundancy device of a block not selected by a block select address signal. By not inputting, the load on the address line is reduced and the operation speed is increased.

Description

Redundancy Device for Semiconductor Memory Devices

1 is a circuit diagram of redundancy according to the first embodiment of the prior art.

2 is a block diagram of redundancy according to the second conventional embodiment.

3 is a circuit diagram of redundancy according to the first embodiment of the present invention.

4 is a circuit diagram of redundancy according to the second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

101: fuse box 201 to 203: redundancy address detection means

301: cell array block 401: switch means

The present invention relates to a redundancy device of a semiconductor memory device, and more particularly, to a redundancy device in which an address is not input to a redundancy device of an unselected block.

In general, a redundancy device is a device that compensates for a defect by replacing a bit line to which a defective cell is connected with an extra spare bit line when a defect occurs in any cell in the cell array. When an address for selecting a defective cell is applied to the inside of the device, the normal path for selecting the defective cell is broken, and instead, the redundancy device operates to enable the bit line to which the repaired cell is connected, thereby making the redundancy operation occur. do.

Hereinafter, for convenience of description, a redundancy device will be described with reference to 16 mega DRAM currently used.

The 16 mega DRAM contains four large cell array blocks consisting of 16 cell arrays containing 256 word cells and 256 k cells connected to each 1k bit line for operational stability. There is a cell array small block.

The four large cell array blocks are classified using two addresses of column addresses, and the sixteen cell array small blocks constituting each of the cell array blocks are each using four addresses of row addresses according to the refresh ratio. The 256 word lines in the cell array small blocks including the 256K bit cells are distinguished by using row addresses, and the 1k bit lines are distinguished using 10 210 addresses among the column addresses.

However, the column address has a characteristic of a chip in a read path for transferring data transferred from the cell array block to the data output device or a write path for transferring data transferred from the data input device to the cell array block. Thus used to selectively pass data.

FIG. 1 is a circuit diagram of redundancy according to the first embodiment of the present invention, which is connected between a power supply voltage Vdd and a node N1, and is connected to a PMOS transistor Q1 operating on / off switching by a precharge signal. ; A plurality of fuses f1 to fn connected between the node N1 and the ground voltage Vss, and a plurality of fuses connected between the fuses f1 to fn and the ground voltage Vss and to which an address signal is applied to a gate. A fuse box 101 comprising NMOS transistors NM1 to NMn; An inverter (G1) connected between the node (N1) and node (N5); A NAND gate G2 that receives and logically combines a row / col path enable signal through a node N4 and an output signal of the inverter G1; An inverter (G3) for inverting the output signal of the NAND gate (G2) and outputting a normal signal (normal); A NAND gate G4 for receiving and logically combining a row / col path enable signal through the node N4 and a signal on the node N4; Inverter G5 outputs a spare signal by inverting the output signal of the NAND gate G4.

The redundancy apparatus of FIG. 1 is a device for detecting whether an address signal input from the outside is a redundancy address or a normal address, and is configured to output a logical sum signal as described above.

The method of storing the redundancy address in the redundancy device is to cut the fuse of the device to which the redundancy address is input. When a signal operating to the output terminal N1 of the redundancy device is input, the redundancy address of the redundancy device is stored. The potential changes to a state indicating a normal state, indicating normal operation, not redundancy.

However, when the address signal corresponding to the cut fuse is input when the fuses f1 to ripple are cut, the potential of the output terminal indicates the redundancy state, that is, the precharge state is maintained as it is, thereby detecting that the redundancy address has been input. do. Subsequent operations will use the output signal of this sensing device to operate the extra cells.

FIG. 2 illustrates that the redundancy sensing device of FIG. 1 is connected. In the case of the device to which the redundancy sensing device is connected as described above, the load of the address line is increased.

This causes a delay in address signal propagation, resulting in a delay in overall operating time.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and by reducing the load on the address line and speeding up the operation speed by preventing an address from being input to a redundancy device of an unselected block, The purpose is to provide.

According to an embodiment of the present invention to achieve the above object, there is provided a redundancy apparatus for a semiconductor memory device, comprising: redundancy address detecting means for detecting a redundancy address for an address signal input from an address input terminal; Redundancy of the semiconductor memory device provided between the address input terminal and the redundancy address sensing means and having switch means for controlling the transfer of the address signal to the redundancy address sensing means by a block selection address signal transmitted from the outside. An apparatus is provided.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a circuit diagram of a redundancy apparatus according to the first embodiment of the present invention, and reference numerals 103 and 105 are redundancy address detecting means for detecting whether an address signal input from the outside is a redundancy address or a normal address. The sensing means (103; 105) includes a PMOS transistor (Q2; Q9) and a fuse (f1; f2) which are switched on or off by an input of a precharge signal, and an NMOS transistor (switching) which is switched according to an address signal input from the outside ( It consists of a fuse box 101 (101) of Q3;

Reference numeral 401 is provided between the address input terminal add and the redundancy address detecting means 103 and 105, and is applied to the redundancy address detecting means 103 and 105 by a block selection address signal add_bs transmitted from the outside. As a switch means for controlling the transfer of the transistor, it preferably consists of a transfer gate (referred to as a transfer transistor) of a PMOS transistor Q6 and an NMOS transistor Q7.

In the same figure, reference numerals Q4 and Q8 denote NMOS transistors as elements for disabling the sensing operation of the corresponding redundancy address sensing means 103 and 105, and the sensing means disable element Q4 refers to the redundancy address sensing means 103. The output terminal N14 of the corresponding redundancy address sensing means 103 by the block selection address signal add_bs connected between the output terminal N14 and the block selection address signal input terminal add_bs applied to the gate through the inverter IV1. By discharging the potential of, the redundancy address detecting means 103 does not operate when the input of the address signal to the corresponding redundancy address detecting means 103 is interrupted.

The sensing means disable element Q8 is connected between the output terminal N14 of the redundancy address sensing means 105 and the block selection address signal input terminal add_bs and applied to a gate through the inverter IV1 to the gate. When the input of the address signal to the corresponding redundancy address detecting means 105 is interrupted by discharging the potential of the output terminal N14 of the redundancy address detecting means 105 by (add_bs), the redundancy address detecting means 105 Do not work.

Reference numeral Q5 denotes an NMOS transistor serving as an element for disabling the input of the address signal to the redundancy address detecting means 103 and 105. The input disable element Q5 corresponds to the NMOS transistors Q3 and Q3 in each fuse box 101. The potential of the node N13 is discharged by the block selection address signal add_bs which is provided between the gate and the ground terminal of Q10) and is input through the inverter IV1, thereby providing the address signal to the corresponding redundancy address detecting means 103,105. When the input is blocked, the address input terminal N13 of the redundant address detecting means 103, 105 is initialized.

According to the first embodiment of the present invention configured as described above, the switch means 401 composed of the PMOS and the NMOS transistors Q6 and Q7 is controlled by the block select address signal add_bs to add the address signal add. To be transmitted to the redundancy sensing devices 103 and 105.

At this time, the signal of the address line is transmitted to the redundancy detection device in the block selected by the block selection address signal add_bs, and the signal of the address line is not transmitted to the block not selected.

4 is a circuit diagram of a redundancy sensing device according to a second embodiment of the present invention. The redundancy address detecting means 201 and the address input terminal add_ij0 detect whether an externally input address signal is a redundant address or a normal address. : 3, add_jk2: 3 and the redundancy address detecting means 201 are provided, and the transmission of the address signal applied to the redundancy address detecting means 201 by the block selection address signal add_bs transmitted from the outside is performed. It comprises a switch means 401 for controlling.

Here, the redundancy address detecting means 201 is connected to the power supply voltage Vdd and the node N1 in the same manner as the configuration described with reference to FIG. 1 to perform on / off switching operation by precharge signal precharge. (Q1); A plurality of fuses f1 to fn connected between the node N1 and the ground voltage Vss, and a plurality of fuses connected between the fuses f1 to fn and the ground voltage Vss and to which an address signal is applied to a gate. A fuse box 101 comprising NMOS transistors NM1 to NMn; An inverter (G1) connected between the node (N1) and node (N5); A NAND gate G2 that receives and logically combines a row / col path enable signal through a node N4 and an output signal of the inverter G1; An inverter (G3) for inverting the output signal of the NAND gate (2) to output a normal signal (normal); A NAND gate G4 for receiving a logical combination of a row / col path enable signal through the node N4 and a signal on the node N1; Inverter G5 outputs a spare signal by inverting the output signal of the NAND gate G4.

The switch means 401 is composed of a plurality of NMOS transistors, the gate of each of which is connected to the input terminal of the block select address signal add_bs via the inverter IV2 and the drain of the address signal add_ij0. It is connected to the input terminal of: 3, add_jk2, 3, and the source is connected to the gates of the respective NMOS transistors NM1 to NMn in one-to-one correspondence in the fuse box 101.

Here, as the gate signal of the NMOS transistor constituting the switch means 401, a potential higher than a power supply potential (for example, Vpp) is preferably applied at turn-on.

Of course, the switch means 401 may be implemented as a PMOS transistor. In this case, it is preferable that a potential lower than the ground potential is applied as the gate signal of the PMOS transistor at turn-on.

According to the second embodiment of the present invention configured as described above, the redundancy address detecting means 201 also transmits the signal of the address line to the redundancy address detecting means in the block selected by the block selection address signal add_bs. The address signal is not transmitted to the redundancy address detecting means of the unblocked block.

According to the present invention as described above, in the case of a row address, when the load of the other normal address is larger than the block selection address and the delay time is long, the operation speed can be reduced by reducing the load of the other normal address. In the case of the column address, there is an effect that can greatly contribute to reducing the delay of the column address line.

Claims (10)

A redundancy apparatus for a semiconductor memory device, comprising: redundancy address detecting means for detecting whether a redundancy address is applied to an address signal input from an address input terminal, and installed between the address input terminal and the redundancy address detecting means and transmitted from the outside; And redundancy means for switching transmission of said address signal to said redundancy address detecting means by a block selection address signal. 2. The redundancy apparatus of the semiconductor memory device according to claim 1, wherein the redundancy address sensing means is provided in plural numbers. The redundancy apparatus of claim 1, wherein the switch means comprises an NMOS transistor. 4. The redundancy apparatus of claim 3, wherein a potential higher than a power supply potential is applied to the gate signal of the NMOS transistor when it is turned on. The redundancy apparatus of a semiconductor memory device according to claim 1, wherein said switch means comprises a PMOS transistor. 6. The redundancy apparatus of claim 5, wherein a potential lower than the ground potential is applied to the gate signal of the PMOS transistor at turn-on. 3. The redundancy apparatus of claim 1 or 2, wherein said switch means comprises a transfer transistor. 2. The redundancy of the semiconductor memory device according to claim 1, further comprising a sensing means disable element for disabling the operation of the redundant address sensing means when the input of the address signal is blocked by the redundant address sensing means. Device. 9. The semiconductor memory device according to claim 1 or 8, further comprising an initialization element for initializing an address input terminal of the redundancy address detecting means when the input of the address signal is blocked by the redundancy address detecting means. Redundancy device. 10. The redundancy apparatus of claim 9, wherein the sensing means disable element and the initialization element comprise MOS transistors.