KR960012793B1 - Fail repair method and circuit for semiconductor memory device - Google Patents

Abstract

The semiconductor memory device is for supplying a memory block selected in test mode with a source power voltage by comprising: a block free decoder outputting the decoding result of a block selecting signal from the external as a block selecting signal; a test pad inputting a test control signal applied from the external; and a block row decoder charging the power voltage line corresponding to the selected memory block to a source power voltage level by composing the test control signal and the block selecting signal.

Description

Fault Remedy Method and Circuits for Semiconductor Memory Devices

1 is a schematic block diagram of a memory device having a defect repair circuit according to the present invention;

FIG. 2 is a detailed view of a portion of the memory block shown in FIG.

3 is a concrete circuit diagram of the test control circuit 26 shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method and a circuit for repairing defects generated in a memory device.

In general, as the semiconductor memory device is highly integrated, the probability of occurrence of a defect increases gradually, and thus, the yield of the manufacturing process is lowered. Therefore, as semiconductor memory devices have been highly integrated, redundant cells have been adopted to replace defective memory cells with the aim of increasing the yield of manufacturing processes.

In a memory device having a static memory cell using a flip-flop type cell (hereinafter referred to as a static cell), a memory cell in which a defect is generated in a memory device employing a redundant cell is selected. In addition to the replacement of the redundant cell, the DC defect of the defective cell must be removed. In other words, the defect is repaired by replacing the defective memory cell with a redundant cell, but unnecessary current flow is generated by the direct current flowing inside the defective cell. The blocking operation is necessary. Prior arts for solving this problem are disclosed in US Pat. No. 4,780,851, which was issued to Osamu Kurakami in 1988.

One of the unique features of the static cell is that the standby current is smaller than other types of memory cells such as DRAM cells. The operating standby current is an important factor in determining the reliability of the memory device. Furthermore, the operating standby current is required to develop a low power consumption memory device that can operate at low power and is suitable for a battery operating system. This is a big factor. Therefore, most static cell memory devices provide the operating standby current rating as a product standard. According to the patent of Osamu, the replacement of a defective memory cell and a DC defect can be eliminated, but it is difficult to identify a memory cell having a problem such as a failure of an operating standby current, that is, an excessive consumption of operating standby current. There is a problem in that a memory cell having a poor operating standby current cannot be replaced with a redundant cell.

Accordingly, an object of the present invention is to provide a method and circuit for repairing a defect of a semiconductor memory device capable of eliminating an operation standby current defect.

According to the above object, the present invention provides a memory cell array comprising a plurality of memory blocks arranged in a row direction and sharing a word line, and provided in the memory block one-to-one and located in the memory block. A semiconductor memory device having power supply voltage supply lines commonly connected to power supply voltage input terminals of static cells, comprising: a block predecoder for receiving block selection signals applied from an outside of the memory device and outputting a decoding result as a block selection signal; And a test pad for inputting a test control signal applied from the outside, and a block low decoder for charging the power voltage line corresponding to the selected memory block to a power voltage level by combining the test control signal and the block selection signal. Power supply only to selected memory block It shall be.

In addition, the present invention provides a memory cell array comprising a plurality of memory blocks arranged in a row direction and sharing a word line, and a plurality of static cells provided in the memory block one-to-one and located in the memory block. In the method for repairing a standby current defect of an operation of a semiconductor memory device having a power supply voltage supply line commonly connected to a power supply voltage input terminal, the first step of applying a test control signal from the outside of the memory device through a test pad and controlling the test control signal Receiving a block selection signal applied from the outside of the memory device and outputting the decoding result as a block selection signal; and combining the block selection signal and the test control signal to supply a power supply voltage line corresponding to the selected memory block. 3 steps of charging to a level; Four steps to determine the operating standby current defect by measuring the current flowing between the source voltage supply line and the ground voltage, and five steps to cut off the power supply voltage to the power supply voltage supply line of the memory block beyond the preset value do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to assist the overall understanding of the present invention.

1 is a schematic block diagram of a semiconductor memory device having a coupling relief circuit according to the present invention. Referring to FIG. 1, the memory cell array has i memory blocks formed from BK1 to BKi. Each memory block has a preset number of memory cells, and is supplied with a power supply voltage through a common voltage line Vcc provided one to one.

FIG. 2 is a detailed view of a part of the memory block shown in FIG. 1. Referring to FIG. 2, the static cell includes a load resistor R1 and R2 connected to the power supply voltage line Vcc and the data storage nodes N1 and N2, respectively, and the gate terminal is connected to the data storage node of the other party so that each channel is latched with each other. Driving transistors T1 and T2 connected to the data storage node and the ground voltage line, and the data storage nodes N1 and N2 and the bit line pair BL and The two transistors T3 and T4 each have a channel connected to each other and a gate terminal thereof is commonly controlled in a word line. The power supply voltage line Vcc supplies a power supply voltage to two static cell groups arranged in a row direction.

Returning to FIG. 1 again, Ai is input to the address buffer 12 as a block selection address for selecting each block. The address buffer 12 is activated when the control signal Mi is input at the low level, receives the block addresses, and forms the address signals Ai and Is output to the block predecoder 14. The block predecoder 14 combines the input address signals to block selection signals. Is output to the block decoder 16. Block decoder 16 is the block selection signal I n gates 18 to which one outputs a low signal, inverters 20 connected to output nodes of each of the NAND gates 18, and a test control signal applied through the test pad 22 i n gates are commonly input to each first input terminal, and i n gates 24 input the outputs of the inverters 120 to the second input terminals. The output of each of the NAND gates 24 is connected one-to-one to the power supply voltage line Vcc of each of the memory blocks BK1 to BKi through the corresponding fuses f1 to fi.

The test control signal? TE input through the test pad 22 is input to a test control circuit, and the test control circuit is a chip select signal applied from the test control signal? TE. Is combined to output a control signal Mi for determining the activation of the address buffer 12. The test pad 22 is connected to the ground voltage through the resistor R1. Accordingly, when there is no input to the test pad 22, the test control signal? TE has a ground voltage level.

FIG. 3 discloses a specific circuit diagram of the test control circuit 26 shown in FIG. Referring to FIG. 2, the test control circuit 26 may provide an external chip select signal. And an NAND gate 28 and an NOR gate 30 that are negative and logically negative, and outputs of each of the NAND gate 28 and the NOR gate 30 are negatively multiplied by the test control signal? TE applied from the test pad 22. NAND gate 32 to be logically multiplied, NAND gate 34 to negatively multiply the output of NAND gate 28 and the output of NAND gate 32, and an inverter 36 that inverts the output and outputs the control signal Mi. ) Therefore, the test control circuit shown in FIG. 3 has a chip select signal applied from the outside, as shown in Equation (1) below. And the test control signal? TE applied from the test pad 22 is operated as an exclusive logical sum.

Therefore, the control signal Mi is the chip select signal. Alternatively, the high level is enabled only when the test control signals? TE remain at levels complementary to each other.

Now, the operation of FIG. 1 will be described with reference to FIGS. 2 to 3.

Except in the test mode, the control signal? TE output from the test pad 22 maintains a low level. At this time, the control signal Mi is determined according to the logic level of the chip select signal. In other words, Is set to low level (i.e., access operation mode), Mi becomes low level. At this time, the address buffer 12 is activated to input a block selection address, and thus the address signals are input to the block predecoder. Normal access operation is performed. On the other hand Is applied to the high level (i.e., the operation standby mode), the Mi becomes the high level. At this time, the address buffer 12 is deactivated so that the block selection address is not inputted, and thus the memory device is placed in the operation standby state. do.

Next, look at the test mode. In the test mode, a high level øTE signal is applied to the test pad 22 and the chip select signal. Is started by applying to a high level. At this time, the control signal Mi has a low level, and the address buffer 12 is activated accordingly. In addition, as? TE is applied at a high level, the outputs of the NAND gates 24 of the block decoder circuit 16 become block select signals PQR /. Since only one memory block selected by the block selection signal is supplied with the power supply voltage Vcc, the power supply voltage is not applied to the remaining memory blocks. In this case, if the current flowing from the power voltage terminal of the selected memory block to the ground voltage terminal is measured, the current consumption in the operation standby mode can be accurately measured. In this case, if the operation standby current is measured while sequentially selecting all memory blocks BK1 to BKi by sequentially converting the block addresses, all the operation standby currents of all the memory blocks can be measured. It is possible to remedy the defect of the operating standby current by judging whether the measured memory block conforms to the designed prescribed value and if it is determined to be defective, by replacing the memory block with a redundant memory block (not shown). At this time, the DC fault is removed by cutting the fuse for supplying the power voltage of the memory block replaced with the redundant memory block.

As described above, according to the present invention, a memory device having excellent reliability is provided by resolving an operation standby current defect.

Claims (6)

A semiconductor memory device having a memory cell array comprising a plurality of memory blocks arranged in a row and sharing a word line, and having a power supply voltage supply line commonly connected to each of the memory blocks. A block predecoder that receives the block selection signals applied from the output signal and outputs the decoding result as the block selection signal, a test pad for inputting a test control signal applied from the outside, and a combination of the test control signal and the block selection signal. And a block low decoder for charging a power supply voltage line corresponding to the memory block to a power supply voltage level, so that the power supply voltage is shared with only the selected memory block in the test mode. The semiconductor memory device of claim 1, wherein the test pad is connected to a ground voltage through a resistor. The semiconductor memory device of claim 1, wherein the power supply voltage line is supplied with a power supply voltage from a block low decoder through a cuttable fuse. An operating standby current defect of a semiconductor memory device having a memory cell array including a plurality of memory blocks arranged in a row and sharing a word line, and a power voltage supply line commonly connected to each of the memory blocks. In the remedy method, a process of applying a test control signal from the outside of the memory device through a test pad and an address signal controlled by the test control signal from the outside of the memory device are received and output the decoding result as a block selection signal. And two steps of combining the block selection signal and the test control signal to charge the power supply voltage line corresponding to the selected memory block to a power supply voltage level, and a current flowing between the power supply voltage supply line and the ground voltage of the selected memory block. 4 steps to determine the operating standby current defect by measuring , A preset predetermined value to the standby current fault remedy of the semiconductor memory device to a power supply voltage supply line of the memory block, characterized in that the process comprises a 5 to cut off the power supply voltage is outside. 5. The method of claim 4, wherein said step 2 is controlled by an exclusive logical sum of a chip select signal and a test control signal for activating an access operation of a memory device. The method of claim 4, wherein the test pad is maintained at a ground voltage level when there is no input of a control signal to the test pad. 6.