KR100375998B1 - Semiconductor device having embedded auto test and repair function and Method thereof - Google Patents

Abstract

Disclosed are a semiconductor memory device and a method for embedding an automatic test and repair function. The automatic test and repair method of the present invention comprises the steps of: (a) generating test data and writing to each memory cell of the memory cell array; (b) reading data from each memory cell; (c) comparing the read data with the written data, respectively; (d) detecting defective row lines and defective column lines based on the comparison result; And (e) using the detection result, replacing the defective line with a redundancy line. In particular, step (d) detects the largest bad row line or the largest bad column line including the most bad memory cells among the bad row lines and the bad column lines. In addition, the semiconductor memory device of the present invention includes an automatic test and repair circuit for performing the automatic test and repair method. By the semiconductor memory device having the automatic test and repair circuit and the automatic test and repair method according to the present invention, the test cost is reduced and the test and repair process is simplified. In addition, the redundancy memory can be optimally used by detecting and repairing the most defective line first.

Description

Semiconductor memory device having embedded auto test and repair function and method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to circuits and methods for automatically testing and repairing memory blocks in semiconductor memory devices incorporating memory blocks.

Semiconductor memory devices have become increasingly large in capacity. In addition, according to the trend of system-on-chip, which combines logic and memory together to implement a system on a single chip, a growing number of semiconductor memory devices in which a large amount of memory is embedded is installed. However, the increase in the capacity of the memory device is a factor in rapidly increasing the test cost of the memory device. The development and purchase of new test equipment for testing large memory devices, and the cost of operating such test equipment, represent a significant portion of the cost of the actual semiconductor memory device.

1 is a flowchart illustrating an overall test and repair process of a semiconductor memory device according to the related art. Referring to this, after the process of the wafer state is finished (S100), the first wafer test is performed by using the wafer level test equipment 10 (S102). The result of the first wafer test is used to replace a failed row or column with a redundancy row or column provided in the memory device. At this time, the repair is performed by selectively cutting the fuse using the wafer level repair equipment 12 such as the laser equipment (S104). In this way, the use of laser equipment for repair is one factor that increases the test cost.

After the laser repair process is finished (S104), the second wafer test is performed again (S106). Here, using the obtained test result, only the semiconductor memory device in normal operation is selected (S108), and a packaging process is performed (S110). After the packaging process S110, an open / short test S112, which is a simple electrical characteristic, and a functional test S114 of the memory device are performed. In these two processes S112 and S114, package level test equipment 14 and 16 are used. Next, a burn-in test is performed (S116), and finally, a function and speed test is performed using the package level test equipment 18 (S118). By using the result of this step (S118), it is again classified as good or bad (S120), and the final product for the good (S122). When the laser repair method is used as described above, defective products generated in the test process performed after the packaging process cannot be repaired. Therefore, it is finally classified as a defective article and processed.

As described above, the conventional test and repair method using external test equipment has a high test and repair cost, a complicated test and repair process, and a low overall yield of the semiconductor memory device.

The technical problem to be achieved by the present invention is the automatic test and repair circuit is performed automatically inside the semiconductor memory device, the test cost is low, the test and repair process is simple, and the automatic test and repair circuit to make optimal use of the redundancy memory It is to provide a semiconductor memory device having a.

Another technical problem to be solved by the present invention is to perform the test and repair automatically in the semiconductor memory device, so that the test cost is low, the test and repair process is simple, and the automatic test and repair to make optimal use of the redundancy memory To provide a way.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a flowchart illustrating an overall test and repair process of a semiconductor memory device according to the related art.

2 is a block diagram illustrating a semiconductor memory device having an automatic test and repair function according to an exemplary embodiment of the present invention.

3 is a diagram illustrating an example of a circuit for generating a test control signal illustrated in FIG. 2.

4 is a diagram illustrating an example of a test pattern generating circuit and an address generating circuit shown in FIG. 2.

FIG. 5 is a detailed block diagram of the comparison circuit and the repair determination circuit shown in FIG. 2.

FIG. 6 is a circuit diagram illustrating an example embodiment of a repair circuit of the semiconductor memory device illustrated in FIG. 2.

7 is a flowchart illustrating an automatic test and repair method of a semiconductor memory device according to an embodiment of the present invention.

8 is a flowchart illustrating an overall test and repair process of a semiconductor memory device according to an embodiment of the present invention.

One aspect of the present invention for achieving the above technical problem relates to a semiconductor memory device. A semiconductor memory device according to an embodiment of the present invention is a memory cell array for storing data, and includes a plurality of row lines, a plurality of column lines, and at least one row for replacing a defective one of the row lines. The memory cell array including a redundancy row line and at least one redundancy column line for replacing a defective one of the column lines; A test circuit for applying predetermined test data to the memory cell array to detect the defective row line and the defective column line and output the detection result; And a repair circuit for replacing the defective row line with a redundancy row line and replacing the defective column line with a redundancy column line in response to the detection result output from the test circuit. The test circuit detects a maximum bad row line or a maximum bad column line including the most bad memory cell among the bad row line and the bad column line, and corresponds to the maximum bad row line or the maximum bad column line. The address to be output is output as the detection result. The repair circuit may include a fuse device that is electrically active in response to the detection result; Exclusive OR means for exclusive OR of the voltages across the fuse element; And a fuse state register for storing the result of the exclusive OR means as a fuse state.

One aspect of the present invention for achieving the above technical problem is a memory cell array for storing data, a plurality of row lines, a plurality of column lines, at least one for replacing a defective row line of the row lines An automatic test and automatic repair method performed in a semiconductor memory device having a memory cell array including a redundancy row line and at least one redundancy column line for replacing a defective one of the column lines. An automatic test and repair method for a semiconductor memory device according to the present invention includes the steps of: (a) generating test data and writing it to each memory cell of the memory cell array; (b) reading data from each memory cell of the memory cell array; (c) comparing the read data with the data written in step (a), respectively; (d) detecting, based on the comparison result of step (c), a bad row line among the row lines and a bad column line among the column lines, and outputting the detection result; And (e) using the detection result obtained in step (d), replacing the defective row line with a redundant row line and replacing the defective column line with a redundant column line. The automatic test and repair method of the semiconductor memory device may include generating (pd1) inverted data of the test data and writing each memory cell of the memory cell array before step (d); (pd2) reading data from each memory cell of the memory cell array; And (pd3) comparing the read data with the data written in the step (pd1). The step (d) is based on the comparison result of the step (c) and the comparison result of the step (pd3), the maximum bad row including the most bad memory cell of the bad row line and the bad column line A line or a maximum bad column line is detected, and an address corresponding to the maximum bad row line or the maximum bad column line is output as the detection result.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, for the convenience of description, signals performing the same role through the drawings are denoted by the same reference numerals.

2 is a block diagram illustrating a semiconductor memory device having an automatic test and repair function according to an exemplary embodiment of the present invention. Referring to this, the semiconductor memory device according to an embodiment of the present invention includes a memory cell array 20, a test circuit 30, and a repair circuit 40.

The memory cell array 20 is a part for storing data. The memory cell array 20 includes a core memory 210 including a plurality of row lines and a plurality of column lines, and a low redundancy memory including at least one redundancy row line for replacing a defective one of the row lines. And a column redundancy memory 230 including at least one redundancy column line for replacing the defective one of the column lines.

The test circuit 30 applies predetermined test data T_DAT to the memory cell array 20 to detect bad row lines and bad column lines. In particular, the test circuit 30 detects the largest bad row line or the largest bad column line including the most bad memory cells among bad row lines and bad column lines, and outputs an address corresponding thereto as a detection result, Try to repair the most defective line first. Thus, the use efficiency of the redundancy memory can be increased.

Preferably, the test circuit 30 includes a row address generation circuit 310, a column address generation circuit 320, a test pattern generation circuit 330, a comparison circuit 340, and a repair determination circuit 350.

The row address generation circuit 310 generates an internal row address I_X_ADDR specifying a row line to access the memory cells. The column address generation circuit 320 generates an internal column address I_Y_ADDR specifying a column line to access the memory cells. For convenience of description, the row address generating circuit 310 and the column address generating circuit 320 are collectively referred to as an address generating circuit. The row address X_ADDR and the column address Y_ADDR are collectively referred to as an address.

Preferably, the semiconductor memory device selects one of an internal row address I_X_ADDR and an external row address E_X_ADDR input through a pin of the semiconductor memory device in response to the test control signal ATR, thereby selecting the row address X_ADDR. In response to the first selector 510 to be outputted as () and the test control signal ATR, a second to select one of the internal column address I_Y_ADDR and the external column address E_Y_ADDR to output as the column address Y_ADDR. A selector 520 is further provided. Here, the test control signal ATR is a signal for causing the semiconductor memory device to enter the automatic test and repair mode according to an embodiment of the present invention.

A circuit for generating a test control signal is shown in FIG. Referring to this, the test control signal ATR is generated by the test enable signal TST_EN while the power-on reset signal PWR_ON_R indicating whether the external power is applied is activated at a high level. The test enable signal TST_EN is a signal applied from the outside of the semiconductor memory device. When both the power-on reset signal PWR_ON_R and the test enable signal TST_EN are activated at a high level, the test control signal ATR is activated. As a result, the semiconductor memory device enters the automatic test and repair mode.

Referring back to FIG. 2, the semiconductor memory device further includes a row decoder 530 and a column decoder 540 that receive a row address X_ADDR and a column address Y_ADDR, respectively, and drive corresponding row and column lines. do.

The test pattern generator 330 generates test data T_DAT to be written in the memory cells. Preferably, the test data T_DAT is a check-board pattern in which the high level and the low level are alternated. The checkerboard pattern is a test data pattern in which data of the same level is not continuous in the row line direction and the column line direction, and is a pattern of, for example, 101010. As such, the test pattern generation circuit 330 for generating the test data T_DAT having the check board pattern and the internal row address I_X_ADDR sequentially increasing or decreasing to sequentially write the test data T_DAT into the memory cells. 4 illustrates an example of an address generating circuit 610 that generates an internal column address I_Y_ADDR.

Referring to Fig. 4, the address generating circuit 610 is composed of only the incremental adder 612. Incremental adder 612 is a device that outputs by adding a predetermined value to a previous output value. The test pattern generator 330 is simply configured as a multiplexer 332. Alternating data starting from 0 is input to one input terminal of the multiplexer 332, and alternating data starting from 1 is input to the other input terminal. The multiplexer 332 multiplexes the input data in response to the internal address I_ADDR generated from the address generation circuit 610, that is, according to whether the internal address I_ADDR is odd or even, and as the test data T_DAT. Output Since the test pattern generator 330 and the address generator 610 of the simple structure as shown in FIG. 4 occupy a minimum occupied area, the test pattern generator 330 and the address generator 610 are well suited for being embedded in a semiconductor memory device.

The test data T_DAT is written in the memory cells designated by the internal address I_ADDR, that is, the internal row address I_X_ADDR and the internal column address I_Y_ADDR. The written data is read again later, and compared with the read data to determine whether the corresponding memory cell is defective.

Referring back to FIG. 2, preferably, the semiconductor memory device selects one of the test data T_DAT and the data E_DAT input from the outside as the write data W_DAT in response to the test control signal ATR. A third selector 550 is further provided.

The comparison circuit 340 compares the data W_DAT written in the memory cells with the data R_DAT read from the memory cells.

The repair determination circuit 350 obtains an address corresponding to the largest bad row line based on the comparison result CMP_R output from the comparison circuit 340 and outputs the address as the repair row address R_X_ADDR or corresponds to the maximum bad column line. The address to be obtained is obtained and output as the repair column address R_Y_ADDR. The repair row address R_X_ADDR or the repair column address R_Y_ADDR corresponds to the detection result.

A detailed block diagram of the comparison circuit 340 and the repair determination circuit 350 is shown in FIG. 5. Referring to FIG. 5, the comparison circuit 340 is implemented with a plurality of comparators 342 and a counter 344. Comparator 342 is an exclusive OR gate. Preferably the number of comparators 342 is equal to the number of memory data buses 620. The memory data bus 620 is a data line connected to the memory cell array 20 to read data from the memory cell array 20 and to write data to the memory cell array 20. Accordingly, the semiconductor memory device may operate as X8, X16, or the like. Therefore, in the case of X16, the number of the comparators 342 is also preferably 16.

Each comparator 342 receives one read data R_DAT output from the data bus 620 and the write data W_DAT generated in the test pattern generator 330 and written in the corresponding memory cell, respectively. Compare this. At this time, the comparator 342 outputs '0' when two input data R_DAT and W_DAT are the same, that is, when the corresponding memory cell is not defective, and when the two input data R_DAT and W_DAT are different. That is, '1' is output when the memory cell is defective. The counter 344 receives' 0 'or' 1 'output from each comparator 342 and counts the number of' 1's. The counter 344 outputs the counted '1' as the defective number FN. Preferably, the counter 344 outputs the defective number FN in units of row lines and column lines. The defective number FN output from the counter 344 corresponds to the comparison result CMP_R.

The repair determination circuit 340 includes first and second registers 357 and 358, a defective number comparator 356, and first and second instructions 352 and 354. The first register 357 is for storing the bad number FN, and the second register 358 is for storing the internal address I_ADDR corresponding to the bad number FN. The defective number comparator 356 compares the defective number FN output from the counter 344 with the value B_FN stored in the first register 357, so that the defective number FN is equal to the first register 357. If the value is larger than the value B_FN stored in the control unit, an active selection signal SS is generated. The first feeder 352 stores the defective number FN in the first register 357 in response to the selection signal SS. Therefore, the first register 357 is continuously updated and stored with the defective number FN having a larger value. In the end, the maximum defective number having the largest value is stored. The second mixer 354 stores the internal row address I_X_ADDR or the internal column address I_Y_ADDR in the second register 358 in response to the selection signal SS. Therefore, in the second register 358, an address of a bad row line or a bad column line corresponding to the maximum number of defectives stored in the first register 357, that is, a repair row address R_X_ADDR or a repair column address R_Y_ADDR that is a detection result. ) Is stored.

In response to the repair row address R_X_ADDR or repair column address R_Y_ADDR, which is a detection result output from the test circuit 30, the repair circuit 40 replaces the defective in-line line with the redundancy row line and replaces the defective column line. Replace with a redundancy column line.

Preferably, the repair circuit 40 includes a fuse that is electrically activated in response to the repair address R_X_ADDR or R_Y_ADDR (hereinafter R_ADDR). The array of fuses for replacing a defective low line with a redundant low line is a low fuse box 410, and the array of fuses for replacing a defective column line with a redundancy column line is a column fuse box 420.

The fuse may be a fuse that is electrically open in response to the repair address R_ADDR, or a fuse that is electrically shorted. The repair circuit 40 includes, for each fuse, a fuse state register for storing the result of the exclusive OR of the exclusive OR of the voltages on both ends of the fuse and the result of the exclusive OR of the fuse or the inversion result as a fuse state. It may further include.

FIG. 6 is a circuit diagram illustrating an embodiment of the repair circuit 40 of the semiconductor memory device shown in FIG. 2. The circuit shown in FIG. 6 is a circuit including one fuse and is a part of the repair circuit 40 including a plurality of fuses.

Referring to this, the repair circuit 40 includes a fuse FS, a PMOS transistor PM, first to fifth NMOS transistors NM1 to NM5, an exclusive OR gate XOR, and an inverter INV. .

The PMOS transistor PM is a transistor for precharging the first node N1. When the precharge signal PRCH_TST is activated at a low level, the PMOS transistor PM supplies the power supply voltage VCC to the first node N1. ) Precharge to level.

The first NMOS transistor NM1 is turned on in response to a specific repair address R_ADDR. Then, in order to activate the fuse FS, a fuse voltage V_FUSE is applied. When the fuse voltage V_FUSE is applied to the second node N2 and the fuse voltage application signal V_FUSE_EN input to the gate of the second NMOS transistor NM2 is activated, the third node N3 is the fuse voltage V_FUSE. ) Will have a level. The third to fifth NMOS transistors NM3 to NM5 are transistors for preventing damage to another device due to a relatively large voltage of the fuse voltage V_FUSE, and are 1/2 of the fuse voltage V_FUSE at each gate. The corresponding voltage HALF_V_FUSE is applied.

When the third node N3 is at the fuse voltage V_FUSE level, the insulating film of the fuse FS is broken, the fuse FS is shorted, and the potential difference between the nodes N3 and N4 is zero. As such, when the fuse FS is activated, a repair for the corresponding repair address R_ADDR is performed.

The exclusive OR gate XOR and the inverter INV are elements for indicating the state of the fuse FS. When the fuse FS is normally activated, since there is no potential difference across the fuse, the output of the exclusive OR gate XOR is zero. Therefore, the fuse state signal FS_ST, which is the result of inverting the output of the exclusive OR gate XOR, becomes 1. That is, when the fuse state signal FS_ST becomes '1', it means that the fuse FS is normally activated. The fuse status signal FS_ST may be stored in a register (not shown).

FIG. 7 is a flowchart illustrating an automatic test and repair method of a semiconductor memory device according to an embodiment of the present invention, FIG. 7A illustrates an automatic test method, and FIG. 7B illustrates an automatic repair method. With reference to this, the overall operation of the semiconductor memory device according to an embodiment of the present invention described above will be described.

First, referring to FIG. 7A, an auto test signal (ATR) is activated by a test enable signal (S200). When the semiconductor memory device enters the automatic test and repair mode by activating the automatic test signal ATR, test data of a check board pattern is generated and written in all memory cells (S202). For this purpose, the address is sequentially generated and generated.

When the test data is written to all the memory cells (S202), the address generating circuit is reset to set the output value of the address generating circuit as the start address (S204). The data is read out from the memory cell of the corresponding address (S206) while sequentially increasing the address starting from the start address (S208). Then, the read data is compared with the prediction data (S210). The predictive data is data written to the address. Since the predictive data is a value which can be known depending on whether the corresponding address is odd or even, it is easy to compare the predicted data with the read data.

After the data is read (S208), inverted data of the data written in the memory cell is written into the memory cell at the address (S212). That is, if 1 was written previously, 0 is written this time.

When such reading, comparing, and inversion data writing processes are performed up to the memory cell designated by the last address (S214), the address generating circuit is reset, and the address is initialized to the start address again (S216).

The address is sequentially increased from the start address to the last address (S218), and data is read again from the corresponding memory cell (S220). The read data is compared with the prediction data again (S222). If the process proceeds to the last address (S224), the test is ended (S226), and the repair address is determined using the comparison result of steps S210 and S222 (S228). The comparison result is the number of failures of the row line or the column line where the failure occurred.

Preferably, first, a test is performed on all the row lines to obtain the address and the number of defects of the defective row line. Next, a test is performed on all the column lines to obtain the address and the number of the defective column lines. All these results are input to the repair determination circuit to find one row line or column line having the most defect among them. Therefore, the line with the most defects can be repaired first. Therefore, the redundancy memory can be used efficiently.

When the repair address is obtained, the repair process is performed next. Referring to FIG. 7B, first, by activating a specific fuse using a repair address, a defective line is replaced with a redundancy line (S300).

After the fuse is activated (S300), the fuse state is checked (S302). Checking the fuse status can be done by reading the value of the register that stores the fuse status signal. If the fuse state is not active, the fuse is reactivated up to a predetermined N times (S304, S300). If the fuse is not normally activated even up to the threshold value N, or if the fuse is normally activated, the corresponding redundancy line is set to not used (S306). To store whether or not the redundancy line is used, a fuse resistor may be provided for each redundancy line. That is, one fuse resistor is provided for each of the redundancy row and the redundancy column, and if the value of the fuse resistor is 1, it means that the corresponding redundancy row line or the redundancy column line is already used or disabled.

Next, an internal automatic test is performed again (S308), and a repair address is determined (S310). Through this, it is determined whether a bad memory cell exists (S312), and if there is no bad memory cell, the semiconductor memory device is determined as a pass (PASS) (S314). If a bad memory cell exists, it is checked whether there is an available redundancy row line or a redundancy column line (S316). If there is an available redundancy line, the process of activating a fuse corresponding to the available redundancy line is repeated (S300). If there is no redundancy line available, the semiconductor memory device is determined as a fail (SAIL) (S318).

The above-mentioned automatic repair and test procedure according to the present invention is a wafer level test and repair procedure. However, the automatic repair and test process according to the present invention can be applied to the package level test and repair process as it is. The automatic repair and test process according to the present invention is performed internally, not using external equipment, and thus can be performed even after packaging is performed.

8 is a flowchart illustrating the overall test and repair process of the semiconductor memory device using the automatic repair and test process according to the present invention.

Referring to this, after the process of the wafer state is finished (S400), the first wafer level automatic test and repair is performed (S402). Using the first automatic test and repair results, a first classification operation for classifying defective and good products is performed (S404). Then, a packaging process is performed on the die in the first classification (S406).

After the packaging process S406, a second automatic test and repair is performed (S408). Next, a burn-in test is performed (S410), and a third automatic test and repair is performed again (S412). Then, a function and speed test may be performed using an external package level test equipment 80 (S414). In this case, the automatic test according to the present invention is omitted, and only the automatic repair is performed according to the result of the external test (S414). Based on this result, the second sorting operation is again performed (S416), and the product is commercialized (S418).

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the semiconductor memory device having the automatic test and repair circuit and the automatic test and repair method according to the present invention, since the test and repair for the memory block is automatically performed inside the semiconductor memory device, the test cost is low and the test and repair is performed. The repair process is simple. In addition, by detecting and repairing the lines with the most defects, the redundant memory is optimally used.

Claims (17)

In a semiconductor memory device, A memory cell array for storing data, comprising: a plurality of row lines, a plurality of column lines, at least one redundancy row line for replacing a defective one of the row lines, and a defective column among the column lines The memory cell array including at least one redundancy column line for replacing a line; A test circuit for applying predetermined test data to the memory cell array to detect the defective row line and the defective column line and output the detection result; And A repair circuit for replacing the defective low line with a redundant low line and replacing the defective column line with a redundant column line in response to the detection result output from the test circuit, The test circuit Detecting a maximum bad row line or a maximum bad column line including the most bad memory cells among the bad row line and the bad column line, the address corresponding to the maximum bad row line or the maximum bad column line Output as a detection result, The repair circuit A fuse element that is electrically active in response to the detection result; Exclusive OR means for exclusive OR of the voltages across the fuse element; And a fuse state register for storing the result of the exclusive OR means as a fuse state. The method of claim 1, wherein the test circuit And a test pattern generation circuit for generating the test data to be written in the memory cells included in the memory cell array. The circuit of claim 2, wherein the test pattern generating circuit is And generating the test data in a checkerboard pattern in which a high level and a low level are alternated. The method of claim 2, wherein the test circuit is A comparison circuit for comparing data written in the memory cells with data read from the memory cells; And And a repair determination circuit that obtains an address corresponding to the maximum bad row line or the maximum bad column line and outputs the detected result as the detection result based on the output result of the comparison circuit. 5. The test circuit of claim 2, wherein the test circuit comprises: A row address generation circuit for generating an internal row address specifying the row line to access the memory cells; And And a column address generation circuit for generating an internal column address specifying the column line to access the memory cells. The method of claim 4, wherein the comparison circuit A plurality of exclusive OR means for receiving output data of the test pattern generation circuit and data read from the memory cell and outputting a result of performing an exclusive OR; And And a high level counter which counts the number of high levels among the output signals of the exclusive ORs and outputs the count as a defective number. The circuit of claim 4, wherein the repair determination circuit comprises: A first register for storing the defective number; A second register for storing the detection result; A bad number comparator that compares the bad number with a value stored in the first register, and generates an latch signal that is activated when the bad number is greater than a value stored in the first register; A first feeder for storing the defective number into the first register in response to the latch signal; And And a second processor for storing an address of a bad row line or a bad column line corresponding to a bad number stored in the first register in a second register in response to the latch signal. Memory device. delete The method of claim 1, And the fuse element is electrically cut in response to the detection result. The method of claim 1, And the fuse element is electrically shorted in response to the detection result. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: A first selector configured to select one of the internal row address and an external row address input from the outside in response to a predetermined test control signal; A second selector for selecting any one of the internal column address and an external column address input from the outside in response to the test control signal; And And a third selector for selecting any one of the test data and external data input from the outside in response to the test control signal. delete A memory cell array for storing data, comprising: a plurality of row lines, a plurality of column lines, at least one redundancy row line for replacing a defective one of the row lines, and a defective column among the column lines An automatic test and automatic repair method performed in a semiconductor memory device having the memory cell array including at least one redundancy column line for replacing a line. (a) generating test data and writing the test data into each memory cell of the memory cell array; (b) reading data from each memory cell of the memory cell array; (c) comparing the read data with the data written in step (a), respectively; (d) detecting, based on the comparison result of step (c), a bad row line among the row lines and a bad column line among the column lines, and outputting the detection result; And (e) using the detection result obtained in step (d), replacing the defective row line with a redundancy row line and replacing the defective column line with a redundancy column line, The automatic test and repair method of the semiconductor memory device may be performed before step (d). (pd1) generating inverted data of the test data and writing them to each memory cell of the memory cell array; (pd2) reading data from each memory cell of the memory cell array; And (pd3) further comparing the read data with the data written in the step (pd1), Step (d) Based on the comparison result of step (c) and the comparison result of step (pd3), the largest bad row line or the largest bad column line including the most bad memory cell among the bad row line and the bad column line. And outputting an address corresponding to the maximum bad row line or the maximum bad column line as the detection result. The method of claim 13, wherein step (a) and step (b) Generating an internal row address specifying the row line to access the memory cells; And And generating an internal column address specifying the column line to access the memory cells. The method of claim 13, wherein step (e) (e1) electrically activating a fuse device responsive to the detection result; (e2) checking the state of the fuse device; (e3) repeating steps (e1) to (e2) a predetermined number of times if the fuse device is not in an active state; (e4) after the step (e3), if the fuse device is not in an active state, setting the fuse device to an unused state and performing steps (a) to (d) again; (e5) determining whether a bad memory cell exists based on the result of step (e4); (e6) if it is determined in step (e5) that the bad memory cell does not exist, determining it as a pass; And (e7) if it is determined in step (e5) that a bad memory cell is present, the automatic test and repair method of a semiconductor memory device comprising the step of determining as a fail. The method of claim 15, wherein step (e1) And automatically cutting the fuse device. The method of claim 15, wherein step (e1) And electrically shorting the fuse device.