KR100268787B1 - Repair method of semiconductor apparatus - Google Patents

Abstract

PURPOSE: A repairing method of a memory device is provided to give the advantage without using a process of cutting off a fuse and requiring an additional process by comparing an address to be applied with a previously latched address to select a repair word line, if the address and the previously latched address are equal. CONSTITUTION: Write data and read data are compared to each other through operations of a writing and a reading for each cell. Using the comparison result, it is determined whether each memory cell has a defect generated. When the write and read data are same to each other, a normal word line is selected while an address signal corresponding to the normal word line is not latched to a latch. Otherwise, the address signal corresponding to the normal word line is latched to the latch. The latched address signal is compared with an address signal inputted from the external. When the latched address signal and address signal are equal, a repair word line is selected and activated.

Description

How to Repair a Memory Device

The present invention relates to a repairing method of a memory device. In particular, when a capacity of a RAM memory is checked, a damaged cell is detected by a row address and the address is latched, and then the applied address is compared with an already latched address. A repair method of a memory device to select a repair word line.

In general, if any one of a number of memory cells is defective, the memory device will not function properly. However, if the cell of the memory device is defective and disposed of, the yield is reduced.

In order to solve this problem, a defective cell in the memory cell is generally replaced with a spare memory cell prepared for repair. This redundant memory cell is selected by the repair word line instead of the normal word line that selects the normal memory cell.

That is, in the conventional case, when an address associated with a normal memory cell is applied, a normal word line is selected to operate the memory device. When an address associated with a defective cell is applied, a repair performing signal is enabled and thus a repair word line is performed. The signal to select is enabled to select the repair word line.

However, in order to perform the repair operation for selecting the repair word line described above, there is a problem in that a process of selecting and cutting a fuse connected to a row address designating a damaged word line is required.

Accordingly, an object of the present invention is to detect a row address of a damaged cell when latching a capacity of a RAM memory and latch this address, and then select a repair word line if both are identical by comparing an address applied thereafter with an already latched address. It is to provide a repair method of a memory device that does not require a cutting process of the fuse.

1 is an address latch circuit of a memory device of the present invention for latching an address of a cell to be repaired.

2 is a block diagram illustrating the operation of a memory device according to the present invention including the address latch circuit of FIG.

* Explanation of symbols for main parts of the drawings

ax01, ax12, ax23, ...: Row address 20: NRD circuit

In order to achieve the above object, the present invention provides a repair method of a memory device, wherein each memory cell is equally determined by comparing the read and read data through a write and read operation for each memory cell when checking memory capacity. According to the first step of determining whether or not a defect has occurred, if the write and read data is the same, the address is not latched to the address latch means so that a normal word line is selected when the write and read data are the same. On the other hand, if the written and read data are not the same, a second step of controlling the corresponding address to be latched to the address latching means, and an address signal applied from the outside through the second step is applied to the latched address. The two address signals are moved through a third step of comparing with the signal and the third step. In one case, a fourth step of selecting and activating a repair word line is provided.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

1 shows an address latch circuit of a memory device of the present invention which latches an address of a cell to be repaired.

In relation to the operation of the memory device of the present invention, when the memory device is first operated, the capacity of the memory device is checked through read and write operations on all memory cells. That is, for checking the memory device, a row address for selecting a word line is activated. Then, the column address is activated to select a cell connected to the word line. At this time, data is written and read into a memory cell corresponding to the row address and the column address that are activated to check the capacity of the first memory device to compare whether the data is the same. These are shown in part B of FIG. As illustrated, when the data write_data written to the memory cell and the read_data read from the memory cell are not the same, transistors respectively receiving the write_data and read_data data signals through the gates are turned on and positioned in the C region of FIG. 1. The high voltage Vpp is applied to the gate of the NMOS transistor. Therefore, the NMOS transistor in the C region is turned on. Thus, as shown in FIG. 1, the defective row address is applied to the latch means (denoted as area A) and latched through the above process.

After the initial checking process of the above-described memory device is completed, the memory device enters a normal operation mode state. At this time, when the row address previously latched with respect to the defective cell and the address applied subsequently are the same, the NAND element located in the region D of FIG. 1 outputs a logic row.

The output logic low signal selects the repair word line.

That is, as shown in FIG. 2, which is a configuration diagram for explaining the operation of the memory device including the address latch circuit, the NAND output signal of FIG. 1 is applied to the gate of the corresponding pull-down transistor of the NRD output circuit section. Therefore, when a NAND output signal of a logic low is applied to the gate of the pull-down transistor made of a PMOS transistor, the pull-down transistor is turned on and nrd, which is an output signal of the NRD circuit part, becomes a logic low to select a repair word line.

At this time, when the compared address is different from the latched address, the output of the NAND gate becomes logic high, and the pull-down transistor is turned off. Therefore, in this case, nrd, which is an output signal of the NRD circuit portion, becomes logic high to select a normal word line.

As described above, in the related art, in order to perform a repair operation, there is a problem in that each fuse connected to an address corresponding to a bad cell has to be cut, and a repair mask for this purpose is additionally required, and thus additional costs and additional processes are required. There was a problem required.

However, the present invention detects a row address of a damaged cell and latches this address when checking a capacity of a RAM memory, and then selects a repair word line if the applied addresses are compared with an already latched address and both are identical. There is an advantage that the cutting of the fuse and its additional process are unnecessary.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (1)

A repairing method of a memory device, comprising: a first step of determining whether or not a defect occurs in each memory cell by comparing the read and read data through a write and read operation with respect to each memory cell during a memory capacity check And if the write and read data are the same, the address is not latched to the address latching means so that a normal word line is selected while the write and read data are the same. A second step of controlling the corresponding address to be latched to the address latching means if not the same; a third step of comparing an address signal applied from the outside with the latched address signal through the second step; If the two address signals are the same through the third step, the repair word line is selected. And a fourth step of activating the memory device.

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