KR20010019340A - Non-volatile semiconductor memory apparatus and method for testing thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device having a function to reduce a test time and a test method thereof are provided to reduce the test time by testing a main cell array and a redundant cell array at the same time. CONSTITUTION: The semiconductor memory device includes a main memory cell array(10), a redundant cell array(12), a row decoder(14), a repair redundant column decoder(18), a column address counter(20), a column decoder(22), a test redundant column decoder(24) and a test command latch(26). The column address counter increases a column address from A0-A7 to A0-A8 in order for not only the main memory cell array but also the redundant cell array to be designated, and enables the test redundant column decoder only in case that there is a test command. Therefore, the main memory cell array is selected by 0-255, and the redundant cell array is selected by 256-259. Because the test step is accomplished before a pre-laser step, a fuse of the repair redundant column decoder is not blown completely and thus maintains a disabled state.

Description

Non-volatile semiconductor memory device and test method with reduced test time {NON-VOLATILE SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR TESTING THEREOF}

The present invention relates to a nonvolatile semiconductor memory device and a test method having a test time shortening function. In particular, the present invention includes a test redundant column decoder to test a redundant cell array at the time of a cell array test, thereby reducing test time. A nonvolatile semiconductor memory device having a shortening function and a test method are provided.

The rapid development of semiconductor technology has resulted in very high integration of semiconductor integrated circuits, especially in the field of memory devices with EEPROM cell arrays. As the ultra-high integration of memory devices has been achieved, the failure rate of memory cell arrays has increased, and the redundant repair technology for replacing the defective cells has been developed in various ways.

In general, a test of a memory EEPROM cell mainly writes and reads substantial data directly to the cell to determine whether there is a defect. At this time, the defect of EEPROM cell occurs in various types according to the process of making memory. Such defects of memory increase as the capacity of the memory increases.

In order to regulate this defect, an extra redundant cell is made in advance and the defective main cell is replaced.

1 shows a configuration of a conventional nonvolatile memory device. Main memory cell array 10, redundant cell array 12. The row decoder 14, the column address counter 16, the redundant column decoder 18, and the column decoder 20 are included.

In order to repair low or column defects, a low redundant cell array and a column redundant cell array are prepared.

When a low defect occurs in the NAND type flash memory, repair is performed in units of blocks of several pages. In this case, the defect of the EEPROM cell of the redundant block is checked in the same manner as the main memory cell.

However, in order to inspect column redundancy cells, writes and reads in the same page unit as the main memory cells must be performed. When such a test is performed, the time for inspecting the column redundant cell array 12 is the same as that of the main memory cell array 10. As a result, the disadvantage is that the test time must be doubled as a result.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device and a test method which can shorten a test time by simultaneously testing a redundant cell array and a main memory cell array in order to solve the problems of the related art.

1 is a diagram showing the configuration of a conventional nonvolatile semiconductor memory device.

2 is a diagram showing the configuration of a nonvolatile semiconductor memory device having a test time reduction function according to the present invention;

3 is a circuit diagram illustrating an example of a test redundant column decoder according to the present invention;

4 is a diagram showing the configuration of the final address detection circuit according to the present invention;

<Description of the code | symbol about the principal part of drawing>

10: cell array 12: redundant cell array

14: row decoder 18: repair redundant column decoder

20: column address counter 22: column decoder

24: test redundant column decoder 26: test instruction latch

In order to achieve the above object of the present invention, the apparatus of the present invention provides a main cell array, a redundant cell array, a column address counter for designating the main cell array and a redundant cell array, and a main column address provided from the column address counter. A column decoder to decode, a test redundant column decoder to decode a redundant column address provided from the column address counter to test the redundant cell array with the main cell array in a test mode, and a bad cell of the main cell array. Repair for decoding the corresponding column address provided from the column address counter, blocking at the column decoder, and providing to the redundant cell array by a fuse option that replaces the normal cell of the redundant cell array. And a redundant column decoder.

Here, the nonvolatile semiconductor memory device detects the last column address of the normal mode to generate a first detection signal, detects the last column address of the test mode to generate a second detection signal, and responds to the test mode. Or final column address detection means for outputting the second detection signal as a final column address detection signal.

A method of the present invention is a nonvolatile semiconductor memory device having a main cell array and a redundant cell array, the method comprising: generating a column address for designating both the main cell array and the redundant cell array; Decoding the column address of the main cell array by means of decoding, and decoding the column address of the redundant cell array by means of a redundant column decoder.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

2 shows a configuration of a nonvolatile semiconductor memory device having a test time reduction function according to the present invention. In FIG. 2, the memory device includes a main memory cell array 10, a redundant cell array 12, a row decoder 14, a repair redundant column decoder 18, a column address counter 20, a column decoder 22, a test redundant. Column decoder 24 and test instruction latch 26.

In the present invention, as shown in the following table according to the test command indicates the operating state

Test command Enable Disable A8 One 0 One 0 Used decoder Test Redundant Column Decoder Column decoder Repair redundant column decoder and column decoder Inspection process Free laser Post EDS Process

For example, the column address counter 20 increases the column address from A0 to A7 to A0 to A8 so that not only the main memory cell array but also the redundant cell array is specified, and the test redundant column decoder is enabled only when there is a test command. do. Therefore, the main memory cell array is selected by 0 to 255, and the redundant cell array is selected by 256 to 259.

Since the test step is performed before the pre-laser, the fuses of the repair redundant column decoder 18 are not cut and thus remain disabled.

3 shows an example of a test redundant column decoder according to the present invention.

The test column redundant column decoder 24 generates an enable signal by NAND combining the test command TEST and the column address signal A8. The four NOR gates NOR1 to NOR4 input column addresses A0, A1, A0B, A1, A0, A1B, AOB, and A1B, respectively, so that the column line selection signals RA0, RA1, RA2, Each occurrence of RA3).

The NAND type EEPROM performs an automatic verification operation internally at the time of page write or block erase. At this time, since the column address is used, the size of the column address is different at the time of pre laser sorting and after the repair process. Therefore, since the size of the column address is different, a circuit for checking the last address must be provided.

4 shows the configuration of the final address detection circuit according to the present invention.

In FIG. 4, the last address detecting circuit detects the last column address in the normal mode and generates the first detection signal FYADDN, and the second column detects the last column address in the test mode. Second detection means 34 for generating a signal FYADDT and output means 36 for outputting the first or second detection signal as a final column address detection signal FYADD in response to a test mode.

The second detection means 34 includes inverters INV5 to INV8, NOR gates NOR6 and NOR7, and NAND gates NAND3. In the test mode, the second detecting unit 34 generates the final address detection signal FYADDT in the low state when A0, A1, and A8 are all high.

The output means 36 includes inverters INV3, INV4, NOR gate NOR5, and NAND gate NAND2. The output means 36 cuts off the last address detection signal FYADDN provided from the first detection means 32 in the test mode and causes FYADDT to be output to FYADD. In contrast, in normal mode, FYADDN is output as FYADD.

As described above, in the present invention, the value of the column address counter is increased so that not only the main cell array but also the redundant cell array can be designated, and a test redundant column decoder is provided so that the main cell array and the redundant cell array are simultaneously specified in the test mode. By doing this, the test time can be reduced by almost half of the conventional test method.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

Main cell array; Redundant cell arrays; A column address counter for designating the main cell array and the redundant cell array; A column decoder for decoding a main column address provided from the column address counter; A test redundant column decoder for decoding a redundant column address provided from the column address counter to test the redundant cell array with the main cell array in a test mode; And Decode the corresponding column address provided from the column address counter, block at the column decoder, and provide to the redundant cell array by a fuse option that replaces the defective cell of the main cell array with the normal cell of the redundant cell array. Non-volatile semiconductor memory device having a test time reduction function characterized in that it comprises a repair redundant column decoder for. The nonvolatile semiconductor memory device of claim 1, wherein Detects the last column address in the normal mode to generate a first detection signal, detects the last column address in the test mode to generate a second detection signal, and responds to the test mode to convert the first or second detection signal into a final column And a final column address detection means for outputting the address detection signal. The method of claim 2, wherein the last column address detecting means First detection means for detecting a final column address in a normal mode to generate a first detection signal; Second detection means for detecting a final column address in a test mode to generate a second detection signal; And And output means for outputting the first or second detection signal as a final column address detection signal in response to a test mode. A nonvolatile semiconductor memory device having a main cell array and a redundant cell array, Generating a column address for designating both the main cell array and the redundant cell array; And And in the test mode, decoding a column address of the main cell array by a column decoder and decoding a column address of the redundant cell array by a redundant column decoder. .