KR20030058256A - Flash memory device and repairing method thereof - Google Patents

Abstract

PURPOSE: A flash memory device and a method for repairing the same are provided to reduce the occurrence of failure during the manufacturing process, to reduce the chip size and to repair at the consumer's level. CONSTITUTION: A flash memory device includes a word line decoder block(110), a failure address register(100), a comparison block(90), a flash cell array block(120), a plurality of sense amplifiers(150) and a data buffer block(160). In the flash memory device, the failure address register(100) stores the data of the failure address storage cell array. And, the comparison block(90) compares the data of the failure address register with the inputted address and outputs the redundancy enable signal in response to the comparison result.

Description

Flash memory device and repair method thereof

TECHNICAL FIELD The present invention relates to semiconductor memories, and more particularly, to flash memory devices, and more particularly, to redundancy circuits and repair methods of flash memory devices.

In general, in order to solve a problem in which a chip does not operate normally when a defect occurs in some memory cells in a semiconductor memory device, an extra memory cell is made in advance and a defective cell is left after the test. In this case, the spare cell is called a spare cell, and a circuit that participates in such a replacement operation is called a redundancy circuit.

Once the test is performed, the internal circuit is programmed to select the bad memory cell and replace the corresponding address with the address signal of the spare cell. Therefore, when the address corresponding to the bad line is input in actual use, it is selected as a spare line instead. Will change. The program method is an electric fuse method that melts and blows a fuse with an overcurrent, a method of burning a fuse with a laser beam, and a method of shorting a junction with a laser beam. have.

1 is a block diagram of a flash memory device according to the prior art.

Referring to FIG. 1, a flash memory device according to the related art selects a flash cell array unit 20 including a redundancy cell array 30, and decodes an address to select a specific word line of the flash cell array unit 20. For detecting and amplifying data of the normal bit line or the redundancy bit line of the flash cell array unit 20 during a read operation, and for sensing and amplifying input data during a program operation to drive the bit line. A data buffer unit for buffering the plurality of sense amplifiers 40 and the data output from the sense amplifier 40 to output the data DATA_OUT, and buffering the input data DATA_IN to the sense amplifier 40. 80 is provided.

On the other hand, the flash memory device according to the prior art, in addition to the redundancy cell array 30 for cell repair, a bad address storage flash cell array unit 50 for storing the address of the cell in which the bit line failure has occurred, and the bad address therefrom. And a comparator unit 70 for comparing the input address with a bad address outputted from the bad address detection amplifier group 60.

In the conventional flash memory device having the above-described configuration, when the input address is determined to be a bad address, the flash memory device activates the redundancy enable signal EN to change the path of the data corresponding to the bad address toward the redundancy cell array 30 so as to program the same. Or perform a read.

However, in the prior art, the flash cell array unit 50 for storing the defective address is separated from the flash cell array unit 20, causing a defect in the process, and since the number of detection amplifiers is required as many as the number of the defective addresses, the chip There was a problem to increase the size of. In addition, when a chip is inspected and a defect occurs during the use of a consumer, there is a disadvantage in that repair is no longer possible.

The present invention has been proposed to solve the above problems of the prior art, a flash memory device having a redundancy structure capable of reducing defects during a process, reducing the size of a chip, and capable of repair at a consumer level, and a repair method thereof. The purpose is to provide.

1 is a block diagram of a flash memory device according to the prior art.

2 is a block diagram of a flash memory device according to an embodiment of the present invention.

3 is a flow chart for a defective flashcell repair in accordance with the present invention.

* Explanation of symbols for the main parts of the drawings

90: comparator donation

100: bad address register

140: flash cell array unit for storing bad address

According to an aspect of the present invention for achieving the above technical problem, in a flash memory device comprising a normal cell array, a redundancy cell array, and a bad address storage cell array, the data of the bad address storage cell array There is provided a flash memory device having a bad address register for storing a data, and a comparison means for comparing an input address with data of the bad address register and outputting a redundancy enable signal according to the result.

According to another aspect of the present invention, there is provided a cell repair method of a flash memory device, the method comprising: programming a predetermined test pattern in the normal cell array; Inspecting the programmed normal cell array; Programming an address of a defective cell of the normal cell array into the defective address storage cell array; Examining the programmed bad address storage cell array; Writing data of the bad address storage cell array to the bad address register; Programming a redundancy cell corresponding to the bad address; And inspecting the programmed redundancy cells.

The present invention includes a flash cell array for storing a defective address in a normal flash cell array, and stores the data (bad address) of the defective address storing flash cell array in a bad address register, thereby enabling a defective remedy of a flash cell in a software manner. It was made. In this case, since there is no separate flash cell array for storing the defective address, the possibility of defects can be reduced during the process, and the size of the chip can be reduced because the sensing amplifier for the defective address is not required. On the other hand, by introducing a software repair method, consumers can perform repairs directly.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2 is a block diagram of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 2, the flash memory device according to the present embodiment may include a flash cell array unit 120 including a redundancy cell array 130 and a bad address storage flash cell array unit 140, and a flash cell by decoding an address. The word line decoder 110 for selecting a specific word line of the array unit 120, and detects and amplifies data of the normal bit line or the redundancy bit line of the flash cell array unit 120 during a read operation, and during a program operation. A plurality of sense amplifiers 150 for driving the bit lines by sensing and amplifying the input data, buffers the data output from the sense amplifier 150 and outputs them as output data DATA_OUT, and buffers the input data DATA_IN It is provided with a data buffer unit 160 for transmitting to the sense amplifier 150.

On the other hand, the flash memory device according to the present embodiment, in addition to the defective address storage flash cell array unit 120 and the redundancy cell array 130 for storing the address of the cell in which the above-mentioned bit line fail for cell repair. And a bad address register 100 for storing data (bad address) of the flash cell array unit 140 for storing a bad address, and a comparator unit 90 for comparing the information of the bad address register 100 with the input address. ).

3 is a flowchart illustrating a repair of a defective flash cell according to the present invention. Hereinafter, the repair process of the flash cell shown in FIG. 2 will be described with reference to the flowchart.

Referring to FIG. 3, first, a predetermined test pattern is programmed into the flash cell array unit 140 (31), and the flash cell array unit 140 is inspected (32). After that, it is checked whether there is a failure (fail) (33), and if a failure does not occur, it is classified as a good chip (41). If a failure occurs, the defective address is stored in the flash cell array unit 140 for storing a defective address. (34).

Next, the programmed defective address storage flash cell array unit 140 is read to check whether the defective address is correctly programmed (35). Thereafter, the path is checked (36), and if it is not a pass, it is classified as a bad chip (42). In the case of a pass, data (bad address) of the flash cell array unit 140 for storing a bad address is stored as a bad address register. (100) (37).

Subsequently, a redundancy cell corresponding to the bad address is programmed (38), and the redundancy cell is checked (39). After that, it checks whether or not the pass (40) is classified as a good chip (41), and if it is not a pass (42).

In this case, when a redundancy cell corresponding to a bad address is programmed, when an address is input, the comparator 90 compares it with data (bad address) stored in the bad address register 100 so that redundancy is enabled. The signal EN is activated, and the program path is changed to the redundancy cell array 130. In addition, even when the redundancy cell corresponding to the bad address is inspected, the redundancy enable signal EN is activated through the above process, and the read path is changed to the redundancy cell array 130.

The MCU using the flash memory of the present invention reads the bad address storage flash cell array unit 140 into the main program and then writes the data (bad address) of the bad address storage flash cell to the bad address register 100. After the addition, the defective flash cell is automatically changed to the redundancy cell array 130 to perform a program and read operation.

As described above, since the present invention does not provide a separate flash cell array for storing a defective address, a possibility of a defect may be reduced during the process, and the size of the chip may be reduced since a separate detection amplifier for the defective address is not required. On the other hand, by introducing a software repair method, consumers can perform repairs directly.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above can reduce the possibility of failure during the process, there is an effect that can reduce the size of the chip. In addition, according to the present invention, since it is possible for the consumer to repair the flash memory directly, the life of the flash memory can be extended.

Claims (5)

A flash memory device comprising a normal cell array, a redundancy cell array, and a bad address storage cell array, A bad address register for storing data of the bad address storing cell array; Comparison means for comparing an input address with data of the bad address register and outputting a redundancy enable signal according to the result Flash memory device comprising a. The method of claim 1, And the normal cell array, the redundancy cell array, and the bad address storage cell array are integrated in one memory cell area. The method according to claim 1 or 2, And the normal cell array, the redundancy cell array, and the bad address storage cell array share at least one sense amplifier. In the cell repair method of the flash memory device of claim 1, Programming a predetermined test pattern into the normal cell array; Inspecting the programmed normal cell array; Programming an address of a defective cell of the normal cell array into the defective address storage cell array; Examining the programmed bad address storage cell array; Writing data of the bad address storage cell array to the bad address register; Programming a redundancy cell corresponding to the bad address; And Examining the programmed redundancy cells Cell repair method of a flash memory device comprising a. The method of claim 4, wherein The step of programming a redundancy cell corresponding to the bad address, Comparing the input address with data written to the bad address register; And activating the redundancy enable signal as the input address and the data written in the bad address register coincide with each other.