KR100206697B1 - Column redundancy circuit of semiconductor memory - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

Column redundancy circuit in semiconductor memory.

2. The technical problem to be solved by the invention:

It is an object of the present invention to provide a redundancy circuit that improves a fail recovery rate in a semiconductor memory employing a redundancy memory cell.

3. Summary of the solution of the invention:

A memory cell array having a left normal memory arranged in a matrix of a plurality of rows and columns and a redundancy column memory cells arranged in a plurality of columns, a redundancy column decoder connected to the redundancy column memory cells, and a normal column connected to the normal memory cells The column redundancy circuit of the semiconductor memory device includes a decoder, a redundancy sense amplifier and an output buffer connected to the redundancy column memory cells through a data bus, and a normal sense amplifier and an output buffer connected to the normal memory cells through the data bus. And controlling the data path of the output buffer when the redundancy column memory cells are selected in one column unit because they are connected between the redundancy and normal output buffers and the redundancy column predecoder and are long due to defects of the normal cells. It characterized by having the input-output control means outputs doede hanneu the redundancy data in a cell of the column through the redundancy data output buffer.

4. Important uses of the invention:

It is used in semiconductor memories employing redundancy memory cells.

Description

Column Redundancy Circuit in Semiconductor Memory

1 is a conventional general column redundancy circuit diagram,

2 is a block diagram of a column redundancy circuit according to the present invention,

3 is a detailed circuit diagram of the embodiment according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly, to a column redundancy circuit of semiconductor memories capable of improving fail rescue rates.

In general, as semiconductor memory devices are increasingly integrated and miniaturized, productivity is emphasized. In particular, memory cells are the most vulnerable to defects in production, resulting in a high yield. Several methods have been proposed to solve this problem, but the most common method is to replace defective shells with redundant cells to improve the yield of production.

In the case of such a repair scheme, a fail cell is usually replaced by row (row) or column (column). Among these, the replacement of the column unit will be described with reference to FIG.

1 shows a conventional column redundancy circuitry structure generally used.

In the memory cell array 100 arranged in row and column units corresponding to eight input / output blocks, a normal column cell and a redundancy column cell are included. In the case of FIG. 1, the number of columns per block for one input / output is 16 normal columns and one redundancy column. The memory cell array 100 is connected to the normal column decoder 200 and the redundancy column decoder 201 corresponding to the number of input / output blocks, respectively, and the normal column decoder 200 and the redundancy column decoder 201 are the normal column predecoder 300 and the redundancy column, respectively. Each is connected to the predecoder 600.

The address buffer 500 is also commonly connected to the normal column free decoder 300 and the redundancy column free decoder 600. The eight input / output circuits 400 correspond to the eight blocks in the memory cell array 100 through data buses.

In the above FIG. 1 configuration, the process of replacing with the corresponding redundancy column due to the defect of the normal cell 102 in the memory shell array 100 is as follows. When a column address specifying a defective cell in the normal memory shell 102 is input to the address buffer 500, the redundancy column predecoder 600 disables the column of the defective normal cell by a program by cutting a fuse provided therein. The signals R-EN and N-DIS are respectively output for enabling the columns of the corresponding redundancy cells. The cutting of the fuse is performed by irradiating a fuse with a laser beam in the wafer state of the memory. The normal disable signal N-DIS is applied to the normal column decoder 200 through the normal column free decoder 300, and the decoder 200 disables the corresponding normal column in response. As a result, the defective normal cell row is placed in an inoperable state when the memory is read or written. Meanwhile, the redundancy enable signal R-EN is applied to the redundancy column free decoder 201 through the redundancy column free decoder 600. As a result, the columns of the redundancy cells are enabled so that the defective normal cells are replaced with a row of redundant redundancy cells.

When the data is read by the selection of the redundancy memory cell, the data in the cell is output to the sense amplifier (not shown) through the data bus. The sense amplifier senses the data accordingly and applies the data output buffer to the redundancy. The data of the cell is output to the outside through the I / 0 circuit 400. As described above, a redundancy cell corresponding to a defect of a normal memory cell is replaced by 8 cal sword units, that is, byte units. This byte-by-byte redundancy replacement technique reduces the probability of salvage of the paycell. In other words, if any cell in the spare column being replaced has a defect, the redundancy replacement fails and does not help yield. In addition, when a large number of memory cells are defective, the number of extra columns for replacing them is at most eight times the number of defectives, which causes an increase in the area of the column redundancy memory cell blocks, thereby increasing the chip size. have. This increase in chip size eventually leads to an increase in cost.

Accordingly, an object of the present invention is to provide a column redundancy circuit of a semiconductor memory capable of improving the fail recovery rate.

Another object of the present invention is to provide a column redundancy circuit which can reduce a memory chip size in a semiconductor memory employing redundancy memory cells.

According to the present invention for achieving the above object, a memory cell array having a normal memory arranged in a matrix of a plurality of rows and columns and a redundancy column memory cells arranged in a plurality of columns, and connected to the redundancy column memory cells A redundancy column decoder and a normal column decoder connected to the normal memory cells, a redundancy sense amplifier and an output buffer connected to the redundancy column memory cells via a data bus, a normal sense amplifier connected to the normal memory cells through the data bus, and A column redundancy circuit of a semiconductor memory device including an output buffer includes a transistor element and a fuse element for internal programming according to an address of a defective cell, and is connected between the redundancy and normal output buffer and a redundancy column free decoder. Normal cell When the redundancy column memory cells are selected by one column due to the coupling, the input / output controller controls the data path of the output buffer to output the data of the redundancy cell of the corresponding column through the redundancy data output buffer. Characterized by having.

According to the technical idea of the present invention described above, the probability of salvage of a failed cell can be guaranteed and the chip size of the memory can be simplified.

Hereinafter, with reference to the accompanying drawings for a thorough understanding of the present invention will be described in detail the configuration and operation of the present invention.

The configuration according to the present invention is shown in FIG. 2, and the configuration of the embodiment according to the present invention is shown in FIG. 3 showing a specific diagram of the column redundancy circuit. In FIG. 2, the same or similar parts as those shown in FIG. 1 are provided as the same reference numerals for the convenience of understanding.

Referring to FIG. 2, a block diagram of a column redundancy circuit is shown. In FIG. 2, the memory cell array 100 is divided into a normal memory shell unit 102 and a redundancy memory cell unit 101, and the normal memory cell unit 102 corresponds to eight I / 0s, that is, one bar art, and one I / O. The number of columns per zero is eight. Here, the redundancy memory cell unit 101 is arranged separately from the normal memory cell unit 102 and a circuit, and a redundancy sense amplifier and an output buffer 360 corresponding thereto are provided separately. In FIG. 2, the operation of enabling the redundancy column decoder 201 by programming an internal fuse of the redundancy column predecoder 600 when replacing a defective normal memory cell with redundancy memory cells is the same as in the related art. In the case of the present invention, the normal column decoder 200 is not disabled. In the present invention, the I / 0 control circuit 400 has as many as the number of normal I / 0, and each of the I / 0 control circuits 400 is programmed by a fuse provided therein so as to correspond to a defective cell as shown in FIG. Disable data output buffer 361 and enable redundancy data output buffer 361. By performing such an operation, when a normal cell is defective, the normal cell, a corresponding sense amplifier and an output buffer 350 are replaced with a redundancy column cell, a corresponding redundant sense amplifier and an output buffer 360. Therefore, the one replaced by one byte unit in the related art can be replaced by one I / 0 unit.

3 shows a specific circuit of the embodiment in the case of having two redundancy column cells in the memory cell array. In FIG. 3, one I / 0 control circuit 400 includes a PMOS transistor 401, an NMOS transistor 402, and a 404 fuse 403 and 405. In FIG. One normal data output buffer 361 consists of two NAND gate N1, N2 PMOS transistors 362, 363, 366, 367, and an transistor transistor 364, 365, 368, 369. One redundancy data output buffer 351 includes two NAND gates N3, N4, and inverters INVR11, INVR12 consisting of PMOS and ANMOS transistors. In FIG. 3, signals SASi and SASi-B (where I is a natural number) refer to signals provided at the first and second output terminals of the sans amp.

The operation in the case where a specific column cell of a normal memory cell is defective will be described with reference to the configuration of FIG. First, when an address for selecting a column of defective cells is applied, the decoder 600 of FIG. 2 outputs a logic high by an internal program. In this case, all the fuses in the remaining I / 02, ..., 8 control circuits are cut except the fuses 403, 405 in the I / 0 control circuit 400 of FIG. Accordingly, since the output of the first control circuit 400 becomes logic high and the first normal data output buffer 361 is unselected, the output becomes a floating state and the redundancy of the first redundancy data output is selected because the buffer 351 is selected. Data from the sense amplifier is delivered.

Therefore, the data of the redundancy column memory cell corresponding to the defective normal cell is output from the first input / output circuit I / 01 through the transfer transistors TR1 and TR2. At this time, since the outputs of the 2-8 control circuits all output lows, the data output from the 2-8 input / output circuits come from normal memory cells.

As described above, when the defective cell is replaced by one barat unit in the related art, it is replaced by one I / 0 unit in the present invention. Thus, when the number of columns per one I / 0 is eight, Redundancy cell area can be reduced by 8 times, which can improve the fail rescue rate and reduce the memory chip size.

Claims (2)

A memory cell array having redundancy column memory cells arranged in a plurality of rows and columns arranged in a matrix of a plurality of rows and columns, a redundancy column decoder connected to the redundancy column memory cells, and a normal column connected to the normal memory cells A column redundancy circuit of a semiconductor memory device including a decoder, a redundancy sense amplifier and an output buffer connected to the redundancy column memory cells through a data bus, and a normal sense amplifier and a block buffer connected to the normal memory cells through the data bus. A transistor comprising: a transistor element and a fuse element for internal programming according to an address of a defective cell, connected between said redundancy and normal output buffer and a redundancy column predecoder, and said redundancy column mesh due to a defect of said normal cell. When the cells are selected in a column unit, the semiconductor memory having an input and output control unit for controlling the data path of the output buffer to output the data of the corresponding redundancy cell through the redundancy data output buffer Column redundancy circuit in the device. 2. The column redundancy circuit of claim 1, wherein the redundancy and normal output buffers have the same structure and are enabled with different logic levels.