KR970051416A - Column Redundancy Circuit in Semiconductor Memory - Google Patents

Column Redundancy Circuit in Semiconductor Memory Download PDF

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Publication number
KR970051416A
KR970051416A KR1019950054753A KR19950054753A KR970051416A KR 970051416 A KR970051416 A KR 970051416A KR 1019950054753 A KR1019950054753 A KR 1019950054753A KR 19950054753 A KR19950054753 A KR 19950054753A KR 970051416 A KR970051416 A KR 970051416A
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KR
South Korea
Prior art keywords
redundancy
column
memory cells
normal
output buffer
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KR1019950054753A
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Korean (ko)
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KR100206697B1 (en
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김창래
곽충근
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김광호
삼성전자 주식회사
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Priority to KR1019950054753A priority Critical patent/KR100206697B1/en
Publication of KR970051416A publication Critical patent/KR970051416A/en
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Publication of KR100206697B1 publication Critical patent/KR100206697B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리의 칼럼 리던던시 회로.Column redundancy circuit in semiconductor memory.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

리던던시 메모리 셀을 채용하는 반도체 메모리에서 페일 구제율을 개선하는 리던던시 회로를 제공함에 있다.It is an object of the present invention to provide a redundancy circuit that improves a fail recovery rate in a semiconductor memory employing a redundancy memory cell.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

복수 개의 행과 열의 매트릭스 형으로 배열된 노말 메모리 및 다수의 열로 구분 배열된 리던던시 칼럼 메모리 셀들을 가지는 메모리 셀 어레이와, 상기 리던던시 칼럼 메모리 셀들에 연결된 리던던시 칼럼 디코더와, 상기 노말 메모리 셀들에 연결된 노말 칼럼 디코더와, 상기 리던던시 칼럼 메모리 셀들의 데이타 버스를 통해 연결된 노말 센스 앰프 및 출력버퍼를 포함하는 반도체 메모리 장치의 칼럼 리던던시 회로는, 상기 리던던시 및 노말 출력버퍼와 리던던시 칼럼 프리 디코더간에 연결되며 상기 노말 셀의 결함에 기인하여 상기 리던던시 칼럼 메모리 셀들이 하나의 칼럼 단위로 선택되는 경우에 상기 출력버퍼의 데이타 통로를 제어하여 상기 대응되는 칼럼의 리던던시 셀의 데이타가 상기 리던던시 데이타 출력버퍼를 통해 출력되게 하는 입출력 제어수단을 가짐을 특징으로 한다.A memory cell array having redundancy column memory cells arranged in a plurality of rows and columns arranged in a matrix of a plurality of rows and columns, a redundancy column decoder connected to the redundancy column memory cells, and a normal column connected to the normal memory cells A column redundancy circuit of a semiconductor memory device including a decoder and a normal sense amplifier and an output buffer connected through a data bus of the redundancy column memory cells is connected between the redundancy and normal output buffers and a redundancy column free decoder and When the redundancy column memory cells are selected by one column due to a defect, the data passage of the output buffer is controlled so that data of the redundancy cell of the corresponding column is output through the redundancy data output buffer. It characterized by having a control means.

4. 발명의 중요한 용도4. Important uses of the invention

리던던시 메모리 셀을 채용하는 반도체 메모리에 사용된다.It is used in semiconductor memories employing redundancy memory cells.

Description

반도체 메모리의 칼럼 리던던시 회로Column Redundancy Circuit in Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 칼럼 리던던시 회로의 블럭 구성도이며,2 is a block diagram of a column redundancy circuit according to the present invention,

제3도는 제2도에 따른 실시예의 세부회로 구성도이다.3 is a detailed circuit diagram of the embodiment according to FIG.

Claims (3)

복수 개의 행과 열의 매트릭스 형으로 배열된 노말 메모리 및 다수의 열로 구분 배열된 리던던시 칼럼 메모리 셀들을 가지는 메모리 셀 어레이와, 상기 리던던시 칼럼 메모리 셀들에 연결된 리던던시 칼럼 디코더와, 상기 노말 메모리 셀들에 연결된 노말 칼럼 디코더와, 상기 리던던시 칼럼 메모리 셀들에 데이타 버스를 통해 연결된 리던던시 센스 앰프 및 출력버퍼와, 상기 노말 메모리 셀들에 상기 데이타 버스를 통해 연결된 노말 센스 앰프 및 출력버퍼를 포함하는 반도체 메모리 장치의 칼럼 리던던시 회로에 있어서; 상기 리던던시 및 노말 출력버퍼와 리던던시 칼럼 프리 디코더간에 연결되며 상기 노말 셀의 결함에 기인하여 상기 리던던시칼럼 메모리 셀들이 하나의 칼럼 단위로 선택되는 경우에 상기 출력버퍼의 데이타 통로를 제어하여 상기 대응되는 칼럼의 리던던시 셀의 데이타가 상기 리던던시 데이타 출력버퍼를 통해 출력되게 하는 입출력 제어수단을 가짐을 특징으로 하는 반도체 메모리 장치의 칼럼 리던던시 회로.A memory cell array having redundancy column memory cells arranged in a plurality of rows and columns arranged in a matrix of a plurality of rows and columns, a redundancy column decoder connected to the redundancy column memory cells, and a normal column connected to the normal memory cells A redundancy sense amplifier and an output buffer connected to the redundancy column memory cells via a data bus, and a normal sense amplifier and an output buffer connected to the normal memory cells through the data bus. In; The redundancy and normal output buffer is connected between the redundancy column predecoder, and when the redundancy column memory cells are selected by one column due to the defect of the normal cell, the corresponding data path of the output buffer is controlled to control the corresponding column. And an input / output control means for causing the data of the redundancy cells of the to be output through the redundancy data output buffer. 제1항에 있어서, 상기 입출력 제어수단은 결함난 셀의 어드레스에 따른 내부 프로그램을 위해 퓨즈소자를 가짐을 특징으로 하는 반도체 메모리 장치의 칼럼 리던던시 회로.The column redundancy circuit of claim 1, wherein the input / output control unit has a fuse element for an internal program according to an address of a defective cell. 제1항에 있어서, 상기 리던던시 및 노말 출력버퍼의 구조는 서로 동일하며, 서로 반대의 논리레벨로 인에이블되어 활성화됨을 특징으로 하는 반도체 메모리 장치의 칼럼 리던던시 회로.2. The column redundancy circuit of claim 1, wherein the redundancy and normal output buffers have the same structure and are enabled with different logic levels. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950054753A 1995-12-22 1995-12-22 Column redundancy circuit of semiconductor memory KR100206697B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950054753A KR100206697B1 (en) 1995-12-22 1995-12-22 Column redundancy circuit of semiconductor memory

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Application Number Priority Date Filing Date Title
KR1019950054753A KR100206697B1 (en) 1995-12-22 1995-12-22 Column redundancy circuit of semiconductor memory

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KR970051416A true KR970051416A (en) 1997-07-29
KR100206697B1 KR100206697B1 (en) 1999-07-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100313515B1 (en) * 1999-07-26 2001-11-15 김영환 Column redundancy circuit for semiconductor memory
KR20020019171A (en) * 2000-09-05 2002-03-12 윤종용 Column redundancy circuit of semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100313515B1 (en) * 1999-07-26 2001-11-15 김영환 Column redundancy circuit for semiconductor memory
KR20020019171A (en) * 2000-09-05 2002-03-12 윤종용 Column redundancy circuit of semiconductor memory device

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Publication number Publication date
KR100206697B1 (en) 1999-07-01

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