JPH0660693A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To inspect whether a defective storage cell exists in a redundancy relief storage cell or not before its redundancy relief. CONSTITUTION:A redundancy relief storage cell inspecting decoder 9 is provided for redundancy relief storage cells 2, 3 for replacing a defective storage cell in a normal storage cell array 1. When an activation signal (k) is input to a test terminal 12 of the decoder 9, an operation of the array 1 is inhibited. When an address signal A from a row address input terminal 10 and an inverting signal (a) are input to the decoder 9, signals (i), (j) for selecting the cell 2 or 3 and activation signals (f), (g) are output in response to a level of the signal, and the cell 2, 3 is inspected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundancy repair circuit.

[0002]

2. Description of the Related Art In recent years, the capacity of memories has been increasing due to the progress of integration technology. On the other hand, however, it becomes very difficult to manufacture a memory cell array that does not include even one defective bit due to the increase in capacity. It has become to. For such a problem, a technique is used in which a spare memory cell array is provided in advance, and if a defective bit exists in the normal memory cell array, it is replaced with the defective bit. This technique is called a so-called redundant relief technique.

A semiconductor memory device having a conventional redundancy repair circuit will be described below. FIG. 3 is a block diagram showing a configuration of a semiconductor memory device having a conventional redundant circuit system. In the figure, 1 is a normal memory cell array, 2 and 3
Is a redundancy repair memory cell, 4 is a normal row (word line) decoder, 5 is a spare decoder used for redundancy repair memory cell 2, 6 is a spare decoder used for redundancy repair memory cell 3, and 7 is a spare Fuse element for decoder 5, 8 is fuse element for spare decoder 6, 10, 1
1 is a row address input terminal, a and b are inversion signals of the signal input to the row address input terminal, c is an activation signal for selecting the redundancy repair memory cell 2, and d is the redundancy repair memory cell 3. An activation signal for selection, e is a prohibition signal for prohibiting the operation of the normal memory cell array 1 when one of the redundancy repair memory cells 2 and 3 is selected, and 2
Reference numerals 0 and 21 are inverters, and 22 is a 2-input AND.

A flow of redundancy relief of the semiconductor memory device having the redundancy relief circuit configured as described above will be described. First, a row address is input to the row address input terminals 10 and 11 to check whether or not there is a defective memory cell in the normal memory cell array 1. As a result, if there is a defective memory cell in the normal memory cell array 1, the fuse elements 7 and 8 are used so that the redundant relief memory cells 2 and 3 having higher priority are replaced in this order in accordance with the replacement priority. Program the address containing the defective memory cell. For example, the regular memory cell array 1
The redundant relief memory cell 2 for the defective memory cell in
The fuse element 7 is used to program the row address including the defective memory cell so as to replace the row address.

Thus, when a row address including a defective memory cell is input, a selection prohibition signal e is output to the normal row decoder 4 so that the defective memory cell in the normal memory cell array 1 is not selected. At the same time, the activation signal c is output from the spare decoder 5 to the redundant relief memory cell 2, and the memory cell in the redundant relief memory cell 2 is selected.

[0006]

However, in the conventional semiconductor device, as described above, when defective memory cells exist in the normal memory cell array 1, the priority order for replacing the redundant relief memory cells 2 and 3 is high. The defective memory cell is replaced according to the above. Therefore,
There are defective memory cells in the normal memory cell array 1,
Moreover, for example, if a defective memory cell exists in the redundant relief memory cell 2 that is preferentially replaced, a defective memory will exist even after the redundant relief.

As described above, if the replacement with the redundant relief memory cell including the defective memory cell is performed according to the replacement priority, there is a problem that the defective memory cell exists even after the redundant relief. In the above case, if replaced with the redundant relief memory cell 3, the defective memory cell does not exist after the redundant relief and can be made into a good product. However, whether the defective memory cell exists in the redundant relief memory cell is determined after the redundant relief. Since it is determined by the inspection of 1., it takes extra inspection time, and in some cases, inspection may be performed after the assembly is carried out. Therefore, there is a problem that extra manufacturing cost is added.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of inspecting whether or not there is a defective memory cell in the memory cell for redundancy relief before the redundancy relief.

[0009]

A semiconductor memory device of the present invention is a semiconductor memory device in which a plurality of redundant relief memory cells for replacing defective memory cells in a regular memory cell array are provided in parallel with a regular memory cell array. Therefore, the inspection circuit for inspecting the redundancy repair memory cell is provided.

[0010]

According to the structure of the present invention, since the inspection circuit for inspecting the redundant relief memory cell is provided, the redundant relief memory cell can be inspected before performing the redundant relief, and the normal memory When replacing a defective memory cell in the cell array with a redundant relief memory cell, the redundant relief memory cell including the defective memory cell is excluded, and the redundant relief memory cell not including the defective memory cell is used for the redundant relief. be able to. Therefore, the redundancy repair rate can be increased, and the extra inspection time and the extra cost after the redundancy repair can be reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, and the same reference numerals as those in FIG. In this embodiment, a redundancy relief memory cell inspection decoder 9 is provided for the redundancy relief memory cells 2 and 3, and the redundancy relief memory cell inspection decoder 9 receives an input from the row address input terminal 10. The signal A and its inverted signal a, and the test decoder 9 from the test terminal 12
An activation signal k for activating is input.

With respect to these input signals, the redundancy relief memory cell inspection decoder 9 outputs an inhibition signal h for inhibiting the operation of the normal memory cell array 1 at the time of inspection of the redundancy relief memory cell described later, and a redundancy relief memory cell at the time of inspection. A selection signal i for selecting the memory cell 2 and a selection signal j for selecting the redundant relief memory cell 3 at the time of inspection are output. The inhibition signal h is an activation signal c for selecting the redundancy repair memory cells 2 and 3 output from the spare decoders 5 and 6.
It is input to the 3-input AND circuit 23 together with d. The selection signal i is sent to the 2-input AND circuit 24 together with the activation signal c, and the selection signal j is sent to the 2-input AND circuit 25 together with the activation signal d.
To enter.

FIG. 2 is a circuit diagram showing a specific structure of the redundancy repair memory cell inspection decoder 9. In FIG. 2, 13, 14 and 15 are inverters, 16 and 17 are 2-input NAND circuits, and FIG. Reference numeral 18 is a pull-down resistor.
The operation of the semiconductor memory device including the redundancy repair memory cell array inspection circuit configured as described above will be described below.

When inspecting the normal memory cell array 1 for a defective memory cell, the redundancy relief memory cell 2,
Inspection is also performed on 3. First, when the H level activation signal k is input to the test terminal 12, the selection prohibition signal h output from the inverter 13 is L level in response to this input signal.
Therefore, the operation of the normal memory cell array 1 is prohibited. Further, the output of the inverter 15 becomes H level, and 2 inputs N
The outputs of the AND circuits 16 and 17 are determined by the other input. In this state, when the H-level address signal A is input to the row address input terminal 10, the inverted signal a thereof becomes L-level, the selection signal i output from the NAND circuit 16 is L-level, and the output of the NAND circuit 17 is output. The selection signal j, that is, becomes H level.

Before programming the fuse elements 7 and 8, since the redundancy repair memory cell selection signals c and d are at H level, the activation signal f output from the AND circuit 24 is at L level and AND. The activation signal g, which is the output of the circuit 25, becomes H level, and only the redundancy repair memory cell 2 is activated and the inspection is performed. On the other hand, when the L-level signal A is input to the row address input terminal 10, the inverted signal a thereof becomes H-level, the selection signal i output from the NAND circuit 16 is H-level, and the selection signal output from the NAND circuit 17 is selected. The signal j becomes L level. Therefore, AND
The activation signal f output from the circuit 24 is at H level, AND
The activation signal g which is the output of the circuit 25 becomes L level,
Only the redundancy repair memory cell 3 is activated and tested.

When the test terminal 12 is opened after the redundancy relieving memory cells 2 and 3 are inspected, the node becomes L level via the pull-down resistor 18, and the selection inhibit signal h output from the inverter 13 is output. Becomes H level. Further, since the output of the inverter 15 becomes L level, the selection signals i and j of the NAND circuits 16 and 17 become H level. Therefore, the output signals e, f, g of the AND circuits 23, 24, 25 are determined by the levels of the redundancy repair memory cell selection signals c, d, respectively. This is a normal redundant relief operation.

In this way, it is possible to inspect whether or not there is a defective memory cell in the redundancy relief memory cell before the redundancy relief, so that the redundancy relief memory cell can be replaced without prioritizing replacement. Redundancy repair can be performed by using a memory cell that does not include a defective memory cell. In the above-described embodiment, only the inspection circuit and the inspection method of the redundant relief memory cells in the row direction have been described, but the inspection of the redundant relief memory cells in the column (bit line) direction can be performed by the same configuration. it can.

[0018]

According to the semiconductor memory device of the present invention, since the decoder circuit for inspecting the redundancy repair memory cell is provided, the redundancy repair by the redundancy repair memory cell including the defective memory cell is avoided. Therefore, the redundancy repair rate can be improved. Further, it is possible to reduce an extra inspection time after redundant relief due to meaningless replacement using a redundant relief memory cell including a defective memory cell, and it is also possible to reduce an inspection cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

2 is a circuit diagram showing a specific configuration of a redundancy repair memory cell test decoder in FIG.

FIG. 3 is a block diagram showing a configuration of a semiconductor memory device including a conventional redundancy repair circuit.

[Explanation of symbols]

 1 Normal Memory Cell Array 2,3 Redundant Relief Memory Cell 4 Normal ROW Decoder 5,6 Spare Decoder 7,8 Fuse Element 9 Redundant Relief Memory Cell Inspection Decoder 10,11 Row Address Input Terminal a, b Input Inversion Signals c, d , I, j Redundancy repair memory cell selection signal e, h Selection prohibition signal f, g Redundancy repair memory cell activation signal k Test decoder activation signal

Claims (1)

[Claims] 1. A semiconductor memory device in which a plurality of redundant relief memory cells for replacing defective memory cells in the regular memory cell array are provided in parallel to a regular memory cell array, and the redundant relief memory cells are inspected. A semiconductor memory device comprising an inspection circuit for the purpose.