KR940006923B1 - Semiconductor memory device with redundant column decoder - Google Patents

Abstract

The device comprises a normal memory cell array which is arranged to select all the cell in the column corresponding to column selecting signal within array by column select signal to be outputted from a normal column decoder, a redundancy cell array to be arranged to select all the cell in the column corresponding to redundant column selecting signal within the array by the redundant column selecting signal to be outputted from redundant column decoder, and a low decoding means to input low address signal to select low column of the normal memory cell array, a column decoding means for outputting redundant column selecting signal when low address indicating bad cell and column address are inputted.

Description

Semiconductor Memory Device with Redundant Column Decoder

1 is a conventional circuit diagram of a semiconductor memory device incorporating a redundant column decoder.

2 is a circuit diagram showing the column selection of FIG.

3 is a circuit diagram of a redundant column decoder according to the prior art.

4 is a circuit diagram of a redundant column decoder according to the present invention.

5 is an operation timing diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to circuitry that provides redundant memory column redundancy when any portion of a memory cell is defective.

As the semiconductor memory device becomes more integrated and large in capacity, the increase in the area of the semiconductor chip increases the failure rate of the memory cells arranged in the array, and the application of redundant cell arrays and redundant decoding circuits to replace the defective memory cells is currently It has become an indispensable element for almost all semiconductor emigration devices. Replacing a bad memory cell of a normal memory cell array with a cell of a redundant cell array typically involves fabricating and testing a semiconductor memory device, followed by a row or column of a defective normal memory cell array. column), an address was checked to disable the normal decoder corresponding to the address and to program the redundant decoder to be enabled at the address. There are two methods of programming such a method of using a memory device and a method of performing the redundancy by cutting off a fuse. The method of disconnecting a fuse uses a laser beam and an electrical method. Has been. In the early stages when a redundant cell array was provided, a method of replacing the entire block of a predetermined normal memory cell array including a defective cell with a predetermined redundant array was used. Recently, only a column of a normal memory cell array including a defective cell is redundant. The trend is to replace columns in cell arrays. In the case of replacing only a column as described above, a normal column decoder and a redundant column decoder are provided in a semiconductor memory device to perform redundancy by an output signal of the redundant column decoder corresponding to a column address signal decoded in the normal column decoder. This is a known fact in the art.

FIG. 1 is a schematic block diagram of a conventional semiconductor memory device having a redundant column decoder. In FIG. 1, the entire memory array is divided into memory arrays 1, 2, 3, i, j. The one memory array includes normal bit lines and redundant bit lines. As is known, the redundant bit line is intended to replace a normal bit line in which a bad cell exists. The normal column decoder transmits the data of the normal bit line to the outside of the memory array, and is divided into (A) and (B) groups as shown in accordance with an encoded address. The redundant column decoder 1 serves to send data of the redundant bit line to the outside of the memory array. In addition, when the array column decoder 1 is operated, the normal column decoder is disabled so that the redundant bit line replaces the normal bit line. The bit lines in each memory array selected by the same column address are simultaneously connected to the outside of the memory array by the output of the same column decoder. That is, one column select signal CSLi simultaneously selects the same column in the entire memory array.

An example showing column selection in the memory array partitioning scheme as shown in FIG. 1 is illustrated in FIG. In FIG. 2, the transistor MTF connected between the memory arrays is a transfer transistor. The transistor MTF is a transfer transistor and outputs data of a predetermined memory cell connected to one end of a channel under control of the column select signal CSL. It serves to convey. For example, when the first column select signal CSLi is applied as a signal of a "high" level, the first pair of bit lines in all memory arrays ( And BL11 to BL1j are connected to each input / output line through the transfer transistor MTF to connect the first bit line pair ( The data of the memory cells connected to BL11 to BL1j are connected to the outside of the memory array. In addition, it will be easily understood that the redundant bit line is connected to the outside of the memory array through each of the input and output lines by the redundant column select signal RCSL output from the redundant column decoder 1.

A redundant column decoder circuit diagram according to the prior art is shown in FIG. The redundant column decoder circuit shown in FIG. 3 is a circuit well known in the art, and its configuration includes an input terminal for inputting column addresses CA0, CA1, ... CAi, and the column address CA0, A transmission stage for transmitting " CA1 " CAi) " turned on " only during a repair operation, a fuse stage appropriately cut according to a column address previously input during the repair operation, and an output of the fuse stage. And an output terminal for outputting a predetermined signal connected to the redundant column selection signal RCSL. In FIG. 3, P1 is a pulse signal generated when the chip enters an enable state, and MF is a master fuse (also called a main fuse) and is cut during the repair operation. . It will be readily understood that the replacement operation of the redundant bit line is performed by the output of the redundant column decoder selected by the specific combination of the column addresses CA0, CA1, .... CAi input in FIG. If the circuit of FIG. 3 is not a repair operation, since the master fuse MF is not cut, each transistor (N / P0, PB0 / NB0, ... PBi / NBi.) Of the transmission line is ＊ is Note that it is the same as. The S0, S1, ... Si signals are all "low" level signals, and the NAND gate 5 at the output stage outputs the "high" level CK1 signal and the REN signal is output at the "low" level. The redundant column select signal RCSL is brought to the "low" level through the delay circuits 7, 8, 9 and 10. From this the output of the normal column decoder of FIG. 2 is enabled and the redundant column decoder is in a disabled state.

On the other hand, when the circuit of FIG. 3 is in the repair operation, the master fuse MF is cut in advance. Then, each of the transistors N0 / P0, PB0 / NB0, ... PBi / NBi of the transmission stage are all "turned on" to enable transmission of the input column addresses CA0, CA1, ... CAi. At this time, each fuse of the fuse stage Is cut so that the S0, S1, ... Si signals are all "high" level signals according to the state of the column addresses CA0, CA1, ... CAi input. For example, if CA0 is a "high" level signal, fuse FC0 is blown, and if CA0 is a "low" level signal, the fuse is reversed. Is cut). Therefore, the NAND gate 5 of the output terminal outputs a CK1 signal having a "low" level, and the REN signal is output as a signal having a "high" level. Then, the normal column decoder of FIG. 2 is disabled from the "high" level REN signal, and the redundant column select signal RCSL becomes a "high" level, thereby performing a redundant bit line replacement operation. That is, in the circuit of FIG. 3, when a defective cell exists in a specific normal bit line, the chip is cut in advance according to a combination of column addresses for selecting the normal bit line, and then the chip is removed. When enabled, the normal column decoder is disabled and the redundant column decoder is enabled so that the redundant normal bit line selected by the redundant column select signal (RCSL), which is an output of the redundant column decoder, includes the bad cell. It is made to take the place of. However, in the case of the circuit of FIG. 3, for example, The first column selection signal CSL1 does not become " high " and the redundant column selection signal RCSL becomes " high " level when one memory cell in the cell is found to be a defective cell. In Instead of / BL11 / RBL1 will take over.

At this time, / BL12 ~ / BL1j is Is selected by the first column select signal CSL1 equal to / BL11. / BL12 ~ Selected by the redundant column select signal RCSL even if there are no defective cells in / BL1j / RBL2 ~ Replaced by RBLj. That is, the first bit line pair from the memory array -2 to the memory array -j without a bad cell is replaced by a redundant bit line pair unnecessarily because there is a bad cell in the first bit line pair of the memory array -1. do. But at this time / RBL2 ~ When a defective cell exists in / RBLj, there is a possibility that a new defective cell occurs. In particular, as many memory arrays are controlled by one column selection signal CSL, this possibility becomes larger, making it difficult to secure reliability of a semiconductor memory device performing a redundancy function.

Accordingly, an object of the present invention is to generate a new defective cell in the redundant bit line when replacing a normal bit line with a redundant bit line in a semiconductor memory device which selects columns of a plurality of memory arrays under the control of the same column select signal. It is to provide a semiconductor memory device that suppresses the maximum.

In order to achieve the object of the present invention, the present invention is a normal memory cell array arranged to select all the cells located in the column corresponding to the column selection signal in the array by the column selection signal output from the normal column decoder, redundant A redundant cell array arranged such that all cells located in a column corresponding to the redundant column selection signal are selected in the array by a redundant column selection signal output from a column decoder, and a memory cell in the redundant cell array during a first operation; The semiconductor memory device operable to be selected is a redundant column decoder having predetermined row decoding means for inputting a row address signal for selecting a row (row) of the normal memory cell array.

In the first operation, the normal column decoder is disabled and the redundant column decoder is enabled by a signal output from the redundant column decoder, so that a defective cell in the normal memory cell array is defective in the redundant cell array. It is characterized in that the repair operation to replace the unknown cell.

The low address signal may be part of a signal for selecting a row (row) of a defective memory cell of the normal memory cell.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The circuit of the redundant column decoder according to the present invention is shown in FIG. 4 and the operation timing diagram thereof is shown in FIG.

The configuration of FIG. 4 according to the present invention will be described. Before the description, it should be noted that the redundant column decoder according to the present invention has the circuit shown in FIG. 3 as it is, and therefore, the description of the column decoding means which is the circuit shown in FIG. The configuration of FIG. 4 includes a normal memory cell array in which all cells located in a column corresponding to the column selection signal are selected in the array by a column selection signal output from the normal column decoder, and a redundant column output from the redundant column decoder. A redundant cell array is arranged such that all cells located in a column corresponding to the redundant column selection signal RCSL are selected in the array by a selection signal RCSL, and a memory cell in the redundant cell array is selected during a repair operation. A semiconductor memory device comprising: column decoding means for inputting and decoding a column address signal for selecting a predetermined selected column and row decoding means for inputting and decoding a row address signal for selecting a predetermined selected row (row); Phase during the repair operation Is to disable the normal column decoder signal and configured to output a signal to be enabled in a given memory cell, the output of the redundant cell array. The row decoding means includes an input terminal for inputting the row address signal, a transmission terminal for transmitting the output of the input terminal in the repair operation, a fuse terminal for appropriately selecting the output of the transmission terminal in the repair operation; And an output terminal for inputting an output of the fuse stage to output a predetermined selected row address. The redundant column selection signal RCSL is output after a predetermined delay time after the redundant column enable signal REN is output as in the method of FIG. 3. The redundant column enable signal REN is output through a logic operation of each output of the column decoding means and the row decoding means.

An operation characteristic of FIG. 4 will be described in detail with reference to FIG. 5. In the present invention, in order to solve the problems of the conventional circuit, by selecting the same column address (CSLi) by the same column address by inputting the low addresses (RAi, RAj) having the function of selecting each memory array to the redundant column decoder. Even if the bit lines are used, the normal column select signal CSLi is disabled and only the redundant column select signal RCSL is enabled as a "high" signal only when a specific bit line is selected in the memory array in which the defective cell exists. Thus, when the column is selected in another memory array, the normal column select signal CSLi is enabled as "high" and the redundant column select signal RCSL is maintained as "low" state, so that if the redundant in the other memory array is Even if a bad cell exists in the bit line, the bad cell cannot be selected. For example, if the address for selecting a memory array in which bad cells exist is "RAi: low, RRAj: high", the fuse FRi and Cut in advance. When a defective cell exists in a characteristic bit line in the memory array selected by the row address, when a column address for selecting the bit line is applied, the previously-cut mast fuse MF as described in the related art and By combination of these, the output signal CKi of the NAND gate 41 which is the output terminal of the column decoding means becomes a "low" signal. In addition, the pull-down transistor RNDi (RNDj) of the row decoding means is " turned off " ) All transistors are "turned on" and with the fuse FRi Since is previously cut, the RSi and RSj signals are both high signal and the CK2 signal is output at the low level.

Therefore, the redundant column enable signal REN becomes a "high" level signal, and the normal column decoder of FIG. 2 is disabled, and a redundant column select signal RCSL is generated to a "high" level after a predetermined delay time, thereby providing a redundant. Select the column bitline. At this time, if the fuse in the row decoding unit D is cut as described above, if "RAi: low, RAj: high" is not satisfied, one of RSi and RSj is a signal of "low" level. Since the CK2 signal is generated as a "high" level signal, the redundant enable signal REN becomes a "low" level signal. The normal column selection signal CSLi is generated as "high" by the redundant enable signal REN of the "low" state, and the redundant column selection signal RCSL is generated as "low" so that the normal bit line is selected. You can see well.

In contrast to the above, in the present invention, by providing a row address for selecting a memory array to the redundant column decoder, only a bit line (that is, one bad memory cell) of the memory array in which the bad cell exists is replaced by the redundant bit line, thereby providing a new bad The generation of cells can be suppressed as much as possible. In particular, the effect is great when random cells exist randomly in several different memory arrays.

Claims (4)

Corresponding to the column selection signal in the array by a column selection signal composed of a plurality of blocks separated and selected by a low address and sharing a column selected by any one column selection signal and output from a normal column decoder. A normal memory cell array arranged to select all cells located in a column, and a redundant column select signal outputted from a redundant column decoder, and a redundant cell array arranged to be selected in a chamber located in a column selected corresponding to the input. A semiconductor memory device, wherein the memory cell in the redundant cell array is selected during a repair operation, comprising: column decoding means for inputting a column address, decoding the same, and outputting a corresponding column selection signal and a low address; An input terminal to make and the mouth A transmission stage for transmitting the output of the stage during the repair operation, a fuse stage for cutting the output of the transmission stage in response to an address input for designating a defective cell during the repair operation, and an output of the fuse stage And row decoding means for inputting and decoding a row address signal for selecting the selected row, the repair operation including at least an output terminal for outputting a predetermined selected row address, wherein the repair operation includes a row address for designating the defective cell; And the redundant column select signal is output only when all the column addresses are input. The redundant column decoder of claim 1, wherein the row address is part of a signal for selecting a row of a defective memory cell of the normal memory cell. Corresponding to the column selection signal in the array by a column selection signal composed of a plurality of blocks separated and selected by a low address and sharing a column selected by any one column selection signal and output from the normal column decoder. A normal memory cell array arranged to select all of the cells located in the column to be selected, and a redundant cell array arranged to be selected to a chamber located in a column selected in response to the input by inputting a redundant column selection signal output from the redundant column decoder. A semiconductor memory device having a memory cell in the redundant cell array during a repair operation, comprising: column decoding means for inputting a column address, decoding the same, and outputting a column selection signal corresponding thereto; An input terminal for inputting and the mouth A transmission stage for transmitting the output of the stage during the repair operation, a fuse stage where the transmission stage and the output are cut in correspondence with an address input for designating a defective cell during the repair operation, and an output of the fuse terminal And row output means for inputting and decoding a row address signal for selecting the selected row, the output terminal for outputting a selected row address of the row; The redundant column decoder includes a redundant column decoder, and outputs the redundant column selection signal only when the redundant column decoder inputs both a low address and a column address for designating the defective cell, thereby selecting the redundant cell array. When a redundant column decoder inputs a column address specifying the bad cell and a row address specifying a normal cell, the redundant cell array is deselected so that the row address and column address specifying the bad cell are determined as the redundant column. The repair operation is performed only when all the input to the decoder. 4. The semiconductor memory device according to claim 3, wherein a signal for outputting the memory cells of the redundant cell array is generated through a predetermined delay circuit after the signal for disabling the normal column decoder is output.