KR0146630B1 - Selection circuit for the memory block of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory block selection circuit of a semiconductor device, and selectively fuses as necessary to enable a die having a defective bit to be used only in a part of a die that is impossible to be repaired during a functional test. Up to 3/4 of the total memory block by installing an optional fuse in the memory block selection circuit so that the memory block selection address signal can be fixed to a high or low potential by blowing A memory block selection circuit of a semiconductor device capable of enabling a die without defects in at least one quarter of the dies in which a defective bit is generated due to a defective bit in an unusable die can be used as a device having a lower level of integration.

Description

Memory block selection circuit of semiconductor device

The accompanying drawings show a memory block selection circuit diagram of a semiconductor device according to the present invention.

* Explanation of symbols for the main parts of the drawings

Q1 to Q4: Transistors F1 to F3: Selective fuse

G1 to G3: gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory block selection circuit of a semiconductor device, and in particular, selectively blows fuses as necessary to fix a memory block selection address signal at a high or low potential. By installing an optional fuse in the memory block selection circuit, at least one quarter of the dies that are disabled due to a fault bit are generated in blocks up to 3/4 of the total memory block. The present invention relates to a memory block selection circuit of a semiconductor device capable of using a die without a defect as a device having a lower level of integration, thereby obtaining a device having improved characteristics compared to a memory device having the same level of integration, and increasing a production yield.

In general, a circuit of a memory device such as a DRAM is composed of a cell area and a circuit area for reading and writing data in the cell. In the cell, a predetermined number of redundancy lines are designed to enable repair in the case of defective bits for improvement of yield, but if a defective bit exceeding the limit is generated, a fault die die) and make it unavailable.

Conventionally, when a defect occurs in a word line or bit line associated with a specific row or column address, the die can be used by replacing it with a redundant word line or bit line to repair the defect. When the number of generated words or bit lines is larger than the number of redundancy words or bit lines, the repair is impossible. In addition, in the case where a defect occurs only in some memory blocks, since address selection depends on an input address signal, even if some blocks are available, they are recognized as a defective die and are disabled. Therefore, switching to a die with a lower level of integration using some memory blocks will increase cost reduction and production yield, and can produce devices with improved characteristics compared to memory devices of the same density.

Accordingly, the present invention selectively blows fuses as needed to fix the memory block selection address signal at a high or low potential. It is an object of the present invention to provide a memory block selection circuit of a semiconductor device that can solve the above-mentioned disadvantages by providing a.

The present invention for achieving the above object is to generate a block selection address signal in accordance with the output of the block selection circuit including an address selection signal and a selection fuse in order to select only available memory blocks of the memory element consisting of a plurality of memory blocks It is characterized in that the configuration.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The accompanying drawings are a memory block selection circuit diagram of a semiconductor device according to the present invention, wherein a transistor Q1 having a gate terminal connected to a node N1 is connected between a power supply terminal Vcc and a node N3, and the power supply terminal ( Transistor Q3 and fuse F2 having a gate terminal connected to the RAS signal input terminal are connected in series between Vcc) and the node N1. In addition, the node N1 is connected to the output terminal of the NAND gate G1, and a signal passing through the inverted gate G3 from the power terminal Vcc and the RAS signal input terminal is input to the input terminal of the NAND gate G1. To be connected. A transistor Q2 having a gate terminal connected to the node N2 is connected between the node N3 and the ground terminal Vss, and a gate terminal is a RAS signal between the ground terminal Vss and the node N2. The transistor Q4 and the fuse F3 connected to the input terminal are connected in series. In addition, the node N2 is connected to the output terminal of the NOR gate G2, and the RAS signal input terminal and the ground terminal Vss are connected to the input terminal of the NOR gate G2, and the node N3 and the block are connected. A fuse F1 is connected between the selection address signal input terminals AX9 or AY9. The operation will be described below.

Since the RAS signal is input in a low state during normal operation, the output of the NAND gate G1 becomes low due to the high signal passing through the inverted gate G3. At this time, the transistor Q3 Since the potential of the node N1 is maintained in a high state since the signal is turned on, the transistor Q1 is turned off. In addition, the output of the NOA gate G2 becomes high but the potential of the node N2 remains low due to the turn-on of the transistor Q4, so that the transistor Q2 also turns off, so that the block selection address signal AX9 or There is no change in the output of AY9).

Then, according to the present invention, when the selection fuse is cut by a method of fixing the block selection address signals AX9 and AY9 to high or (and) low states for use as a device having a lower level of integration. This will be described with reference to the description.

If you want to use only blocks where the signals AX9 and AY9 are high, disconnecting the fuses F1 and F2 of the circuits AX9 and AY9 causes the state of node N2 to remain unchanged, and only the potential of node N1 goes low. Since the transistor Q1 is turned on, the block select address signal is fixed to a high state.

If you want to use only blocks with AX9 and AY9 signals low, disconnect the fuses F1 and F3 of the AX9 and AY9 circuits.The state of node N1 remains unchanged and only the potential of node N2 becomes high, Since the Q2 is turned on, the block select address signal is fixed at the low state.

If you want to use only blocks where AX9 signal is high and AY9 signal is low, disconnecting fuses (F1 and F2) in AX9 circuit will fix AX9 signal in high state, and disconnecting fuses (F1 and F3) in AY9 circuit will be AY9 The signal is fixed low.

If only the block in which the AX9 signal is low and the AY9 signal is high, the fuses F1 and F2 are disconnected in the AX9 circuit, and the fuses F1 and F3 are disconnected in the AY9 circuit.

The disconnection position of the selection fuses F1, F2, and F3 can be found in the function test before the repair, and the memory block can be selected only by the fuse disconnection by the laser beam. In the standby state, the RAS signal is high, so leakage current is prevented. This circuit can be applied when the operation method of the memory device is X1 or X4. Especially, since 4M and 1M memory devices have the same package type, when 4M is recycled, the same 4M package is used as 1M. Just sorting is needed, and when 1M is recycled, it can be used as 256K DRAM by changing pin ID after package. It is expected that the present invention can be applied to next-generation memory devices, and in the current device design structure, I / O usage method places specific I / O in a specific block. In this case, the present invention cannot be applied. Therefore, a method of co-distributing I / O use per block must be adopted. The memory block selection address signals AX9 and AY9 are arbitrary addresses and can be changed according to a design structure for selecting a cell block.

As described above, according to the present invention, the uppermost block selection address is fixed to a block in which no defect bit exists so that the memory bit is used as a device having a lower level, thereby improving cost reduction effect and production yield, and improving characteristics compared to memory devices having the same density. There is an excellent effect to produce an improved device.

Claims (2)

In a memory block selection circuit of a semiconductor device, a block selection address signal is generated in accordance with an output of the block selection circuit including an address selection signal and a selection fuse to select only memory blocks usable among memory elements including a plurality of memory blocks. A memory block selection circuit of a semiconductor device, characterized in that. The memory block selection circuit of claim 1, wherein the memory block selection circuit is connected between a power supply terminal Vcc and a node N3 and driven according to a voltage of the node N1, the power supply terminal Vcc, and the node. A transistor Q3 connected between the fuses N1 and driven according to an input of a RAS signal, an inverting gate G3 for outputting an inverted voltage using the RAS signal as an input, and the inverting gate; Between the NAND gate G1 for determining the potential of the node N1 according to the output voltage of G3 and the respective voltages supplied from the power supply terminal Vcc, and between the node N3 and the ground terminal Vss. Transistor Q2 connected and driven according to the voltage of the node N2, and the transistor Q4 connected between the ground terminal Vss and the node N2 through a fuse F3 and driven according to the input of the RAS signal. ) And the voltage according to the voltage supplied from the RAS signal and the ground terminal Vss. And a fuse (F1) connected between the node (N3) and the block select circuit address signal input terminal for determining the potential of the node (N2). Block selection circuit.