KR100206699B1 - Volatile memory device having improved row redundancy - Google Patents

Abstract

1. Field of the invention as described in the claims: volatile semiconductor memory device.

2. Technical problem to be solved by the present invention: Provides a volatile semiconductor memory device that provides the efficiency for a low-direction redundancy scheme.

3. Summary of the Invention A volatile semiconductor memory device in which a redundant word line is shared by redundancy memory cells in a plurality of memory cell blocks for a row-direction redundancy scheme is provided. And a switching unit installed in response to the block selection signal and the complementary signal of the block selection signal to enable repair even when normal memory cells corresponding to the same row address are defective between adjacent memory cell blocks.

4. Significant use of the invention: Used as a volatile semiconductor memory device with improved low redundancy efficiency.

Description

Volatile Semiconductor Memory Devices with Improved Low Redundancy Efficiency

1 is a low redundancy related block diagram of a conventional volatile semiconductor memory device.

2, 3, and 4 are detailed circuit diagrams of corresponding portions in FIG. 1, respectively.

5 is a low redundancy related block diagram of a volatile semiconductor memory device according to a specific embodiment of the present invention.

FIG. 6 is a detailed circuit diagram illustrating a connection relationship between a low fuse generator 10 and a switching unit 100 in FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a volatile semiconductor memory device such as a DRAM, and more particularly, to a volatile semiconductor in which one spare word line is shared by redundancy memory cells in a plurality of memory cell blocks for a low-direction redundancy scheme. It relates to a memory device.

In general, a volatile semiconductor memory device, such as a dynamic random access memory (DRAM) which includes a plurality of memory cells as a matrix array and accesses data in a selected memory cell, is manufactured in which the memory cells in a normal memory cell array are defective. In case of becoming defective or defective, it can be designed and manufactured as shown in FIG. 1 so as to have redundant memory cells for replacing normal memory cells.

Referring to FIG. 1, when a volatile semiconductor memory device such as a DRAM is designed to be half activated, a plurality of memory cells in a normal memory cell array are replaced by redundant memory cells when determined as a row addressable fail. The redundancy memory cells in the memory cell blocks 50 and 51 of the memory cell block share a spare word line connected to one row fuse generator 10. That is, four spare word lines respectively connected to the first memory cell block 50 and the second memory cell block 51 are connected to the output terminals of one row fuse generator 10, and these output terminals are represented by SW0 as shown in FIG. , SW1 SW2, and SW3. For example, if the normal memory cells in the first memory cell block 50 are determined as row addressable fail, the decoding of the block selection information in the row fuse generator 10 having a fuse box composed of a plurality of cuttable fuses in FIG. The fuse 2 corresponding to the row address signal DRA8 and the failed row address is cut by a light source such as a laser. Therefore, since the fuse 2 is cut when the row address for selecting the failed row is applied, the potential of the fuse common node NO1 becomes high and the redundancy enable signal RED appears as a logic signal high. In FIG. 1, reference numerals 40 and 41 which are not described are row decoders. On the other hand, when the redundancy enable signal RED appears as a logic signal high, the output terminals SW0, SW1, SW2, and SW3 show only a spare word line to replace a failed word line by a high signal due to an enable signal of DRAOB1B to DRAO1. Enable it. The PIRRE generator 20 receives the redundancy enable signal RED output as logic high and the decoded row address signal DRA8 which is the block selection information to output the low redundancy signal PIRRE as high in order to disable the normal word line. do. Here, the logic signal as described above is generated when the PIRRE generator 20 of FIG. 1 includes NAND gates 21-25 as shown in FIG. The PIXI generator 30, which receives the logic high signal from the PIRRE generator 20, disables the normal word line connected to the output terminal PIXO-3 when it is composed of a plurality of elements 30-39 as shown in FIG. Let's do it. That is, the high signal applied to one input of the NOR gate 35 in FIG. 4 causes the four NOR outputs to be logic low, so that the level of the output terminal PIXO-3 becomes the ground level. When the normal word line is enabled, the PIXI generator 30 is responsible for providing the word line driver with a voltage level higher than a normal power supply voltage so that the selected word line can be boosted quickly.

As described above, FIG. 1 described with reference to FIGS. 2, 3, and 4 shows signals generated by cutting a fuse corresponding to a row address of a defective cell in order to repair a defective normal memory cell in a row direction. It can be seen that it has a device structure that enables the spare word line and disables the corresponding normal word line. The block selection signals DRA8 and B are alternately provided, and one row fuse generator 10 is commonly used among adjacent blocks. It can be seen that the half activation method is taken.

Here, when the spare word line (or low redundancy word line) of one memory cell block is enabled, the spare word line of the adjacent block is also enabled. This is because different spare word lines between adjacent blocks use one row fuse generator 10 in common. In this case, if a defect occurs at the same row address in the first memory cell block 50 and the second memory cell block 51, the repair of the two blocks cannot be accomplished with one row fuse generator 10. That is, when a defect occurs at the same row address between adjacent blocks, when the first memory cell block 50 is repaired as one row fuse generator 10, the redundancy memory cells in the inactive second memory cell block 51 become a hurt. Will receive.

Accordingly, an object of the present invention is to provide a volatile semiconductor memory device capable of solving the above-described conventional problems.

Another object of the present invention is to provide a volatile semiconductor memory device capable of repairing even when memory cells corresponding to the same row address among adjacent memory cell blocks fail.

The present invention for achieving the above objects, a memory having a plurality of normal cells for storing data on a single semiconductor substrate and a plurality of cell blocks comprising a plurality of redundancy cells for resolving defects of the normal cells A cell array, normal and redundancy word line drivers respectively driving the normal word lines connected to the normal cells and the redundancy word lines connected to the redundancy cells in response to applied word line enable signals and word line driving signals; A volatile semiconductor memory device, comprising: a fuse box including cuttable fuse elements, wherein the redundancy word line is driven in accordance with an output of the fuse box, the block selection signal and the block selection in the redundancy word line Redundant in response to the complementary signal of the signal To install and to provide a switching signal to enable the word lines, it characterized in that the memory cells corresponding to the same row address are made possible even during a repair the defect between the adjacent memory cell blocks.

Hereinafter, a structure and a method thereof of a volatile semiconductor memory device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. Like reference numerals in the accompanying drawings indicate elements having the same configuration and function as much as possible. In the following description, the detailed items for such configurations are described in detail in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, features and functions of well-known semiconductor basic devices are not described in detail in order not to obscure the present invention.

First, basic technical principles will be briefly described for a more thorough understanding of the present invention. If one row fuse generator 10 uses neighboring blocks in common but can simultaneously repair memory cells corresponding to the same row address between adjacent memory cell blocks, it may be highly desirable in many aspects. That is, in the related art, one row fuse generator 10 may be commonly used by adjacent blocks to make the chip more compact. However, when memory cells corresponding to the same row address are defective between adjacent memory cell blocks, Repair was not possible. However, in the embodiment of the present invention, the aforementioned switching unit is configured as shown by reference numeral 100 of FIG. 5 to solve the above conventional problem.

As illustrated in FIG. 6, the switching unit 100 illustrated in FIG. 5 is composed of a plurality of N-type transistors N1 and N2. Two transistors are provided for each spare word line and enable corresponding spare word lines in response to a block selection signal DRA8 and a complementary signal DRA8B of the block selection signal. That is, a pair of N-type transistors each having a drain terminal connected to the conventional output terminal SWO (SPO in FIG. 6) and the source terminals connected to the spare word line terminals SWO-8B and SWO-8 constitute a unit switching unit. Fuse 2 receiving the block selection signal DRA8 of FIG. 6 and the complementary signal DRA 8B of the block selection signal when the memory cells corresponding to the same row address are defective between adjacent memory cell blocks, and a fuse corresponding to the row address is cut. When the block select signal DRA8 and the complementary signal DRA8B of the block select signal are applied to the respective gates of the two transistors, all spare word lines to be repaired are enabled. On the other hand, when the memory cells corresponding to different row addresses between adjacent memory cell blocks are defective, fuse 2 corresponding to the block selection signal of FIG. 6 and the fuse corresponding to the row address are cut off, and the When the DRA8 and the block select signal complementary signal DRA8B are applied to each gate of the two transistors, only the spare word line to be repaired is enabled.

As described above, only a spare word line of a block to be repaired can be selectively enabled, indicating that repair can be performed not only when the memory cells corresponding to the same row address among adjacent memory cell blocks are defective but also in other cases. According to the present invention as described above, even if the memory cells corresponding to the same row address between the adjacent memory cell blocks is defective, the repair is possible.

Although the above-described invention has been described and limited by way of example with reference to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. . For example, as far as the matter allows, it will be apparent that the switching unit may use Morse transistors or bipolar elements having different conductivity types, as well as change or change the structure or the structure of FIG.

Claims (4)

A memory cell array having a plurality of normal blocks for storing data on a single semiconductor substrate and a plurality of cell blocks including a plurality of redundancy cells for resolving defects of the normal cells, and an applied word line enable signal 12. A volatile semiconductor memory device having a normal word line connected to the normal cells and a redundancy word line driver respectively connected to the redundancy cells in response to a plurality of word lines and word line driving signals. And a redundancy word line in response to the block selection signal and the complementary signal of the block selection signal in the redundancy word line when the redundancy word line is driven according to the output of the fuse box. Provide a signal to enable And a switching unit configured to enable repair even when memory cells corresponding to the same row address are defective between adjacent memory cell blocks. The apparatus of claim 4, wherein the switching unit comprises a plurality of MOS transistors. The apparatus of claim 1, wherein the switching unit comprises a plurality of bipolar transistors. A memory cell array having a plurality of normal cells for storing data and a plurality of cell blocks including a plurality of redundancy cells for resolving defects of the normal cells, applied word line enable signals and word line driving signals A redundancy word line control method of a volatile semiconductor memory device having a normal word line connected to the normal cells and a redundancy word line connected to the redundancy cells, respectively, in response to the plurality of redundancy words, comprising: Preparing a switching unit in the redundancy word line in response to a block select signal and a complementary signal of the block select signal; Providing one end of the switching section with an output of a corresponding fuse box in the low fuse generator when memory cells corresponding to the same row address between adjacent memory cell blocks fail; Providing the block selection signal and a complementary signal of the block selection signal to the switching unit; And enabling the redundancy word line as an output signal of the fuse box provided at one end of the switching unit.