JPH02192092A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To relieve short-circuit between select lines over different decoders by providing at least two pairs of spare row decoders, for which two spare word lines are connected out of the plural spare word lines, to replace the word line with defining the two word lines as one couple. CONSTITUTION:A semiconductor memory uses a signal to be basic for selecting a word line WL, the two pairs of first sub decoder signals phiXG and phiXK, for which the signal is decoded by a least-significant bit, and the four pairs of second sub decode signals phiX1-phiX4, for which the first sub decode signals phiXG and phiXK are respectively decoded by a just high-order bit of the least significant bit. The second sub code signals phiX1-phiX4 are inputted to the respective four word lines of the four way system and the first sub decode signals phiXG and phiXK are inputted to two spare word lines SWL which is replaced as a unit when the spare word line SWL is used. Thus, by the same number of the spare word lines as that of the conventional semiconductor memory, a defect over the two row decoders can be relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device equipped with a redundant circuit.

[Conventional technology]

FIG. 9 is a block diagram showing the configuration of a conventional semiconductor memory device equipped with a redundant circuit. The redundant circuit is a spare circuit for increasing manufacturing yield, and consists of spare memory cells, spare decoders, and the like.

FIG. 9 shows an example of a 64-bit storage device having signals Ao to A as address inputs.

In FIG. 9, memory cell array 1 includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The memory cell array 1 also includes a spare row 2 consisting of spare memory cells arranged in a plurality of rows and a spare column 3 consisting of spare memory cells arranged in a plurality of columns. A plurality of word lines are provided corresponding to the plurality of rows of the memory cell array 1,
A plurality of bit lines are provided corresponding to the plurality of columns.

On the other hand, RAS buffer 4 responds to externally applied row address strobe signal RAS to row address buffer 5.17 generating circuit 6. φ8 generation circuit 7. and activates the sense amplifier control circuit 8. G generation circuit 6 and φ8 generation circuit 7 generate precharge φP and drive signal φ8, respectively, at predetermined timings. The row address buffer 5 receives an externally applied address signal A.
.

~A7 and some of them as row address signal RA
2 to RA7 to the row predecoder 9, and the rest to the φ8 subdecoder 1 as row address signals RAG to RA.
Give to 0. The row predecoder 9 receives row address signals RA, ~RA? given from the row address buffer 5. is predecoded and the row selection signals Xi, Xj, x+t are given to the row decoder group 1) and the spare row decoder 12. Row decoder group 1) responds to precharge signal G from 6 generation circuit 6 and selects 4 rows of memory cell array 1 based on row selection signals Xi, Xj, and Xk. The φ8 sub-decoder 10 receives the drive signal φ8 from the φ8 generation circuit 7.
In response, subdecode signals φX1 to φX4 are applied to word driver group 13 based on row address signals RAo and RAl applied from row address buffer 5. The word driver group 13 receives sub-decode signals φ□ to φ
In response to X4, the word line of one of the four rows selected by row decoder group 1) or spare row decoder 12 is driven. Information in the memory cells connected to the driven word line is read onto each bit line. The sense amplifier control circuit 8 controls the sense amplifier group 14 at a predetermined timing.
make it work. Sense amplifier group 14 amplifies information on each bit line.

On the other hand, CAS buffer 15 activates column address buffer 16 and read/write buffer 17 in response to externally applied column address strobe signal CAS. Column address buffer 16 latches externally applied address signals Ao to λ and provides them as column address signals to column predecoder 18. Column predecoder 18 predecodes the column address signal,
A column selection signal is applied to column decoder group 19 and spare column decoder 20. Column decoder group 19 selects one column of memory cell array 1 based on a column selection signal. In this way, one word line and one bit line are selected, and information is successively written or written to the memory cell located at the intersection thereof. In FIG. 9, only one selected word line WL1, one selected bit line BL, and the memory cell MC at the intersection thereof are shown.

Continuation and writing of information is carried out in the read/write buffer 17.
Selected by Read/write buffer 17 activates input buffer 21 or output buffer 22 in response to externally applied read/write signal R/W. When input buffer 21 is activated, input data DIN is written into the selected memory cell MC as described above. When the output buffer 22 is activated, the information stored in the memory cell MC selected as described above is output data D. Read as LIT.

Note that all of the above circuits are formed on the same semiconductor chip 23.

By the way, defective memory cells may occur during the manufacturing stage. Furthermore, a defective word line such as a disconnection may occur. It is economically undesirable to treat the entire semiconductor memory device formed on a semiconductor chip as a defective product when a defect occurs only in the negative part. Therefore, if a defective memory cell or a defective word line is included in the selected row, the spare row decoder 12
The spare row 2 is set in advance to be selected in place of the defective row. Furthermore, if the selected column includes a defective memory cell or a defective bit line, the spare column decoder 20 is set in advance so that spare column 3 is selected in place of the defective column. be done. In this way, the manufacturing yield is improved.

FIG. 10 is a diagram showing the configuration of a part of the row predecoder 9 included in FIG. 9, and particularly shows a circuit portion for generating the row selection signal Xi.

Here, X means any one of X+, Xt, Xs, and Xa.

The gate circuit 91 receives the row address signal RA t and outputs the same signal RA w and a signal RA 2 which is an inversion of the row address signal RA 2. The gate circuit 92 receives the row address signal RA3 and outputs the same signal as the row address signal RA3 and a signal RA3 which is an inversion of the row address signal RAs.
Signal RA2. Either one of the signals RAW and one of the signals RA3゜πT〒 are input. The combinations of the signal RA or RA z and the signal RA 3 or RA input to the gate circuits 93 to 96 are different from each other. Row selection signals X1-X4 are output from gate circuits 93-96, respectively. Row address signal RA
Depending on the level of z and RA3, the row selection signals X,
~X, one of them is at "H" level, and all the others are at "L" level.

Note that the row selection signal X in FIG. 9 is XS.

It means any of Xb, X7, Xs, and Xk is Xq
.

Xl. ,X, ,X,2.

Row selection signals X5 to Xs are created using row address signals RAa and RA5 in the same manner as in the case of FIG.
A. is created in the same manner as in the case of FIG. 10.

FIG. 1) is a diagram showing the configuration of the φ× sub-decoder 10 included in FIG. 9. φ. Generation circuit 101, φ8□ generation circuit 102. The φ81 generation circuit 103° and the φX4 generation circuit 104 each receive a row address signal RA or its inverted signal RAI, and generate a sub decode signal φXI+ in response to a drive signal φ. φXz, φx3.φx4 are output.Sub decode signals φXl+φ8□ according to the levels of the row address signals RA o , RA l and the inverted signals RAG and R penalty.

φ. , φX4 becomes "H" level, and all the others become "L" level.

FIG. 12 is a diagram showing a detailed configuration of the memory cell array 1 and its peripheral portion included in FIG. 9.

In the memory cell array 1, 4m word lines WL and a plurality of bit line pairs BL and B are arranged so as to cross each other. Here m is a positive integer. Furthermore, four spare word lines SWL are arranged on the sides of these word lines WL. Each word line WL and bit line B
A memory cell MC is provided at the intersection with L or BL,
A spare memory cell SMC is provided at the intersection of each spare word line SWL and the bit line BL or (2). 4
m word lines WL and 4 spare word lines SWL
(4m+4) word drivers 13a are provided corresponding to the word drivers 13a. Each word line WL and each spare word line SWL are connected to a corresponding word driver 13a. 4m word lines WL and word driver 13a
is divided into m groups each consisting of four word lines WL and four word drivers 13a. m row decoders Ila are provided corresponding to these m sets. Each row decoder lla selects a corresponding set of four word drivers 13a. Further, one spare row decoder 12 is provided corresponding to four spare word lines SWL and four word drivers 13a. The spare row decoder 12 selects four corresponding word drivers 13a.

On the other hand, a plurality of sense amplifiers 14a and a plurality of column decoders 19a are provided corresponding to the plurality of bit line pairs BL, BL. Each bit line pair BL.

The output terminals are connected to the corresponding sense amplifiers 14a and the corresponding column decoders 19a.

Next, the operation of the circuit shown in FIG. 12 will be explained.

One of the row decoders lla is selected based on row selection signals Xi, Xj, and Xk.

The selected row decoder lla drives a corresponding set of four word drivers 13a. According to the sub-decode signals φX, ~φ×4, the four word drivers 1
One of the word lines 3a drives the corresponding word line WL. Thereby, the memory cell M connected to that word line WL
The information in C is read onto each bit line BL or BL,
It is amplified by the sense amplifier 14a. Then, one of the column decoders 19a is selected according to the column address signal.
is selected. During writing, information is written onto the bit line pair BL, B connected to the selected column decoder 19a. When successive occurrences occur, the selected column decoder 1
Information on the bit line pair BL, BL connected to 9a is read.

If a defective memory cell or defective word line is formed during the manufacturing stage, the spare row decoder 12 is selected instead of the row decoder 1)a corresponding to the defective memory cell or defective word line. selected. That is,
When an address signal for selecting a row decoder lla corresponding to a defective memory cell or a defective word line is applied, a spare row decoder 12 is selected in place of the row decoder lla. Then, one of the word drivers 13a connected to the spare row decoder 12 drives the corresponding spare word line SWL in accordance with the sub-decode signal φ to φ4.

FIG. 13 is a diagram showing a specific circuit configuration of the row decoder 1)a and word driver 13a included in FIG. 12.

The row decoder lla is an N-channel MO3) transistor Q.
1~Q4. P channel MO3) transistors Q5 to Q7.
and link element LNO.

The link element LNO is made of polysilicon, aluminum, or the like, and can be fused with a laser beam or the like. Transistor Q5. Q6 is coupled between power supply potential vcc and node N1. Transistor Q5
A precharge signal φ2 is applied to the gate of the transistor Q6, and the gate of the transistor Q6 is connected to the node N2. A link element LNO and transistors Ql, Q2 . Q3 is connected in series. Transistors Ql, Q2. Row selection signals Xi, Xj, and Xk are applied to the gates of Q3, respectively. As mentioned above, X represents any one of X, ~X4, and Xj
represents any one of X, ~Xll, and Xk represents X, ~X
l! Indicates one of the following.

Row selection signal Xi given to each row decoder lla.

The combination of X, , Xk is different from other row decoders lla. Transistor Q7 is coupled between power supply potential ■cc and node N2, and its gate is connected to node Nl. Transistor Q4 is coupled between node N2 and ground potential, and has its gate connected to node N1. Transistor Q4 and transistor Q7 constitute an inverter. Therefore, the level of node N2 is opposite to the level of node Nl. If a defect exists in a memory cell or word line, the link element LNO of the corresponding row decoder lla is blown out in advance by a laser beam.

Nodes Nl and N2 of each row decoder lla are connected to a corresponding set of four word drivers 13a. Each word driver 13a is an N-channel MoS transistor Q
8. Q9. Consists of QIO.

Transistor Q9 is coupled between any one of sub-decode signals φ□ to φX4 and word line WL, and its gate is connected to the corresponding row decoder l via transistor Q8.
It is connected to node N2 of la. Transistor QI
O is coupled between the word line WL and the ground potential, and its gate is connected to the node N1 of the corresponding row decoder lla.

The gate of transistor Q8 is coupled to power supply potential VCC. Each word driver 13a in each group receives a different sub-decode signal φ83. φ8□, φX3+ or φ,! 4 is combined.

Next, the operations of row decoder lla and word driver 13a will be explained. Precharge signal φP is “L”
At the level, the transistor Q5 is in the on state, and the potential of the node N1 is "H" level (Vcc level)
It becomes. Therefore, the transistor Q10 of the word driver 13a is in an on state, and the word line WL
The potential of is at "L" level (ground level).

When precharge signal 5 rises to the "H" level, transistor Q5 is turned off. Transistors Ql, Q2. Q
Row selection signals Xi, Xj, Xk given to the gates of 3
When all become 'H' level, transistors Q1 and Q
2. Q3 are all turned on, the potential of node N1 becomes "L" level, and the potential of node N2 becomes "H" level. As a result, the transistor QIO of the word driver 13a is turned off. When any one of sub-decode signals φX1 to φ×4 rises to the "H" level, the potential of the corresponding word line WL rises to the "H" level. However, if link element LNO is blown, node N1
The potential of word line WL is kept at "H" level, and as a result, the potential of word line WL is kept at "L" level. Therefore, if link element LNO is blown out in advance, four word lines WL corresponding to that row decoder 1)a will not be selected.

FIG. 14 shows the spare row decoder 12 included in FIG.
FIG. 2 is a diagram showing a specific circuit configuration.

This spare decoder 12 includes N-channel MOS transistors Qll-Q25 . P channel MOS transistor Q
26~Q30. It consists of link elements LNI to LN12.

Transistor Q29. Q30 is coupled in parallel between power supply potential VCC and node N3. transistor Q
ll to Q22 are link elements LNI to LN12, respectively.
It is coupled between node N3 and ground potential via. The gates of transistors Qll-Q22 are coupled to row selection signals X+''X, t, respectively. Transistors Q23 and Q24 are coupled in series between node N1 and ground potential. Transistors Q26 and Q27
are coupled in parallel between power supply potential VCc and node N1. Transistors Q23 and Q24 are connected in series between node N1 and ground potential. Transistor Q26. Q23. A precharge signal φ2 is applied to the gate of Q29. Also, transistor Q27. Q24
The gate of is connected to node N3. Transistor Q28 is coupled between power supply potential VCC and node N2, and transistor Q25 is coupled between node N2 and ground potential. Transistor Q28°Q25. Q30
The gate of is connected to node N1. Transistor Q23. Q24. Q26゜Q27 constitutes a two-man NAND gate, and transistors Q25. Q28 constitutes an inverter.

A spare row decoder 12 instead of the row decoder lla consisting of
is selected, the link elements LNI~LN
For example, it is assumed that a spare row decoder 12 is selected in place of the row decoder lla shown in FIG. 14.

The illustrated row decoder lla is selected when the row selection signals XI+XS and Xq are all at the "H" level, if the link element LNO is not disconnected. Therefore, link element LNO of row decoder lla and link elements LNI, LN5 . Fuse LN9 in advance.

When the precharge signal φ is at the "L" level, the transistor Q26 is on, the transistor Q23 is off, and the node N1 is precharged at the "H" level. Therefore, the node N2 is at "L" level. Furthermore, since the transistor Q29 is in the on state at this time, the node N3 is precharged to the "H" level, the transistor Q27 is in the off state, and the transistor Q24 is in the on state. When precharge signal I rises to the "H" level, transistor Q26 is turned off and transistor Q23 is turned on. As a result, the potential of node N1 becomes L'' level,
The potential of node N2 becomes H” level. At this time,
Transistor Q29 is turned off and transistor Q30 is turned on. Here, when the row selection signals X+, Xs, and Xq all become H" level, the transistors Q1) and Q15
．． Q19 turns on. However, these transistors Q
ll, Q15. Link element LN1.Q19 is connected to link element LN1.Q19.
LN5. Since LN9 is disconnected, the potential of node N3 remains at the "H" level and does not change. Therefore, the potential of node N1 is at L" level, and the potential of node N2 is at "H" level.
level is maintained. This state means that the spare row decoder 12 is in the selected state.

However, when at least one row selection signal other than Xt, Xs, and Xq goes to "H" level, Qll.

Q15. At least one transistor other than Q19 is turned on, and the potential of node N3 becomes "L" level. As a result, the transistor Q27 is turned on and the transistor Q24 is turned off, and as a result, the node N1 goes to "H" level.
Node N2 becomes "L" level. This state means that the spare row decoder 12 is in a non-selected state. In this way, link elements LNI, LN5 . When LN9 is disconnected, row selection signals X+, Xs, and Xq are “
When the level becomes H'', spare row decoder 12 is selected instead of row decoder lla.

Next, the operation of the semiconductor memory device shown in FIGS. 9 to 14 will be explained with reference to the timing chart in FIG. 15.

During the standby period when the precharge signal φ2 is at the "L" level, the potential of the node N1 of all the row decoders 1)a and the spare row decoder 12 is at the "H" level, and the potential of the node N2 is at the "L" level. For this reason,
All word lines WL and all spare word lines S
The potential of WL is at "L" level.

First, a case will be described in which a row decoder 1)a (hereinafter referred to as a normal decoder) corresponding to a normal memory cell MC and four normal word lines WL is selected. After precharge signal φ1 rises to “H” level, signal X! is applied to the selected row decoder 1)a. ,X
j and Xk are all at "H" level. As a result, the potential of node N1 falls to "L" level, and node N2
The potential rises to the "H" level. As a result, four corresponding word drivers 13a are selected.

Then, when one of the sub-decode signals φ8, .about.φX4 rises to the "H" level, the potential of the corresponding word line WL is raised to the "H" level by the word driver 13a. At this time, the potential of the spare word line SWL is "L"
″ level remains unchanged.

Next, the defective memory cell MC or defective word line WL
A case will be described in which row decoder 1)a (hereinafter referred to as a defective decoder) corresponding to row decoder 1)a is selected. After the precharge stone rises to the "H" level, the row selection signals X&, XJ,
All Xk are at "H" level. However, since the link element LNO of the defective decoder 1)a has been blown out in advance, the potential of the node N1 remains at the "H" level and the potential at the node N2 remains at the "L" level. Therefore, four word drivers 1 corresponding to this defective decoder lla
3a is not selected, and the sub decode signal φ8. .about..phi.X4 rises to the "H" level, the potential of the corresponding word line WL remains at the "L" level and does not change. At this time, the spare row decoder 12 is used instead of the defective decoder 1laO.
is selected, and as a result, one of the spare word lines SWL rises to the "H" level.

In the above case, in the row decoder 1)a (unselected decoder) not selected by the address signal, at least one of the applied row selection signals Xi, Xj, and Xk is low.
" level, so the potential of the node N1 remains at the "H" level and the potential at the node N2 remains at the "L" level.

Therefore, the potential of the corresponding word line WL is maintained at the "L" level.

As described above, even if a defective memory cell or defective word line occurs during the manufacturing stage, the device can be used as a normal semiconductor memory device by replacing the defective decoder with a spare decoder.

[Problem to be solved by the invention]

In the above semiconductor memory device, memory cell defects (
If defects such as bit defects), word line disconnections, and word line shorts within the same row decoder occur, these defects can be repaired by replacing the corresponding row decoder with a spare row decoder. . For example, as shown in FIG. 16, a break in the word line WL corresponding to the row decoders 1la-j (indicated by di) or a short circuit (indicated by d2) between the word lines WL corresponding to the row decoders 1la-j can be repaired. becomes. However, if a defect such as a short circuit between word lines in different row decoders occurs, there is a problem that the defect remains even if replacement with one spare row decoder is performed. For example, a short circuit (indicated by d3) between a word line belonging to row decoders 1la-j and a word line belonging to row decoders 1la-k cannot be repaired unless two spare row decoders are prepared. It is thought that such problems will become more prominent as the capacity of memory elements increases and the elements become further miniaturized.

This invention was made to solve the above-mentioned problems, and it is possible to repair various defects that occur during the manufacturing stage, especially short circuits between selection lines that span different decoders, without increasing the number of spare memory cells. The object of the present invention is to obtain a semiconductor memory device that can perform the following steps.

[Means to solve the problem]

A semiconductor memory device according to the present invention is a semiconductor memory device equipped with a redundant circuit, and includes a plurality of word lines.

A 4-way or more decoding system that includes multiple spare word lines, each of which has multiple memory cells connected to one of the multiple word lines, and has 4 or more word lines connected to a set of row decoders. As a spare selection means, two spare word lines are connected to one set of spare row decoders, and at least two sets of spare row decoders capable of replacing word lines with two rows are provided.

[Effect]

In this invention, by providing a plurality of spare row decoders, it is possible to repair a defect that spans two row decoders.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a semiconductor memory device including two sets of spare row decoders according to an embodiment of the present invention.

The semiconductor memory device of FIG. 1 is different from the semiconductor memory device of FIG. 9 because the number of spare word lines connected to the spare row decoder 42 is the same in the semiconductor memory device of FIG. The number of spare row decoders 42 is two (hereinafter distinguished as 42a and 42b), φKG
+ φ□ sub decoder 43 and sub decode signals φXI to φX4 are inactivated when selecting a spare word line,
The difference is that a spare row decoder selection signal generation circuit 44 that generates a signal 5REA or S RE n for activating the spare row decoder 42 is newly provided, and that the sub-decoder circuit 45 is different.

Further, in FIG. 1, generation of sub-decode signals φX1 to φX4 is achieved by decoding signal φ8 with signal RA and signal φXG+
Generates φXK, further decodes with signal RA, and generates φ. φX2+ φX4 from φ□, φXI+ from φ□
The difference is that it is configured to generate φ■.

The case where a normal decoder is selected is the same as the semiconductor memory device shown in FIG. 9, so the explanation will be omitted, and the operation when a defective decoder is selected will be explained.

When a selected word line is defective, when a signal to select the word line is issued, the spare row decoder selection signal generation circuit 4
The link in 4 is the spare row decoder selection signal 5REA,
5REB is set to "L", and the signal 5REA.

Row decoder group 1 in order to inactivate row decoder selection signals φX1 to φx4 by S RE m becoming “L”
) are all in a non-selected state, and instead, the spare row decoder 42 is activated when the signal S RE a or 5REI becomes "L". At this time, the signal φK generated by the φ8°, φ□ generation circuit 43
By inputting G or φXK, one of the spare word lines is selected and activated.

Next, the individual circuits will be explained.

FIG. 2 is a block diagram showing a detailed configuration of the memory cell array 1 and its peripheral portion included in FIG. 1.

Row decoder 1)a, word driver 13a, memory cell array 1 and sense amplifier 14a9 column decoder 19a
Regarding this, it is similar to the conventional example shown in FIG. Second
The figure differs from Figure 12 in 1. Spare row decoder 42
The difference in the configurations of 42a and 42b is that there are two spare word lines connected to one set of spare row decoders.
The number of spare word lines is the same as that of the conventional example shown in FIG. 2, and two spare row decoders 42a and 42b are mounted.

Therefore, it is possible to repair a defect caused by a word line short circuit between two row decoders.

FIG. 3 is a diagram showing the portion A-1 in FIG. 2 in more detail. In FIG. 3, word driver 13a
are transistors Q8., similar to the word driver 13a shown in FIG. Q9. Consists of QIO. row decoder llb
is the link LNO from the row decoder lla shown in FIG.
is removed. The spare row decoder 42a is a circuit to which a spare row decoder selection signal 5REA is input, and the spare row decoder 42b also has a circuit configuration different from that of the spare row decoder 42a, except that a spare row decoder selection signal S RE v is input. The same is true.

In FIG. 3, signals 5REA and 5REll are normally “H”.
” and the spare row decoder 42a.

42b is in an inactive state. If a defective word line exists and a signal to select the word line is output, the signal φx+
~φ×4 becomes inactive, and all word lines become unselected. On the other hand, signal 5REA.

5REII becomes "L", one of the spare row decoders 42a and 42b becomes active. For example, if the signal 5REA becomes "L", the spare row decoder 42a becomes active and the node N
4 becomes "H" and node N5 becomes "L". At this time again,
Spare word line selection signal φXG+ that is always in an inverted state
Since either one of φ□ is at "H", one of the spare word lines 5WL1 and 5WL2 becomes selected instead of the defective word line.

The signal 1]5 is also similar to the signal 5REa. In this case, either spare word line 5WL3 or 5WL4 is selected.

FIG. 4 shows the φKG+φ□ sub-decoder circuit 43. In the figure, Q40. Q42 is a P channel transfer transistor, Q41, Q43, Q44 . Q45. Q46 represents an N-channel transistor. The signal RA. generated in the row address buffer. is input, node N6 becomes "L".
Node N7 becomes "H".

Then, N-channel transistor Q46 becomes non-conductive. VCC is applied to the gate of N-channel transistor Q44.
Since the power supply voltage of V is applied, the potential of node N8 is V
((V(y). Here, V represents the threshold voltage of the N-channel transistor. When two signals φ boosted to more than VCC are input in this state, the potential of node N8 increases due to capacitive coupling. As a result, the boosted spare word line selection signal φX6 is output. Similarly, for the signal φ□, the inverted signal RA0 of the signal RAτ is output.
After inputting the signal φ8, the signal φ■ is outputted.

FIG. 5 shows the configuration of spare row decoder selection signal generation circuit 44 of FIG. 1. In the figure, Q47. Q4B
, Q51, Q52, Q55, Q57, Q5B, Q59 are P-channel transistors, Q49, Q50, Q
53, Q54. Q56, Q60 to Q73 represent N-channel transistors, and LN2Q to LN33 represent link elements. Further, φ is an inverted signal of the precharge signal φ2.

In FIG. 5, since links LN20 to LN33 are normally connected, the address signal RA.

~RAT becomes conductive due to the input of any one of N-channel transistors Q60 to Q73, so the potential of node N9 becomes "L" and the spare row decoder selection signal SREA becomes "H". There is.

If a defective word line exists, if the link corresponding to the transistor to which the address signal for selecting the defective word line is input is fused in advance with a laser beam, the address signal for selecting the defective word line will be transmitted to the transistors Q60 to Q60.
Even if input to Q73, the potential of node N9 does not fall to “H”
As a result, the spare row decoder selection signal SREA
becomes “L”.

FIG. 5 explains the spare row decoder selection signal SREA, and the spare row decoder selection signal S RE m
The same circuit configuration is also used for .

FIG. 6 is a circuit diagram showing the φ8 sub-decoder 45 included in the semiconductor memory device of FIG. 1.

In the figure, Q74. Q75. Q7B, Q79. Q85 is a P-channel transistor, Q76, Q7? .

Q80. Q81. Q82. Q83. Q84. Q86,Q
87. Q88. Q89 represents an N-channel transistor.

Normally, the spare row decoder selection signals 5REA and SRE are both "H", so the node N10 is "L".
By inputting the address signal RA +, the node Ni
Since transistor Q83.1 becomes "H" and node N12 becomes "L". Q88 is conductive, transistor Q84.
Q89 becomes non-conductive, and if the signal φX6 is “H”, the row decoder selection signal φ8□ becomes “H”, and the signal φ□
is "H", row decoder selection signal φ becomes "H".

The same applies to row decoder selection signals φX3+φX4.

If a word line defect exists, one of the spare row decoder selection signals S REA and S REB becomes "L", so the potential of node NIO becomes "H", node Nil becomes "L", and node N12 becomes "H". ”, and all row decoder selection signals φ×, to φx4 become “L”.

If a word line defect occurs in one row decoder, for example, d5. If the defect is due to a word line short circuit as indicated by d5, it can be repaired by setting only one of the spare row decoders 42a and 42b in FIG. 8, which shows the spare row decoders and spare word lines. is possible.

In addition, word lines WL2 and WL indicated by d7 in FIG.
3, the spare row decoder 42 in FIG.
Relief is possible by setting both a and 42b.

Defect relief when a word line defect occurs between two adjacent row decoders will be described below.

For example, a word line WL as indicated by d4 in FIG.
4 and WL5 are short-circuited, the spare row decoder 42a
Word line WL4 connected to row decoder 1lb-j by
, row decoder 1 l by spare row decoder 42b
By relieving the word line WL5 connected to bk, defect relief becomes possible.

As described above, in this embodiment, in a semiconductor memory device including a plurality of word lines WL and a plurality of spare word lines SWL, the signal A which is the basis for selecting a word line WL is used.
0 to A, two sets of first sub-decode signals φKG+ φXK in which the signal is decoded with the least significant bit, and the first sub-decode signal φXG+ φ□ in the bit immediately above the least significant bit. A second sub-decode signal φ is generated using four sets of second sub-decode signals φ□ to φX4, each of which is decoded. ~φX4 is input to each of the four word lines WL of the 4-way system, and the first sub-decode signal φXG+φXK is input to the spare word line SW.
Since we adopted a decoding method in which the input is input to two spare word lines SWL, which are replaced as a unit when L is used, two It becomes possible to repair defects that extend across row decoders, and the manufacturing yield of the device increases.

Furthermore, by adopting such a redundant configuration, there is an advantage that selection of a dummy word line becomes extremely easy. For example, in the case of the dummy reversal method, regardless of whether a normal decoder or a spare decoder is selected for the dummy word line, the signal φXG connects the dummy word line DWLc, and the signal φ□ connects the dummy word line Line D
The configuration may be such that WLX is pulled down.

In the above embodiment, two spare row decoders are both arranged on one side of the row decoder group, but one spare row decoder may be arranged on both sides of the row decoder group.

Furthermore, it goes without saying that the present invention can be applied not only to 4-way decoding methods but also to more decoding methods.

〔Effect of the invention〕

As described above, according to the present invention, in a decoding system with 4 or more lines, the spare row decoder that can replace one set of two word lines is provided with a spare row decoder of 2 m or more, so that the same spare word line as the conventional one can be used. It is possible to repair a defective word line between two row decoders by increasing the number of row decoders, and there is an effect that a semiconductor memory device with a dramatically improved manufacturing yield can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing the detailed configuration of the memory cell array shown in FIG. 1 and its peripheral parts, and FIG. 2 is a circuit diagram showing a more detailed configuration of the part A-1 in FIG. 2, FIG. 4 is a specific circuit diagram of the sub-decoder for φ FIG. 6 is a specific circuit diagram of the φ8 sub-decoder shown in FIG. 1, and FIGS. 7 and 8 are each an embodiment of the present invention. FIG. 9 is a block diagram showing the configuration of a conventional semiconductor memory device, and FIG.
Figure 1) is a diagram showing the detailed configuration of the main part of the row predecoder shown in Figure 1). Figure 12 is a diagram showing the detailed configuration of the φ8 sub-decoder shown in Figure 9. A diagram showing a detailed configuration of a memory cell array and its peripheral parts,
13 is a circuit diagram showing a more detailed configuration of the main part of FIG. 12, FIG. 14 is a specific circuit diagram of the row decoder and spare row decoder shown in FIG. 12, and FIG. 15 is a circuit diagram of a conventional semiconductor Timing chart diagram 16th for explaining the operation of the row decoder and spare row decoder of the storage device
The figure is a diagram for explaining defects that can be repaired by a conventional semiconductor memory device. In the figure, 1) is a row decoder group, 422.42b is a spare row decoder, Q is a transistor, WL is a word line,
MC is a memory cell, SWL is a spare word line, and SMC is a spare memory cell. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A plurality of word lines, a plurality of spare word lines, a plurality of memory cells each connected to one of the plurality of word lines, and a plurality of memory cells each connected to one of the plurality of spare word lines. In a decoding type semiconductor memory device comprising spare memory cells, four or more word lines are connected to a set of row decoders, and one of the four or more word lines is selected, A semiconductor memory device comprising at least two sets of spare row decoders to which two of the spare word lines are connected and which can replace the word lines with one set of two.