KR100512159B1 - Pad layout for semiconductor memory device - Google Patents

Abstract

A semiconductor memory device according to the present invention includes a plurality of cell array blocks having a plurality of memory cells for storing information, arranged in rows and columns; At least two potential application pads for supplying an externally applied potential corresponding to the high potential to the cell array blocks to perform an operation that requires a relatively high potential relative to an internal potential, such as burn-in.

Description

Pad layout of semiconductor memory device {PAD LAYOUT FOR SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a layout of a potential application pad arrangement provided in a semiconductor memory device.

Recently, various kinds of internal potentials (Internal DC Votage) are used in the semiconductor-related products to ensure the normal driving of the chip. Examples thereof include various reference voltages, bulk voltages, boosting voltages, pre-charge voltages, and capacitor pole plate voltages of DRAM cells.

These various internal potential levels use pads, and the purpose of the pads is firstly for external level monitoring of the potential, and secondly forcing the potential internally through the pad from the outside. Therefore, it is intended to apply potential other than output level (Self Level) by internal potential generator to internal circuit stage and use it for analysis of product's operation characteristics and defects.

However, when a potential is forcibly applied to the chip through the pad, the internal resistance formed by the transmission line and the circuit terminal and the loading determined by the parasitic capacitor are large to ensure the level of the internally applied potential accurately. Pad application (e.g., forcing) time is required to be quite long, which causes a number of problems, such as difficult to guarantee the level of the internal potential accurately.

In particular, a special purpose operation of the product, such as wafer burn-in, is applied to the product, and thus a method of implementing the operation by forcibly applying the potential through the internal potential pad is utilized, while applying a potential into the chip through the pad. Is increasingly being used.

1 is a layout showing a pad arrangement for potential application according to the prior art, and FIG. 2 is an equivalent circuit diagram according to the pad arrangement of FIG. 1. As shown in Fig. 1, according to the prior art, although the chip area of the product is increased and the internal loading is greatly increased compared to the normal operation by the special purpose operation of the product such as wafer burn-in, the pad for applying the level Depends on one.

In this case, as can be seen in the equivalent circuit diagram of FIG. 2, since the internal resistance (R1 + R2) and the loading are both viewed when the external potential is applied, the applied current of the chip is limited by the internal resistance. In other words, the parasitic capacitance C1 + C2 causes a problem that the actual internal potential is different for each chip site. For example, as shown in FIG. 5, the partial potential N3 on the side farthest from the application pad has a problem in that the potential at a specific time is different from that of the nearest side N2.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of minimizing the time required when an internal potential level is applied through an external pad when a large internal loading is connected to the normal operation by an operation such as an increase in chip area or burn-in. To provide a pad layout.

(Configuration)

According to one aspect of the present invention for achieving the above object, a plurality of cell array blocks having a plurality of memory cells for storing information, arranged in rows and columns; At least two potential application pads for supplying an externally applied potential corresponding to the high potential to the cell array blocks to perform an operation that requires a relatively high potential relative to an internal potential, such as burn-in.

In this embodiment, the pads are arranged in a direction to disperse the overall internal loading.

(Action)

By such an apparatus, it is possible to minimize the time required when applying the internal potential level through the external pad and to ensure the correct applied potential.

(Example)

Reference will now be made in detail with reference to FIGS. 3 to 5 according to an embodiment of the present invention.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details.

3 is a layout showing a pad arrangement for potential application according to the present invention. 4 is an equivalent circuit diagram according to the pad arrangement of FIG. 3, and FIG. 5 is a diagram illustrating a potential delay time of the present invention and the prior art.

Referring to FIG. 3, a plurality of array blocks are arranged in rows and columns. For convenience, in the embodiment of the present invention, the array blocks are composed of four blocks. A plurality of pads corresponding to the array blocks ARRAY BLOCK 1 and ARRAY BLOCK 2 and ARRAY BLOCK 0 and ARRAY BLOCK 3 arranged in the column direction are disposed.

Of the plurality of pads, the potential applying pads PAD1 and PAD2 for applying an external potential to forcibly boost the internal potential from the outside for the special purpose described above are corresponding to the array blocks ARRAY BLOCK. 1) and (ARRAY BLOCK 2) and (ARRAY BLOCK 0) and (ARRAY BLOCK 3).

The present invention provides a layout for disposing the potential applying pads to solve the conventional problems that may occur when applying levels through the pads for internal potentials with relatively large internal loadings. When such a layout is applied, when the internal loading is increased due to the increase of the area due to the large capacity of the product and the operation for the special purpose of the product such as wafer burn-in, the time required for external application of the level of the internal DC potential is applied. Minimize and ensure accurate applied potential.

More specifically, as shown in FIG. 4, in which the potential application pad is viewed internally, the external potential is dispersed by dispersing the internal resistance R1 or R2 and the loading C1 or C2 according to the parasitic capacitor. It is possible to effectively reduce the potential arrival time required during application. As a way to solve this problem, the internal potential transmission line can be formed to be wider to reduce the resistance, but there are limitations on the layout and the improvement effect will be insignificant since the intrinsic plane resistance value of the transmission line itself is small.

Referring again to FIG. 3, in accordance with the present invention, the positions of the potential application pads PAD1 and PAD2 are arranged in the direction of distributing the internal loading as much as possible in the full loading model, and the portion where the internal loading is most viewed. The decision should be made in such a way as to minimize the difference between small parts. As can be seen from the diagram of FIG. 5 showing the improvement effect according to this, it can be seen that the application potential arrival time of the specific portion (eg, N2 and N3) according to the layout of the present invention is relatively reduced compared to the conventional layout.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, when a large internal loading is connected to the normal operation by an operation such as an increase in chip area or burn-in, the time required for applying the internal potential level through the external pad can be minimized, The applied potential can be guaranteed.

1 is a layout showing a pad arrangement for potential application according to the prior art;

2 is an equivalent circuit diagram according to the pad arrangement of FIG. 1;

3 is a layout showing a pad arrangement for dislocation application according to the present invention;

4 is an equivalent circuit diagram according to the pad arrangement of FIG. 3;

5 shows the potential delay time of the present invention and the prior art,

* Explanation of symbols on the main parts of the drawings

R1, R2: internal resistance C1, C2: parasitic capacitance

Claims (1)

A plurality of cell array blocks having a plurality of memory cells for storing information and arranged in rows and columns; At least two potential application pads for supplying an externally applied potential corresponding to the high potential to the cell array blocks to perform an operation requiring a relatively high potential relative to an internal potential, such as burn-in, The potential applying pads are disposed in a direction in which the most facing portion and the least facing portion are viewed in the full loading model.

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