KR100631911B1 - method for testing redundancy memory cells in semiconductor memory device - Google Patents

Abstract

In the disclosed semiconductor memory device to increase repair efficiency, the method of testing a redundant memory cell may receive the redundancy low test signal so that a redundant main word line connected to the redundant memory cell may be sequentially enabled even in a state before the repair process. Sequentially generating a plurality of redundancy main word line enable signals through a redundancy main word line counter; Applying the plurality of redundant main word line enable signals to a redundant main row decoder to enable corresponding redundancy main word lines; Applying a block address for normally applying an external row address and selecting a normal block, but disabling the normal block using a redundancy main block signal; Sequentially generating a plurality of redundancy main column line enable signals through a redundancy main column line counter receiving a redundancy column test signal; And applying a plurality of redundancy main column line enable signals to a redundancy main column decoder to enable corresponding redundancy main column lines.

Semiconductor Memory Device, Redundant Memory Cell Test, Laser Fuse, Repair Efficiency

Description

Method for testing redundancy memory cells in semiconductor memory device             

1 is a circuit block diagram illustrating a word line and a column line of a semiconductor memory device according to an embodiment of the present invention.

2 is a layout view of redundancy main word lines and column lines in a memory cell array;

FIG. 3 is a redundancy low test timing diagram related to FIG. 1.

4 is a redundancy column test timing diagram related to FIG. 1.

TECHNICAL FIELD The present invention relates to the field of semiconductor memory, and more particularly, to a method of testing a redundant memory cell in a volatile semiconductor memory device such as a highly integrated static RAM and the like.

Typically, when fabrication of a semiconductor memory device is completed in a wafer state, each chip on the wafer is subjected to various tests. Such tests are necessary to determine whether the circuit elements of each chip operate to a predetermined specification, and various test parameters are used in the test to check various electrical characteristics and operations of the chip. As a result of the test, if any one of the control circuits in the semiconductor memory chip is defective, defect repair of the semiconductor memory device is virtually impossible. If the memory cell in the memory cell array is defective, the repair process is performed by performing a redundancy memory. The replacement of the cell allows the defect to be repaired. In other words, when some of the normal memory cells are determined to be defective, the spare memory cells can be replaced with spare memory cells, which can operate as a normal semiconductor memory device. As such, a fuse circuit including fuses meltable by high energy light such as a laser for defect repair is made together in the manufacture of memory cells and circuit elements of a semiconductor memory device.

Redundant fuse circuits in conventional semiconductor memory devices are disclosed in US Pat. No. 5,933,382, issued August 3, 1999. With such a circuit, a redundant memory cell or block is selected by the decoding circuit instead of the defective memory cell or block to write / read data. The fuse programming is an address code cutting operation, which is an important task of increasing the manufacturing yield of integrated circuits by repairing defective memory cells or blocks. Therefore, if a redundant fuse circuit is manufactured and a normal memory cell is defective, opening a fuse associated with its address allows the redundant memory cell corresponding to the fuse open information to be driven in place of the defective normal memory cell. As can be seen, fuse programming is usually performed in a state in which redundancy memory cells are normally operated without prior testing.

Therefore, when the redundancy memory cell replaced by the repair process also has a defect in a subsequent test process, the repair process becomes useless and the repair efficiency is deteriorated. Therefore, a technique capable of increasing the repair efficiency is desired.

Accordingly, an object of the present invention is to provide a redundancy memory cell test method that can solve the above problem.

Another object of the present invention is to provide a redundancy memory cell test method for performing a repair memory cell test in a normal memory cell test process performed before performing a repair process.

It is still another object of the present invention to provide a redundancy memory cell test method capable of increasing repair efficiency.

According to one aspect of the present invention for achieving the above objects and other objects, the redundancy memory cell test method,

Disabling the normal main word line by applying an external row address for selecting a normal main word line and applying a column address normally, and providing a redundancy low test signal through a pin during a low redundancy memory cell test; A plurality of redundant main word line enable signals are sequentially provided through a redundant main word line counter that receives the redundant low test signal so that the redundant main word lines connected to the redundant memory cells can be sequentially enabled even before the repair process. Generating to; Applying the plurality of redundant main word line enable signals to a redundant main row decoder to enable corresponding redundancy main word lines; Applying a block address for normally applying an external row address and selecting a normal block, but disabling the normal block using a redundancy main block signal; Sequentially generating a plurality of redundancy main column line enable signals through a redundancy main column line counter receiving a redundancy column test signal; And applying the plurality of redundancy main column line enable signals to a redundancy main column decoder to enable corresponding redundancy main column lines.

According to the present invention described above, since the redundancy memory cell test can be performed together with the normal memory cell test before the repair process, the repair efficiency is increased.

The above and other objects, features, and operational advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention described below with reference to the accompanying drawings. It should be noted that the same or similar parts to each other in the drawings are described with the same or similar reference numerals for convenience of explanation and understanding.

1 is a circuit block diagram illustrating a word line and a column line of a semiconductor memory device according to an exemplary embodiment of the present invention. In the drawing, the redundancy main word line (RMWL) counter 10 and the redundancy main block / column line counter 50 respectively provide the redundancy low test signal and the redundancy column test signal applied through the redundancy low test pin and the redundancy column test pin. Each count is received. FIG. 1 illustrates an example of a configuration that is applied when the redundancy main word line RMWL and the redundancy column line RMCL in the memory cell array 100 are arranged in two lines, respectively. Therefore, when the redundancy main word line RMWL and the redundancy column line RMCL increase in number, the redundancy main word line counter 10 and the redundancy main block / column line counter 50 of FIG. Create a large number of them. The first and second redundancy main row decoders 20 and 21 are connected to the redundancy main word line counter 10 through lines L2 and L3, respectively, and the first and second redundancy main column decoders 60 and 61 respectively. Are connected to the redundancy main block / column line counter 50 via lines L4 and L5, respectively. The first normal main row decoder 30 of the plurality of normal main row decoders is connected to the redundancy low test pin through line L1. The redundancy low test signal REDR_Test applied through the redundancy low test pin has a timing of transition to a high level during the redundancy low test as shown in FIG. 3. The redundancy column test signal REDC_Test applied through the redundancy column test pin has a timing to transition to a high level during the redundancy column test as shown in FIG. 4.

Hereinafter, the operation of FIGS. 1 and 2 will be described with reference to FIGS. 3 and 4.

3 is a redundancy row test timing diagram related to FIG. 1, and FIG. 4 is a redundancy column test timing diagram related to FIG. 1. First, referring to FIG. 3, in the low repair cell test, the external clock signals XKB and XK are fixed to decode the main word line MWL1 of FIG. 2 using the redundancy low test pins, and the redundancy main low of FIG. The redundancy main word line enable signals PMWLRED1 and PMWLRED2 are sequentially generated by the redundancy main word line counter 10 to enable the redundancy main word lines without the repair fuse cutting in the decoder 20. The first and second redundancy main row decoders 20 and 21 receive the enable signal of the redundancy main word line counter 10 through lines L2 and L3, respectively, and generate output signals RMWL1 and RMWL2. . The output signals RMWL1 and RMWL2 are signals for enabling the redundancy main word lines RMWL1 and RMWL2 of FIG. 2. In this case, the column address is normally enabled and tested, and the normal main word line MWL1 goes unselected by the redundancy low test pin as shown in FIG. 3. In this way, an external row address for selecting a normal main word line is applied and a column address is normally applied. However, when a low redundancy memory cell is tested, a redundancy low test signal is provided through a pin to disable the normal main word line and provide low redundancy. A memory cell test is performed. Redundant main word line enable through a redundant main word line counter 10 that receives the redundancy low test signal so as to enable the redundancy main word lines connected to the redundancy memory cells in order even before the repair process. By generating signals sequentially and applying the plurality of redundant main word line enable signals to the redundant main row decoders 20 and 21 to enable corresponding redundancy main word lines, a repair process such as a laser is performed. It can be seen that the redundancy memory cell test is performed in the low direction before the following. Therefore, it is possible to increase the repair efficiency since the repair can be properly performed to the redundant memory cells without defects by using this information when repairing, in advance, whether the repair cell is defective before the laser cutting process, that is, the repair process.

Referring to FIG. 4, the column redundancy memory cell test will be described. In the column repair cell test, the signal of the waveform REDC_Test shown in FIG. 4 is applied to the redundancy column test pin shown in FIG. 1. The RMBL RMCL counter 50 sequentially generates the redundancy main column line enable signals PMCLRED1 and PMCLRED2, and the redundancy main column decoders 60 and 61 which receive the redundancy main column lines enable signals PM and the corresponding redundancy main column lines of FIG. By generating the redundancy column select signals RMCL1 and RMCL2 that enable RMCL1 and RMCL2, the column repair cells are tested. In this case, the row address is normally enabled and the block except the redundancy block is disabled using the output signal PMBLRED1 of the counter 50 to disable the normal block. Give a block address that allows the normal block to be selected to prevent conflicts with normal cell tests. That is, the external row address is normally applied and a block address for selecting a normal block is applied, but the normal block is disabled by using the redundancy main block signal. In this way, a plurality of redundant main column line enable signals are sequentially generated through a redundant main column line counter that receives a redundancy column test signal, and the plurality of redundant main column line enable signals are applied to a redundancy main column decoder. By enabling the corresponding redundancy main column line, testing of redundancy memory cells in the column direction is possible prior to the repair process.

On the other hand, testing of the redundancy row and column cross point is accomplished by running the row and column direction tests simultaneously.

The present invention has been described based on the embodiments based on the illustrated drawings, but is not limited thereto, and various changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is obvious that other embodiments may be modified, as well as equivalent embodiments. For example, one of the tests in the row and column direction can be performed first and the configuration of the counter can be varied if the matter permits.

Therefore, the technical protection scope of the present invention will be defined by the technical matters described in the claims.

As described above, according to the present invention, since the redundancy memory cell test can be performed together with the normal memory cell test before the repair process, the repair efficiency is increased.

Claims (3)

A redundancy memory cell test method in a semiconductor memory device, comprising: Disabling the normal main word line by applying an external row address for selecting a normal main word line and applying a column address normally, and providing a redundancy low test signal through a pin during a low redundancy memory cell test; A plurality of redundant main word line enable signals are sequentially provided through a redundant main word line counter that receives the redundant low test signal so that the redundant main word lines connected to the redundant memory cells can be sequentially enabled even before the repair process. Generating to; Applying the plurality of redundant main word line enable signals to a redundant main row decoder to enable corresponding redundancy main word lines; Applying a block address for normally applying an external row address and selecting a normal block, but disabling the normal block using a redundancy main block signal; Sequentially generating a plurality of redundancy main column line enable signals through a redundancy main column line counter receiving a redundancy column test signal; And applying a plurality of redundancy main column line enable signals to a redundancy main column decoder to enable corresponding redundancy main column lines. 2. The method of claim 1 wherein the row and column direction tests are performed simultaneously for testing redundancy rows and column cross points. The method of claim 1, wherein the redundancy memory cell test is performed after a normal memory cell test and before a laser repair process.

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