KR20030093410A - Burn-in control circuits of redundancy memory cell in memory device and method same - Google Patents

Abstract

PURPOSE: A circuit for controlling the burn-in of a redundancy memory cell in a semiconductor memory device and a method for controlling the same are provided to previously prevent the defect occurrence of redundancy memory cell replaced by the repair process by screening the status of failure at once, thereby increasing the efficiency of repair. CONSTITUTION: A circuit for controlling the burn-in of a redundancy memory cell in a semiconductor memory device includes a burn-in counter(12) and a burn-in redundancy decoding unit(16). The burn-in counter(12) generates a burn-in address signal, a burn-in address carry signal and a redundancy burn-in signal by counting a burn-in clock supplied from outside by the activation of the burn-in enable signal. And, the burn-in redundancy decoding unit(16) generates a redundancy word line enable signal to activate a corresponding redundancy word line among the redundancy word lines of the redundancy memory cell array by decoding the burn-in address carry signal by the activation of the generated redundancy burn-in signal and the burn-in enable signal.

Description

BURN-IN CONTROL CIRCUITS OF REDUNDANCY MEMORY CELL IN MEMORY DEVICE AND METHOD SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a circuit and a control method for controlling a normal memory cell and a redundancy memory cell to be burn-in tested simultaneously in a wafer state.

Typically, when fabrication of a semiconductor memory device having a large number of memory cells for storing data is completed in a wafer state, each memory chip on the wafer is subjected to various tests. For example, a test for detecting a defect of a memory cell and its driving circuit, etc. may be representative. At present, semiconductor memory chip makers apply the burn-in process in the state of wafer processing in order to increase the production yield, and then perform the wafer level burn-in test process that screens semiconductor performance and defects at the wafer stage. Is running. The wafer burn-in test as described above is essential to determine whether the circuit elements of each chip are operated to a predetermined specification, and various electrical parameters and operating states of the chip are inspected by using various parameters during the test. As a result of the test, when a defect of a memory cell located in the memory cell array is found, the repair process is performed to replace the redundant memory cell so that it can operate as a normal semiconductor memory device. As such, a fuse circuit including fuses meltable by high energy light such as a laser for defect repair of a defective memory cell is made together in the manufacture of a redundant semiconductor memory cell and circuit elements of a semiconductor memory device.

Redundant fuse circuits in semiconductor memory devices are already well known to those skilled in the art. By the redundant fuse circuit as described above, instead of the defective memory cell or block, the redundant memory cell or block is selected by the decoding circuit to read or write data. The fuse program is a kind of address code cutting operation that repairs a defective memory cell or block to increase the manufacturing yield of an integrated circuit. Therefore, when a redundant fuse circuit is manufactured and a defective normal memory cell is opened, when a defective address program fuse associated with the address is opened, the normal memory cell in which the corresponding redundant memory cell is defective by the open program information of the fuse is generated. It can be seen that it can be driven instead. Therefore, in order to further increase the yield of the semiconductor memory device, it is required to test whether the redundancy memory cell operates normally.

Redundant memory cell control circuits and methods, and methods for testing redundancy memory cells are disclosed in Korean Patent Registration No. 10-0234377 (Redundant memory cell control circuit and its control method of a memory integrated circuit; Patents) and the techniques disclosed in Korean Patent Application Laid-Open No. 2001-0073745 (A Redundant Memory Cell Test Method in Semiconductor Memory Devices; hereinafter referred to as "Public Patent"). .

The above patent discloses a circuit for accurately controlling an operating state of a redundancy memory cell when burn-in testing a semiconductor memory device having redundancy memory cells, wherein the normal memory cells are replaced by the redundancy memory due to an error despite a defect in the general memory cells. It only has a control circuit that is not replaced by cells, but does not have a circuit that simultaneously performs burn-in tests of normal memory cells and redundant memory cells.

The patent discloses a method of performing a test of a redundancy memory cell in a normal memory cell test process performed before performing a repair process, but the wafer burn-in test of the normal memory cell and the redundancy memory cell cannot be performed simultaneously. It is. In addition, the disclosed patent is operated to receive a test signal provided from the outside of the chip after entering the test mode in order to test the redundant memory cells.

Accordingly, an object of the present invention is to provide a configuration of a semiconductor memory device and a test method thereof in which burn-in tests of redundant memory cells are simultaneously performed during burn-in tests of normal memory cells.

Another object of the present invention is to provide a burn-in control circuit of a redundant memory cell in a semiconductor memory device and a method of controlling the same, capable of simultaneously performing row and column redundancy cell tests and cross-point cell tests through a single memory cell burn-in test. have.

It is still another object of the present invention to provide a control circuit and a control method for automatically performing a burn-in test of a redundant memory cell during burn-in test of a normal memory cell without entering an additional test mode or using an external signal for burn-in test of the redundant memory cell. In providing.

The burn-in control circuit of a redundant memory cell according to an aspect of the present invention for achieving the above objects is a normal memory cell array having a plurality of main word lines, and a redundant memory cell array having a plurality of redundancy word lines. A semiconductor memory device comprising: a burn-in counter for generating a burn-in address signal, a burn-in address carry signal, and a redundancy burn-in signal by counting a burn-in clock provided from the outside by activating the burn-in enable signal; And a normal low word line decoder for decoding the burn-in address signal to enable the corresponding main word line among the main word lines of the normal memory cell array, and activating the generated redundancy burn-in signal and the burn-in enable signal. Decode burn-in address carry signal Including deonsi memory generates a redundancy word line enable signal to one of the redundancy word lines of the cell array in the redundancy wordline enable the burn-in redundancy decoding unit which is characterized in that configuration.

According to the present invention having the above configuration, when the memory cells in the normal memory cell array are burned in by using the burn-in counter, the defects of the redundant memory cells replaced by the repair process by burning in the redundant memory cells in the redundant memory cell array together The occurrence can be prevented in advance, so that the efficiency of the recycling can be increased.

1 is a block diagram of a burn-in control circuit of redundancy memory cells of a semiconductor memory device according to a preferred embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of FIG. 1 and illustrates timing diagrams of a main word line and a redundancy word line at burn-in of a normal memory cell and a redundant memory cell.

3 is a circuit diagram of an embodiment of the burn-in redundancy decoder shown in FIG.

4 is a circuit diagram of an embodiment of the low redundancy decoder shown in FIG.

5 is a circuit diagram of an embodiment of the column redundancy decoder shown in FIG.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in more detail with reference to the accompanying drawings in which: FIG. It should be understood, however, that the present invention may be embodied in many different forms and should not be limited to the described embodiments. It should be noted that the following examples are intended to be illustrative and to sufficiently convey the spirit of the present invention to those skilled in the art. It should also be noted that detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention are omitted.

As will be appreciated by those skilled in the art, in semiconductor memory devices, normal memory cell arrays and redundant memory cell arrays and control circuits for driving them are well known in the art. Therefore, in the following drawings, the details related to the memory cell arrays are not described in detail.

1 is a block diagram of a burn-in control circuit of a redundancy memory cell of a semiconductor memory device according to a preferred embodiment of the present invention. Referring to FIG. 1, the burn-in address WBI_ADD (WBI_address) and the burn-in address carry CA0, CA1 and the burn-in enable signal are activated by a wafer burn-in enable signal (WBI) to count the burn burn-in clock (WBIK). It has a burn-in counter 12 that generates a redundancy burn-in signal WBI_B0 (WBI_burn-in). The burn-in counter 12 decodes the burn-in address signal so that the corresponding main word line MWLi (where i is 0, 1, 2, 3, etc.) among the main word lines MWL <0 to n> of a normal memory cell array (not shown). Is connected to a normal low word line decoder 14. Further, another output terminal of the burn-in counter 12 includes a redundancy memory cell array (not shown) by decoding the burn-in address carry signals CA0 and CA1 by activation of the generated redundancy burn-in signal WBI_B0 and the burn-in enable signal WBI. The burn-in redundancy decoding unit 16 for generating a redundancy word line enable signal for activating the corresponding redundancy word line RMWLi among the redundancy word lines RMWL <0 to 3> is connected. Reference numeral 18 denotes a column redundancy decoder, which has a function of decoding a column address input from the outside and generates an enable signal RYB of the column redundancy memory cell array in response to activation of the burn-in enable signal WBI.

Among the above configurations, the burn-in redundancy decoding unit 16 decodes the burn-in address carry signals CA0 and CA1 by activating the redundancy burn-in signal WBI_B0 and the burn-in enable signal WBI to redundancy burn-in word line enable signal WBI_EN <0 ~. A redundancy enable signal having a function of decoding the row address signal and generating a low redundancy enable signal when the redundancy burn-in word line enable signal WBI_ENi is active. A low redundancy decoder 22 that enables the wordline RMWLi.

1 is a structure to be applied when there are four low redundancy word lines, and the configuration according to the present invention should be changed according to the number of low redundancy word lines, and the scope of the technical idea according to the present invention. It should be noted that can not be escaped.

FIG. 2 is a timing diagram illustrating the operation of FIG. 1 and illustrates timing diagrams of a main word line and a redundancy word line at burn-in of a normal memory cell and a redundant memory cell.

First, the operation of the burn-in control circuit of a redundant memory cell in a semiconductor memory device constructed in accordance with a preferred embodiment of the present invention will be described with reference to FIGS. 1 and 2.

Now, when the burn-in enable signal WBI is activated as shown in FIG. 2 to burn-in the memory cells in the normal memory cell array and the redundant memory cell array, the burn-in counter 12 is provided from outside as shown in FIG. The burn-in clock signal WBIK is counted to generate a burn-in address signal WBI_ADD which is sequentially increased and provided to the normal low word line decoder 14 connected to the output terminal.

At this time, the normal low word line decoder 14 decodes the burn-in address WBI_ADD and generates a normal word line enable signal for sequentially enabling a plurality of normal main word lines MWL <0 to n> as shown in FIG. 2. Accordingly, when the burn-in enable signal WBI and the burn-in clock WBIK are input from the outside, the normal word line MWLis are enabled in the net search as shown in FIG. 2, and the memory cells in the normal memory cell array are burned in as described above. The normal low word line decoder 14 may use the current memory cell burn-in test circuit.

In addition, the burn-in counter 12 outputs the redundancy burn-in signal WBI_B0 and increases the burn-in address carry signals CA0 and CA1 when the count-in address P is completed, as shown in FIG. In this case, the burn-in redundancy decoder 20 for inputting the redundancy burn-in signal WBI_B0 and the burn-in address carry signals CA0 and CA1 generated at each predetermined period P is the redundancy burn-in word line enable signal WBI_ENi as shown in FIG. 2 (where i is 0, 1, 2). Natural numbers). The low redundancy decoder 22 decodes the row address signal RAi to generate a low redundancy enable signal, and the redundancy word line RWLi is generated by the generated low redundancy enable signal in the activated redundancy burn-in word line enable signal WBI_ENi. Enable as shown to burn-in of the low redundancy memory cell. This operation will be more clearly understood by the description of the detailed circuit described below.

Meanwhile, the column redundancy decoder 18 decodes the column address signal CLAi to generate a column redundancy enable signal, and activates the column redundancy enable signal RYB in response to activation of the burn-in enable signal WBI input from an external source. Allow the cell to burn in at the same time.

As a result, when the normal word line is enabled during the burn-in test of the memory cell in the normal memory cell array, the low redundancy word line RMWLi is simultaneously enabled at a constant period P so that the memory cells in the redundancy memory cell array are also burned in together. .

FIG. 3 is a circuit diagram of the embodiment of the burn-in redundancy decoder 20 shown in FIG. 1, showing two inverters 24, 26 and a plurality of inverters for decoding the burn-in address carry CA0, CA1 to output the redundancy burn-in wordline enable signal WBI-ENi. NAND gates 28 to 34 and NAND gates 44 for generating an output control signal when the redundancy burn-in signal WBI_B0 and the burn-in enable signal WBI are both in the active state, and the output terminals of the NAND gates 28 to 34 respectively. And NOR gates 36 to 42 connected to one terminal and gating the decoded redundancy burn-in word line enable signal WBI_ENi in response to an output of the NAND gate 44.

The burn-in redundancy decoder 20 configured as shown in FIG. 3 decodes the burn-in address carry signals CA0 and CA1 which are sequentially increased among the signals generated at the burn-in counter 12 to two inverters 24, 26 and four NAND gates 28 to 34. . The decoded result is outputted through the Noah gates 26 to 42 by the redundancy burn-in signal WBI_B0 activated every predetermined period P in the burn-in counter 12 and the burn-in enable signal WBI activated during the burn-in test. That is, the redundancy burn-in enable signal WBI_ENi is generated according to the states of the burn-in address carry signals CA0 and CA1 and the redundancy burn-in signal WBI_B0. As a result, as shown in FIG. 2, when the normal word line MWLi is enabled at every constant period P, the redundancy word line RMWLi is also enabled one by one. In the above configuration, since the NAND gate 44 is not in the burn-in mode, the burn-in enable signal WBI provided from the outside is deactivated. Do not affect.

FIG. 4 is a circuit diagram according to a specific embodiment of the low redundancy decoder 22 shown in FIG. 1. Referring to FIG. 3, a row address fuse box (commonly referred to as a "decoding unit") 46 for decoding a row address signal RAi to activate an output node N1, and the output node in response to activation of the precharge signal PRER Redundancy enable signal that generates a low redundancy enable signal RedR_EN when the precharge unit 48 that precharges N1 to a predetermined level, for example, a power supply voltage level, and the output node N1 of the row address fuse box 46 is activated. The generation unit 50 and a row driver 53 for enabling the redundancy word line RMWLi in response to the activation of the redundancy burn-in word line enable signal WBI_ENi or the low redundancy enable signal RedR_EN. The row driver 53 includes a noah gate 52 and an inverter 54.

Now, in the normal operation mode other than the burn-in operation mode, since the burn-in enable signal WBI is in an inactive state, the redundant burn-in wordline enable signal WBI_ENi also has an inactive state, that is, a logic "low" state. Therefore, in the normal operation mode, the redundancy word line RMWLi is selectively generated by the low redundancy enable signal REDR_EN generated in the normal low redundancy decoder section including the row address fuse box 46, the precharge unit 48, and the redundancy enable signal generator 50. Is enabled. The detailed operation of the conventional low redundancy decoder unit is well known to those skilled in the art, and thus the detailed description thereof will be omitted. When operating in the burn-in mode, as described above, the operation of the burn-in counter 12 and the burn-in redundancy decoder 20 activates the redundant burn-in word line enable signal WBI_ENi with a logic " high " Therefore, in the burn-in operation, the NOA gate 52 gates the redundancy burn-in word line enable signal WBI_ENi generated at a predetermined period P in the redundancy decoder 20 to provide the inverter 54 with the corresponding redundancy word line.

Fig. 5 is a circuit diagram of the embodiment of the column redundancy decoder 18 shown in Fig. 1, which includes a column address fuse box (commonly referred to as a "decoding section") 56 which decodes the column address signal CLAi to activate the output node N2. In response to the activation of the precharge signal PREC, the precharge unit 58 for precharging the output node N2 to a predetermined level, for example, a power supply voltage level, and the output node N2 of the column address fuse box 56 are activated. The redundancy enable signal generator 60 generating the column redundancy enable signal RedC_EN, the inverter 61 inverting the burn-in enable signal WBI, and the redundancy in response to the activation of the output of the inverter 61 or the column redundancy enable signal RedC_EN. It consists of a column driver 63 which enables the word line RMWLi. The column driver 63 includes a NAND gate 62 and an inverter 64.

In the configuration shown in FIG. 5, when the burn-in enable signal WBI is in an inactive state in the normal operation mode instead of the burn-in operation mode, a logic “low” is input to one terminal of the NAND gate 62 in the column driver 63. Therefore, in the normal operation mode, the column redundancy word line RYB is generated by the column redundancy enable signal REDC_EN generated in the normal column redundancy decoder section including the column address fuse box 56, the precharge unit 58, and the redundancy enable signal generator 60. Is optionally enabled. Since the detailed operation of the conventional column redundancy decoder unit is well known to those skilled in the art, the detailed description thereof will be omitted. When operated in burn-in mode, the burn-in enable signal WBI is activated with a logic " high " as described above. Accordingly, in the burn-in operation, the enable signal RYB of the column redundancy memory cell is enabled by the outputs of the NAND gate 62 and the inverter 64 which input the burn-in enable signal WBI and the column redundancy enable signal RedC_EN. This causes burn-in for all column redundancy memory cells along with normal memory cells at burn-in.

As described above, according to the present invention, a burn-in test of a normal memory cell and a redundant memory cell is simultaneously performed by using an output of a burn-in counter, thereby screening whether a memory cell is defective at a time and replacing the redundant memory cell by a repair process. The occurrence of defects can be prevented in advance, thereby improving the recycling efficiency.

Claims (5)

A semiconductor memory device having a normal memory cell array having a plurality of main word lines, and a redundancy memory cell array having a plurality of redundancy word lines. A burn-in counter that counts the burn-in clock provided from the outside by activating the burn-in enable signal to generate a burn-in address signal, burn-in address carry signal, and redundancy burn-in signal; Generating a redundancy word line enable signal that decodes the burn-in address carry signal by activation of the generated redundancy burn-in signal and the burn-in enable signal to activate a corresponding redundancy word line among redundancy word lines of a redundancy memory cell array. The burn-in redundancy decoding unit comprises a burn-in control circuit of a redundancy memory cell in a semiconductor memory device. The redundancy of claim 1, further comprising: a normal low word line decoder configured to decode the burn-in address signal to enable a corresponding main word line among main word lines of a normal memory cell array. Burn-in control circuit of memory cell. The burn-in redundancy decoder of claim 1, wherein the burn-in redundancy decoding unit decodes the burn-in address carry signal by activating the redundancy burn-in signal and the burn-in enable signal to generate a redundancy burn-in word line enable signal, and the redundancy burn-in word. And a low redundancy decoder for generating a low redundancy enable signal to enable the redundancy word line when a line enable signal is in an active state. 4. The column redundancy according to any one of claims 1 to 3, wherein the column redundancy has a function of decoding an externally input column address and generates an enable signal of a column redundancy memory cell array in response to activation of the burn-in enable signal. And a decoder, characterized in that the burn-in control circuit of the redundancy memory cell in the semiconductor memory device. A burn-in control method of a redundancy memory cell of a semiconductor memory device having a normal memory cell array having a plurality of main word lines and a redundancy memory cell array having a plurality of redundancy word lines, A burn-in counting step of counting the burn-in clock input by activation of the burn-in enable signal to generate a burn-in address signal, a burn-in address carry signal, and a redundancy burn-in signal of a predetermined period; A redundancy word line enable step of decoding the burn-in address carry signal by activation of the generated redundancy burn-in signal and the burn-in enable signal to activate corresponding redundancy word lines among redundancy word lines of a redundancy memory cell array at a predetermined period. And controlling the burn-in of the redundancy memory cell in the semiconductor memory device.