JP3566349B2 - Semiconductor memory device and test method therefor - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor memory device having a spare memory array for relieving a defective memory cell and a test method therefor.
[0002]
[Prior art]
FIG. 33 schematically shows a structure of a main part of a conventional semiconductor memory device which is a dynamic random access memory, for example. In FIG. 33, the semiconductor memory device includes four memory arrays MA1-MA4 each having a plurality of memory cells arranged in a matrix of rows and columns, and rows provided corresponding to memory arrays MA1-MA4, respectively. Decoder blocks RD1-RD4, spare memory arrays SMA1-SMA4 provided corresponding to memory arrays MA1-MA4, respectively, and column decoder CD provided commonly to memory arrays MA1-MA4 and spare memory arrays SMA1-SMA4.
[0003]
Each of memory arrays MA1-MA4 includes 16 word lines WL (m, 1) -WL (m, 16) to which one row of memory cells are connected. Here, m is any integer of 1-4, and specifies the memory array.
[0004]
Row decoder block RDm selects word line WL (m, n) in corresponding memory array MAm according to a row address signal and an array address signal. Here, n is any one of 1-16. The row address signal designates a row or word line in each of memory arrays MA1-MA4, and the array address signal designates one of the four memory arrays.
[0005]
Each of spare memory arrays SMA1-SMA4 includes four word lines SWL (m, 1) -SWL (m, 4), and relieves up to four defective word lines (defective rows) in corresponding memory arrays MA1-MA4. can do.
[0006]
Each of spare row decoders SRD1 to SRD4 has a defective address designating a defective word line in a corresponding memory array programmed and stored therein. When a defective word line is addressed, the defective word line is designated. The spare row decoder in which the defective address is programmed selects the corresponding spare word line in the corresponding spare memory array.
[0007]
Column decoder CD selects one column in each of memory arrays MA1-MA4 and spare memory arrays SMA1-SMA4 according to a column address signal.
[0008]
In the configuration shown in FIG. 33, repair of a defective word line is performed as follows. Now, when it is determined that the word line WL (1,3) in the memory array MA1 is defective, the word line WL (1,3) is replaced by the spare word line SWL (1,1) in the spare memory array SMA1. Can be Spare memory array SMA1 can only repair the defective word line of defective word line WL (1, n) in memory array MA1, but cannot repair the defective word lines in other memory arrays MA2-MA4.
[0009]
In FIG. 33, as an example, word line WL (1,3) is replaced by spare word line SWL (1,1), and word line WL (1,6) is replaced by spare word line SWL (1,2). The word line WL (1,12) is replaced with a spare word line SWL (1,3), and the word line WL (1,16) is replaced with a spare word line SWL (1,4). It is.
[0010]
FIG. 34 is a diagram showing a schematic configuration of a replacement control circuit used in the semiconductor memory device shown in FIG. In FIG. 34, four program circuits PR1-PR4 are provided for storing a defective word line address signal and determining whether or not the defective word line has been addressed. Each of program circuits PR1-PR4 stores an address of a defective word line replaced with a spare word line arranged at the same position in each of spare memory arrays SMA1-SMA4. That is, the program circuit PR1 stores the addresses of the spare word lines SWL (1,1), SWL (2,1), SWL (3,1), and the defective word line to be replaced with SWL (4,1). The program circuit PR1 uses the spare word lines SWL (1,1), SWL (2,1), SWL (3,1) and SWL (4,1) to store these four defective word line addresses. Includes four link circuits LINK1-LINK4 for storing defective word line addresses to be replaced. Similarly, the program circuit PR4 has four link circuits LINK1 to LINK4, and these link circuits LINK1 to LINK4 are provided with spare word lines SWL (1, 4), SWL (2, 4), SWL (3, 4) and The address of the defective word line which is replaced and replaced by SWL (4, 4) is stored. Although not shown in FIG. 34, a program circuit including four link circuits is also provided for the remaining spare word lines SWL (m, 2) and SWL (m, 3).
[0011]
Decision circuits D1-D4 are provided corresponding to program circuits PR1-PR4, respectively. Each of decision circuits D1-D4 determines whether or not a corresponding spare word line group has been designated in response to an output signal of corresponding program circuit PR1-PR4, and determines control signal SEEx ( x = 1-4) is generated (activated).
[0012]
Spare row decoders SRD (1,1), SRD (2,1), SRD (3,1) and SRD (4,1) receive control signal SEE1 from decision circuit D1, and when control signal SEE1 is in an active state. The state is enabled. Generally, spare row decoder SRD (m, x) receives array support signal BSm and control signal SEEx.
[0013]
Each of row decoders RD (m, n) is provided with a gate Gmn for enabling or disabling corresponding row decoder RD (m, n) according to array instruction signal BSm and control signal SEEx. In FIG. 34, gates G11, G21, G31 provided for row decoders RD (1, 1), RD (2, 1), RD (3, 1) and RD (4, 1) are representatively provided. G41 is shown. These gates G11, G21, G31 and G41 receive control signal SEE1 from decision circuit D1. That is, row decoders RD (m, 1) -RD (m, 16) are divided into groups according to control signals SEE1-SEE4.
[0014]
Gate Gmn supplies array request signal BSDmn to corresponding row decoder RD (m, n) in response to signals BSm and SEEx. The configuration of the gate Gmn will be described later. When the control signal SEEx is active, the gate Gmn disables the corresponding row decoder RD (m, n).
[0015]
FIG. 35 is a diagram specifically showing the configuration of the circuit shown in FIG. In FIG. 35, spare row decoder SRD (m, x), row decoder RD (m, n), program circuit PRx and related circuits are representatively shown.
[0016]
As described above, the program circuit PRx includes the link circuits LINK1 to LINK4 each having the same configuration. Link circuit LINK1 includes a p-channel MOS transistor QP1.1 for precharging node N1 to high voltage VPP in response to precharge signal PR, and fuse elements F1.1-F1.8 connected in parallel to node N1. And n channel MOS transistors QN1.1-QN1.8 connected between fuse elements F1.1-F1.8 and the ground node, respectively. MOS transistors QN1.1-QN1.8 receive internal (predecode) address signals Xi (i = 1-4) and Xj (j = 5-8) at their gates (control electrodes), respectively. At the time of programming a defective word line address, link elements F1.1-F1.8 are cut by irradiation with an energy beam such as a laser beam. Specifically, a fuse element corresponding to a defective word line address among fuse elements F1.1-F1.8 is cut.
[0017]
The decision circuit DX includes a four-input NOR gate NO31 that receives the output signals of the link circuits LINK1 to LINK4, and an inverter INV31 that inverts the output signal of the NOR gate NO31 to generate the control signal SEEx.
[0018]
Spare row decoder SRD (m, x) provided for spare word line SWL (m, x) receives control signal SEEx and array designating signal BSm, and receives spare word line designating signal SWEm. x, which generates (activates) x, and a spare word line drive signal of a high voltage VPP level by inverting an output signal of the NAND gate NA31 to the corresponding spare word line SWL (m, x). The inverter INVSm. x. Here, the circuit shown in FIG. 35 operates using the high voltage VPP as one operation power supply voltage, but may operate using the power supply voltage Vcc as the operation power supply voltage.
[0019]
Gate Gmn provided for row decoder RD (m, n) receives an inverter INV32 for inverting array designation signal BSm, and NOR for generating a decoder enable signal BSDmn in response to the output signal of inverter 32 and control signal SEEx. Includes gate NO32.
[0020]
Row decoder RD (m, n) receives signal BSDmn and internal (pre-decoded) address signals Xi and Xj, and receives a 3-input NAND gate NAm. n and the NAND gate NAm. n of the inverter INVm.n which inverts the output signal of the inverter INVm. n. Next, the operation of the circuit shown in FIG. 35 will be briefly described.
[0021]
In the precharge (standby) state, precharge signal PR is at L level, MOS transistor QP1.1 included in link circuits LINK1-LINK4 is on, and node N1 is at H level of high voltage VPP level. It is charged. Link elements F1.1-F1.8 are programmed in advance according to the test results of the semiconductor memory device (selectively disconnected).
[0022]
The program of link elements F1.1-F1.8 will be described later, but the link element corresponding to the defective row address is disconnected.
[0023]
In the active cycle, precharge signal PR rises to H level, and MOS transistor QP1.1 is turned off. In this state, when the defective word line is addressed, the corresponding fuse element has been cut, so that node N1 maintains the H level of the high voltage VPP level. When a normal word line is designated, its address is not programmed in link circuit LINK1, so that at least one of MOS transistors QN1.1-QN1.8 is turned on, and node N1 is brought to the ground potential level. Discharge. The decision circuit Dx generates the control signal SEEx at the high voltage VPP level when the addressed word line is replaced with any of the spare word lines SWL (m, x). When a defective word line is not specified, control signal SEEx maintains L level.
[0024]
When control signal SEEx and array designating signal BSm both rise to the H level, spare row decoder SRD (m, x) transmits a spare word line drive signal at the high voltage VPP level to corresponding spare word line SWL (m, x). introduce. In other cases, spare row decoder SRD (m, x) transmits an L level signal to corresponding spare word line SWL (m, n).
[0025]
When control signal SEEx is at an H level, signal BSDmn output from NOR gate NO32 included in gate Gmn attains an L level, and row decoder RD (m, n) is disabled. That is, the NAND gates NAm. The output of n is at H level irrespective of the values of address signals Xi and Xj.
[0026]
When the control signal SEEx is at the L level, the NOR gate NO32 is enabled, and the array designation signal BSm is directly generated as the signal BSDmn. When the signals BSm, Xi and Xj specify the word line WL (m, n), the row decoder RD (m, n) outputs the word line drive signal at the high voltage VPP level to the word line WL (m, n). ).
[0027]
FIG. 36 schematically shows an arrangement of row decoders and spare row decoders provided for memory array MA1. In FIG. 36, row decoder block RD1 includes NAND gate NA (1, n) and inverters INV1. . n including unit row decoders RD (1, 1), RD (1, 2),. NAND gates NA (1,1), NA (1,2)... NA (1,16) receive different combinations of address signals Xi and Xj, respectively. The decoder enable signal BSD1n (n = 1-16) is divided into groups according to the control signal SEEx.
[0028]
As spare decoder SRD1, inverter INVS. 1 and INVS 1.4 are representatively shown.
[0029]
FIG. 37 schematically shows a structure of a portion related to one column in one memory cell array. In FIG. 37, one column includes a pair of bit lines BL and / BL, and memory cells MC in a corresponding column are connected. FIG. 37 representatively shows a memory cell MC arranged corresponding to the intersection of bit line BL and word line WL (m, n). The memory cell MC includes a capacitor CS for storing information in the form of electric charge, and a transfer gate QN31 connecting the capacitor CS and the bit line BL in response to a potential on the word line WL (m, n). Capacitor CS receives cell plate voltage VCP of an intermediate potential (Vcc / 2) on one electrode (cell plate electrode).
[0030]
For a pair of bit lines BL and / BL, a sense amplifier SA differentially amplifies the potentials of bit lines BL and / BL, and bit lines BL and / BL in response to a precharge / equalize signal EQ. Precharge / equalize circuit BLEQ for precharging and equalizing to a precharge voltage VBL level of an intermediate potential (Vcc / 2) level. Although not shown, the sense amplifier SA includes a flip-flop type cross-coupled MOS transistor.
[0031]
Precharge / equalize circuit BLEQ includes an n-channel MOS transistor QN32 for electrically connecting bit lines BL and / BL, an n-channel MOS transistor QN33 for transmitting intermediate voltage VBL to bit line BL, and an intermediate voltage Includes n-channel MOS transistor QN34 for transmitting VBL to bit line / BL. MOS transistors QN32-QN34 are turned on when signal EQ attains an H level and indicates a standby state.
[0032]
During operation (in an active cycle), signal EQ is at low level, and MOS transistors QN32-QN34 are all off. Bit lines BL and / BL are electrically floated at intermediate voltage VBL level. When word line WL (m, n) is selected, its potential rises to H level, and transfer gate QN31 is turned on. Thereby, the capacitor CS is coupled to the bit line BL, and the potential of the bit line BL changes according to the data (charge amount) stored in the capacitor CS. Bit line / BL maintains the voltage level of precharged intermediate voltage VBL. Next, sense amplifier SA is activated to differentially amplify the potentials of bit lines BL and / BL, and the potentials of bit lines BL and / BL reach H level and L level according to data stored in memory cell MC. Change.
[0033]
According to an output signal from column decoder (CD), bit line pair BL and / BL are selected, and data is written or read from memory cell MC.
[0034]
When the memory cycle is completed, the potential of word line WL (m, n) falls, and transfer gate QN31 is turned off. Sense amplifier SA is then deactivated, and signal EQ rises to H level. As a result, MOS transistors QN32-QN34 are turned on, and precharge and equalize bit lines BL and / BL to intermediate voltage VBL.
[0035]
The word line WL (m, n) has been boosted to a high voltage VPP higher than the operation power supply voltage VCC, and the voltage of the operation power supply voltage VCC level can be applied to the memory cell capacitor without receiving the loss of the threshold voltage of the transfer gate QN31. CS can be written to, and transfer gate QN31 can be turned on at high speed.
[0036]
[Problems to be solved by the invention]
When replacing a word line using the above-described redundancy method, when the memory cell MC itself is defective, or when the word line WL (m, n) is disconnected, the word WL (m, n) is used. Can be rescued.
[0037]
However, when the word line WL (m, n) and the bit line BL are short-circuited as indicated by a resistor R1 in FIG. 38, a current flows from the bit line BL to the word line WL (m, n) in the standby state. During standby, word line WL (m, n) is discharged to the ground potential level via a word driver (an inverter included in a corresponding row decoder). Therefore, the voltage level of intermediate voltage VBL decreases, and standby current Icc2 increases. When the word line WL (m, n) is short-circuited with the cell plate voltage VCP supply line as indicated by the resistor R2 in FIG. 38, the current consumption similarly increases and the cell plate voltage VCP decreases. When the precharge intermediate voltage VBL supply line is short-circuited with the bit line BL or / BL as shown by the resistor R3a or R3b in FIG. 38, when the sense amplifier SA operates, both operations of the sense amplifier SA are performed. Both the power supply (VCC and ground potential level) are short-circuited to the intermediate voltage VBL supply line, and the potential of the bit line BL or / BL is not sufficiently and correctly amplified during the operation of the sense amplifier SA. A problem arises in that reading cannot be performed and current during the sensing operation increases.
[0038]
In addition, when the sense amplifier SA is short-circuited to the power supply voltage VCC supply line or the ground line, a leak current occurs in the standby state. The problem of the leak current due to the short circuit with the power supply line or the ground line also occurs in the word driver.
[0039]
Even if word line replacement is performed, a defect due to such a short circuit cannot be remedied by a conventional redundancy method based on word line replacement because the short circuit defect continues to exist in the memory array.
[0040]
In order to remedy such a short-circuit defect, a remedy method in which replacement is performed in array units as shown in FIG. 39 is described in "DRAM technology for file use" by Kikawa et al., 1993 IEEE ISSCC, Digest of Technical Paper , Feb. 24, 1993, p. 48, p. 49. In FIG. 39, the semiconductor memory device has a memory array MA1-MA4 having a plurality of memory cells arranged in a matrix of rows and columns, and a memory array MA1-MA4 having the same size as each of the memory arrays MA1-MA4. And the number of columns). Row decoder blocks RD1-RD4 are provided for memory arrays MA1-MA4, respectively, and spare row decoder blocks SRD are provided for spare memory array SMA. Column decoder CD is provided commonly for these arrays MA1-MA4 and SMA.
[0041]
Row decoder blocks RD1-RD4 receive high voltage VPP on internal power supply line 1a via fuse elements F41-F44, respectively, and spare row block decoder SRD receives high voltage VPP via switching element SW3.
[0042]
Memory arrays MA1-MA4 also receive voltage VBL (or VCP) on internal power supply line 1b via fuse elements F31-F34, and spare memory array SMA receives voltage VBL (or VCP) via switching element SW2. .
[0043]
If a defect exists in memory array MA1 irrespective of whether it can or cannot be relieved by replacing the word line, fuse elements F31 and F41 are cut (blown), and switching elements SW2 and SW3 are turned on. Is done. When memory array MA1 is addressed, the array address is programmed such that spare memory array SMA is accessed. Since the voltages VPP, VBL and VCP are not supplied to the memory array MA1, even if there is a short-circuit defect, there is no current flowing through this short-circuit portion, and the current consumption is reduced.
[0044]
In FIG. 3 of the aforementioned document, if the memory capacity is increased, the word line replacement method cannot sufficiently increase the production yield, and in FIG. 5, the memory array increases as the memory capacity increases. Since the number of (blocks) is increased and the size of the array block is reduced, it is stated that the block redundancy scheme by array replacement as shown in FIG. 39 does not increase the chip occupation area so much.
[0045]
However, according to such a block redundancy method, the memory array is replaced with a spare memory array even when there is only a defect that can be remedied by word line replacement. Thus, if a defective word line is distributed across multiple memory arrays due to small sized particles that tend to be distributed across multiple memory arrays, such a defective word line may be Even if the number is smaller than the number of word lines included in the spare memory array, it cannot be repaired.
[0046]
In addition, in such a block redundancy system, since voltages VPP, VBL and VCP are supplied to the memory array only through the fuse element, a standby current test cannot be performed for each array, and therefore, each memory can be used. It is necessary to analyze the distribution pattern of the defective cells in the array to determine whether or not there is a short-circuit failure, and it takes a long time to detect the defective array.
[0047]
Therefore, in order to increase the product yield, it is desirable to assume both replacement in word lines and replacement in array units in a semiconductor memory device.
[0048]
However, when both the conventional word line replacement method and the conventional block redundancy method as described above are mounted on one semiconductor memory device, the chip area increases, the number of fuse elements increases significantly, and replacement control is performed. The circuit configuration becomes complicated and large-scale.
[0049]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device in which both a redundant word line system and a block redundant system can be mounted by a simple replacement control circuit without increasing the chip occupation area.
[0050]
Another object of the present invention is to provide a semiconductor memory device capable of easily detecting a defective memory array.
[0051]
[Means for Solving the Problems]
A semiconductor memory device according to a first aspect includes a plurality of memory arrays and at least one spare array. Each of the memory arrays includes a plurality of memory cells arranged in rows and columns, and a plurality of word lines provided corresponding to each row and connected to the memory cells of the corresponding row. At least one spare array includes a plurality of memory cells arranged in rows and columns, and a plurality of spare word lines arranged corresponding to each row and connected to memory cells of the corresponding row, respectively. The number of spare word lines is the same as the number of word lines included in each of the memory arrays, and if there are no defective word lines, each of the word lines in each of the memory arrays is replaced by the spare word in the spare memory array. It is uniquely associated with a line.
[0052]
The semiconductor memory device according to the first aspect further includes a replacement control circuit that replaces the defective word line with a corresponding spare word line when the defective word line exists in a certain memory array among the plurality of memory arrays.
[0053]
The semiconductor memory device according to claim 2 is Including a plurality of memory arrays and at least one spare array. Each of the memory arrays includes a plurality of memory cells arranged in rows and columns, a plurality of word lines provided corresponding to each row and connected to the memory cells of the corresponding row, and a plurality of memory cells arranged in one row. And at least one redundant word line to which the memory cell is connected. At least one spare array includes a plurality of memory cells arranged in rows and columns, and a plurality of spare word lines arranged corresponding to each row and connected to memory cells of the corresponding row. The number of spare word lines is the same as the number of word lines included in each of the memory arrays, and when there is no defective word line, each of the word lines in each of the memory arrays is replaced with the spare word line of the spare array. Uniquely associated. The device according to claim 2 further comprises: A replacement control circuit for replacing a defective word line with a corresponding spare word line when a defective word line exists in an array of a plurality of memory arrays; There is a defective word line in the memory array memory A redundant replacement circuit that replaces a defective word line with a redundant word line included in the array when present in an array is included.
[0054]
According to a third aspect of the present invention, in the semiconductor memory device, the replacement control circuit of the first aspect is provided corresponding to each of the spare word lines, and decodes a given row address signal to convert a spare word line drive signal into a corresponding spare word. A plurality of spare row decoders for transmitting the data to a corresponding word line in accordance with the result of the decoding, and a plurality of word lines in each of the memory arrays. And a plurality of row decoders for generating the same. Each of the plurality of row decoders and each of the plurality of spare row decoders have the same logical configuration.
[0055]
According to a fourth aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, further comprising an internal voltage line transmitting a predetermined internal voltage, and a defective memory array when a defective memory array exists in a plurality of memory arrays. Voltage supply control means for separating from the voltage lines and connecting the internal voltage lines to the spare memory array.
[0056]
According to a fifth aspect of the present invention, the semiconductor memory device according to the first aspect further includes an internal voltage line for supplying a predetermined internal voltage to each of the plurality of memory arrays; Can be remedied by replacement When it is determined that only a defective word line exists , these of An internal voltage control element for supplying a predetermined internal voltage to the plurality of memory arrays is provided.
[0057]
According to a sixth aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, further comprising: an internal voltage line transmitting a predetermined internal voltage; a unit for generating a standby current test mode instruction signal; Address determining means for generating an array instruction signal in response to a test mode instruction signal and inhibiting generation of a row address signal; and setting an internal voltage line in response to the standby current test mode instruction signal and the array instruction signal. Connection control means for connecting only to the array specified by the signal is provided.
[0058]
According to a seventh aspect of the present invention, in the semiconductor memory device according to the first aspect, a row selecting means for generating a row designating signal in accordance with a row address signal designating a row in each of the plurality of memory arrays; An array selection circuit for generating a signal; and selection control means for enabling the array selection means and disabling the row selection means in response to activation of the standby current test mode instruction signal.
[0059]
According to a eighth aspect of the present invention, there is provided a semiconductor memory device according to the first aspect, further comprising: a means for generating a spare array designating signal defining a spare array; and a standby current test mode designating signal and a spare array designating signal. Means for supplying a predetermined internal voltage to a spare array designated by the spare array and isolating another array from the internal voltage line.
[0060]
According to a ninth aspect of the present invention, in the semiconductor memory device of the first aspect, the semiconductor memory device includes a plurality of memory blocks each including a plurality of memory arrays and the at least one spare array. It is arranged corresponding to each.
[0061]
A test method for a semiconductor memory device according to a tenth aspect includes a plurality of memory arrays each having a plurality of memory cells arranged in rows and columns and the same number of memory cells in rows and columns as the memory arrays. A method of testing a device including at least one spare memory array and an internal voltage transmission line transmitting a predetermined internal voltage, wherein the internal voltage line is connected to a memory array designated by an array designating signal and the remaining array And performing a standby current test of the specified memory array by separating the memory array from the internal voltage line. If the memory array is determined to be defective due to the large standby current in the standby current test, Replacing the spare array with a spare array, and connecting the spare array to an internal voltage line to form a spare array. Performing a standby current for the memory array and, when the standby current test is performed for all the memory arrays, performing a function test for determining whether or not a defective row exists in any of the plurality of memory arrays And, if the defective row can be replaced with a row in the spare array, replacing the defective row.
[0062]
[Action]
In the semiconductor memory device according to the present invention, the word line of the spare array and the word line of each memory array are uniquely associated with each other when no defective word line exists, and the replacement control circuit replaces the defective word line. Word line replacement or array replacement can be easily performed according to the failure mode.
[0063]
In the semiconductor memory device according to the second aspect, each of the memory array and the spare array includes a redundant word line, and the defective word line is replaced by the redundant word line by the redundant replacement circuit. It can be replaced with a spare word line or a redundant word line, and the efficiency of repairing a defective word line is improved. Further, redundant word lines are also provided in the spare array, so that a defective spare word line can be repaired, and accordingly, the repair efficiency of the defective word line or defective array is improved.
[0064]
In the semiconductor memory device according to the third aspect, the row decoder provided corresponding to the word line of the memory array and the spare decoder provided corresponding to the spare word line of the spare array have the same logical configuration. , And an address signal can be applied in common, thereby simplifying the configuration of a replacement control circuit for replacing a word line. Also, there is no access delay due to the repair of the defective word line.
[0065]
In the semiconductor memory device according to the fourth aspect, the supply of the internal voltage to the defective array is prohibited, while the internal voltage is applied to the spare array, and the replacement of the defective array by the spare array is realized.
[0066]
In the semiconductor memory device according to the fifth aspect, when there is only a repairable defective word line, an internal voltage is supplied to each of the memory arrays via the voltage control element, and the defective word line relief is performed in word line units. Is realized.
[0067]
In the semiconductor memory device according to the sixth aspect, in the standby current test mode, the generation of the row address signal is inhibited, while only the array specifying signal is generated, and the internal voltage is applied to the array specified by the array specifying signal. Then, the supply of the internal voltage to the remaining arrays is prohibited, whereby a standby current test can be performed for each array, and the defective array can be easily detected.
[0068]
In the semiconductor memory device according to the seventh aspect, in the standby current test mode, the operation of the row selection circuit is prohibited, and only the array selection circuit operates. As a result, a standby current test can be performed on the array specified by the array specifying signal generated from the array selection circuit.
[0069]
In the semiconductor memory device according to the present invention, a spare array designating signal generating means is provided, and in a standby current test mode, a spare array is designated by the spare array designating signal from the spare array designating signal generating means to spare the internal voltage. Since the power is supplied to the array and the supply of the internal voltage to the other arrays is prohibited, a standby current test for the spare array can also be realized.
[0070]
10. The semiconductor memory device according to claim 9, wherein a replacement control circuit is provided for each of a plurality of memory blocks each including a plurality of memory arrays and at least one spare array. , A defective word line and a defective array can be relieved in each memory block.
[0071]
11. The semiconductor memory device test method according to claim 10, wherein a standby current test is performed for each array, and if a defective array is present, the array is replaced with a spare array. Since a functional test of the device is performed to detect and remedy a defective word line, array replacement can be performed at a high speed, and replacement can be performed in word line units when no defective array exists.
[0072]
【Example】
FIG. 1 is a diagram schematically showing a configuration of a main part of a semiconductor memory device which is an embodiment of the present invention, for example, a dynamic random access memory. 1, the semiconductor memory device includes a plurality of memory arrays MA1-MAw (w = 4 in the configuration of FIG. 1). Each of memory arrays MA1-MAw includes a plurality of memory cells arranged in rows and columns. The semiconductor memory device further includes a spare memory array SMA having a plurality of memory cells arranged in rows and columns for repairing a defective memory array by replacement. Each of memory arrays MA1-MAw includes X (16 in the arrangement of FIG. 1) word lines WL (m, n). Here, m is 1-w and n is 1-X. Word line WL (m, n) is arranged corresponding to each row of corresponding memory array MAm, and the memory cells on the corresponding row are connected. In the following description, it is assumed that the semiconductor memory device includes four memory arrays MA1-MA4, and each of the memory arrays MA1-MA4 includes 16 word lines, for the sake of simplicity.
[0073]
Spare memory array SMA includes the same number of spare word lines SWL (s, X) as memory arrays MA1-MA4, and each of spare word lines SWL (s, X) has a corresponding row in spare memory array SMA. A memory cell is connected. Here, based on the above assumption, spare memory array SMA also includes 16 spare word lines SWL (s, 1) -SWL (s, 16). Row decoder block RDBm is provided for each of arrays MA1-MA4. Row decoder block RDBm includes 16 row decoders RD (m, n) provided corresponding to word lines WL (m, n) included in corresponding memory array MAm. Similarly, for spare memory array SMA, 16 spare row decoders SRD (s, n) provided corresponding to spare word lines SWL (s, 1) -SWL ((s, 16)) are provided. .
[0074]
Column decoder CD is provided commonly to memory arrays MA1-MA4 and spare memory array SMA. Column select line CSL transmitting a column select signal from column decoder CD extends over memory arrays MA1-MA4 and spare memory array SMA. The column selection line CSL may select one column (a pair of bit lines) in each of the memory arrays MA1-MA4 and the spare memory array SMA, or select a plurality of columns in each of the arrays MA1-MA4 and SMA. May be configured.
[0075]
The internal voltage VI on the internal voltage line 1 is supplied to each of the memory arrays MA1-MA4 via fuse elements (fusible link elements) F1-F4. Internal voltage VI includes high voltage VPP for driving word lines, intermediate voltage VBL for precharging / equalizing bit lines, and cell plate voltage VCP applied to memory cell capacitors. In FIG. 1, these predetermined reference voltages VPP, VBL, and VCP are generically indicated by internal voltage VI. Spare memory array SMA is supplied with internal voltage VI via switching element SW1. Spare row decoder block SRDB receives high voltage VPP represented by internal voltage VI via switching element SW1.
[0076]
High voltage VPP, bit line precharge / equalizing intermediate voltage VBL, and cell plate voltage VCP are supplied to arrays MA1-MA4 and SMA via different fuse elements or switching elements, respectively. However, in FIG. 1, in order to simplify the drawing, one fuse element Fm is provided for each memory array MAm, and one switching element SW1 is provided for spare memory array SMA. Shown.
[0077]
When spare memory array SMA is used (when a defective word line or a defective array exists), switching element SW1 is turned on. If the memory array MAm is defective due to a large leak current, the corresponding fuse element Fm is blown, and the supply of the internal voltage VI to the defective array MAm is prohibited. Next, a rescue method in the configuration shown in FIG. 1 will be briefly described.
[0078]
Replacement (repair) in word line units is performed as follows. If the k-th word line WL (m, k) in the memory array MAm is defective and should be relieved, the spare word line SWL (s, k) in the spare memory array SMA and the k-th word line WL ( m, k) are replaced. For example, word line WL (1,2) of memory array MA1 is replaced with spare word line SWL (s, 2) of spare memory array SMA, and word line WL (2,6) of memory array MA2 is replaced by spare memory. The spare word line SWL (s, 6) of the array SMA is replaced, and the word line WL (3, 12) of the memory array MA3 is replaced by the spare word line SWL (s, 12), and the word line WL of the memory array MA4 is replaced. (4, 16) is replaced with a spare word line SWL (s, 16).
[0079]
When a defective word line exists in a plurality of memory arrays and their numbers, that is, the row addresses are different, all of these defective word lines can be replaced by the spare word line of spare memory array SMA. The line can be rescued.
[0080]
When such a replacement method is applied to a specific memory array MAm, the specific memory array MAm is entirely replaced with a spare memory array SMA. That is, with the replacement configuration shown in FIG. 1, both replacement in word lines and replacement in array units can be performed. When replacement is performed in word line units, switching element SW1 is turned on, and fuse elements F1-F4 are all turned on. When replacement is performed in array units, switching element SW1 is turned on, and fuse element Fu corresponding to defective memory array MAu is blown. Thereby, supply of internal voltage VI to defective memory array MAu is prohibited, and current consumption in defective memory array MAu is prevented.
[0081]
FIG. 2 is a diagram showing a configuration for generating an enable signal for enabling spare row decoders SRD (s, 1) to SRD (s, 16) shown in FIG. The configuration shown in FIG. 2 is provided for each of spare row decoders SRD (s, 1) to SRD (s, 16). In FIG. 2, a spare row decoder enable signal generation circuit includes a first program circuit 10 for programming whether a corresponding spare word line SWL (s, n) is used, and a corresponding spare word line SWL. A second program circuit 12 for programming which memory array uses (s, n) is included. First program circuit 10 includes a resistance element Rn connected between a node receiving high voltage VPP and node Nn, and a fuse element Fn. Connected between node Nn and a ground potential node. 5 is included.
[0082]
When the corresponding spare word line SWL (s, n) is used, that is, when word line WL (m, n) in any of memory arrays MA1-MA4 is defective, fuse element Fn. 5 is blown, for example, by a laser beam. The resistance element Rn pulls up the node Nn to the high voltage VPP level, the signal SEn rises to the H level, indicating that the corresponding spare word line SWL (s, n) is used.
[0083]
If the corresponding spare word line SWL (s, n) is not used, fuse element Fn. 5 maintains the conduction state. Resistance element Rn has a large resistance value, so that node Nn is discharged to the ground potential level, signal SEn attains L level, indicating that the corresponding spare word line SWL (s, n) is not used.
[0084]
Second program circuit 12 includes NAND gates NAn.NAn. Provided corresponding to memory array designating signals BS1'-BS4 'provided from a block (array) decoder described later. 1-NAn. 4 and NAND gate NAn. 1-NAn. 4 are connected to the fuse elements Fn. 1-Fn. 4 and an inverter INVn.
[0085]
NAND gate NAn. 1-NAn. 4 receives signal SEn from first program circuit 10 at one input, and receives corresponding array designation signals BS1'-BS4 'at the other input. NAND gate NAn. 1-NAn. 4 is output from the corresponding fuse element Fn. 1-Fn. 4 to a signal line 5.
[0086]
Inverter INVn inverts the signal on signal line 5 to generate spare row decoder enable signal BSEn for controlling enable / disable of spare row decoder SRD (s, n). In the programming of the memory array in the second program circuit 12, the NAND gate NAn. That receives the memory array designating signal BSm 'designating the memory array MAm using the corresponding spare word line SWL (s, n). Only the fuse element provided at the output of m is rendered conductive, and the remaining fuse elements are cut.
[0087]
For example, when memory array MA1 uses spare word line SWL (s, n), fuse element Fn. 2-Fn. 4 is cut, and fuse element Fn. 1 is made conductive. NAND gate NAn. Only one output signal is transmitted to signal line 5. At this time, since the corresponding spare word line SWL (s, n) is used for signal SEn, fuse element Fn. 5 is disconnected and becomes H level.
[0088]
When memory array MA1 is addressed, that is, when access is requested, signal BS1 'attains H level and NAND gate NAn. 1 goes low, the signal BSEn from the inverter INVn goes high, and the corresponding spare row decoder SRD (s, n) is enabled.
[0089]
When another memory array is addressed, signal BS1 'is at L level and NAND gate NAn. 1 is at the H level, and the signal BSEn is also at the L level. When the corresponding spare word line SWL (s, n) is not used by any of memory arrays MA1-MA4, fuse element Fn. 1-F1n. All 4 are made conductive. In this state, as described above, signal SEn is also at L level (fuse element Fn.5 is conductive), and NAND gate NAn. 1-NAn. 4 are all disabled and always output a signal of H level regardless of the logic level of the memory array designation signals BS1'-BS4 '. Therefore, the signal on signal line 5 is at H level, and signal BSEn maintains L level. Thereby, the corresponding spare word line SWL (s, n) is maintained in the non-selected state.
[0090]
By using the configurations of program circuits 10 and 12 shown in FIG. 2, row decoder RD (m, n) and spare row decoder SRD (s, n) have the same logical configuration as described later. As a result, the control of enabling / disabling the row decoder RD (m, n) and the spare row decoder SRD (s, n) is simplified.
[0091]
Further, fuse elements Fn. Used for word line replacement (or array replacement) are used. 1-Fn. 5, the fuse element Fn. 1-Fn. The total number is 80 except for 4 and the number of fuse elements is greatly reduced as compared with the conventional word line replacement method. Here, when the number of fuse elements includes the fuse elements F1 to F4, and the fuse elements are provided for each of the high voltage VPP and the intermediate voltage VBL as the internal voltage, the total is 88.
[0092]
According to the above configuration, defective word line WL (m, n) in memory array MAm is intentionally replaced by spare word line SWL (s, n) having the same number (same row address) as spare memory array SMA. Therefore, there is no need to program or store which defective word line WL (m, n) is replaced with which spare word line SWL (s, n).
[0093]
Here, the reason why the high voltage VPP is used to generate the signal SEn is as follows. Each of array designating signals BS1'-BS4 'attains a high voltage VPP level when activated, as will be described later. Inverter INVn and NAND gate NAn. 1-NAn. 4 operates using the high voltage VPP as one operation power supply voltage. Therefore, high voltage VPP is used in program circuit 10 to match the voltage levels of signals BS1'-BS4 'with the voltage level of signal SEn. However, signals BS1'-BS4 'are at the level of operating power supply voltage VCC, and NAND gates NAn. 1-NAn. 4 and the inverter INVn operate using the operating power supply voltage VCC as the operating power supply voltage, the operating power supply voltage VCC may be used in the first program circuit 10 instead of the high voltage VPP.
[0094]
FIG. 3 is a diagram showing a configuration for generating a normal decoder enable signal BSn (m, n) for controlling enable / disable of the normal row decoder RD (m, n). In FIG. 3, address buffer 3 receives an externally applied address signal, receives an array address signal BA for addressing one of memory arrays MA1-MA4, and a word line WL (m, 1) -WL ( m, 16n) is generated. Row address signal RA is applied to normal row decoder RD (m, n) and spare row decoder SRD (s, n) via a row predecoder (this configuration will be described later).
[0095]
Block decoder 3 receives and decodes array address signal BA from address buffer 2 to generate array designation signal BSm '. Although the block decoder 3 operates using the high voltage VPP as one operation power supply voltage, the block decoder 3 may operate according to the operation power supply voltage VCC.
[0096]
Array designating signal BSm 'from block decoder 3 is applied to inverter IVm, and the output signal of inverter IVm is applied to one input of NOR gate NOn (m). Normal decoder enable signal DSEn is applied to the other input of NOR gate NOn (m). Normal decoder request signal DSn (m) is output from NOR gate NOn (m). The NOR gates NOn (m) are provided corresponding to the respective normal row decoders RD (m, n) as shown in FIG. FIG. 4 shows, as an example, a state where NOR gates NOn (1) -NOn (4) are provided corresponding to row decoders RD (1, n) -RD (4, n), respectively. NOR gates NOn (1) -NOn (4) receive inverted array designating signals / BS1 '-/ BS4' at their first inputs and normal row decoder enable signal DSEn at their second inputs. Next, the operation of the configuration shown in FIGS. 3 and 4 will be described.
[0097]
When spare word line SWL (s, n) is not used, signal BSEn is at L level. Thereby, spare row decoder SRD (s, n) is disabled. NOR gate NOn (m) inverts inverted array designating signal / BSm 'and outputs signal BSn (m). One of the row decoders RD (1, n) -RD (4, n) is enabled according to the normal decoder request signal BSn (m).
[0098]
When spare word line SWL (s, n) is used, signal BSEn rises to H level only when a memory array using spare word line SWL (s, n) is designated. It is now assumed that memory array MA1 uses spare word line SWL (s, n). That is, consider a case where word line WL (1, n) is defective and replaced with spare word line SWL (s, n).
[0099]
When array designating signal BS1 'rises to the H level and designates memory array MA1, signal BSEn rises to the H level, disabling NOR gate NOn (m), and outputs signals BSn (m) and BSn (1). -BSn (4)) maintains the L level, and the row decoders RD (1, n) -RD (4, n) are disabled. When a word line WL (1, a) other than the defective word line WL (1, n) is designated, the row decoder RD (1, a) is enabled by the corresponding decoder enable signal BSa (1), and the signal BSa ( When 1) is at the H level, the word line WL (1, a) is selected.
[0100]
When a memory array other than memory array MA1 is designated, signal BSEn attains an L level, and NOR gates NOn (m) (NOn (1) -NOn (4)) are enabled. One of signals / BS2 '-/ BS4' attains an L level, an output signal BSn (m) from a corresponding NOR gate NOn (m) (m） 1) rises to an H level, and a corresponding row decoder RD ( m, n) are enabled.
[0101]
FIG. 5 is a diagram showing a configuration of a row decoder RD (m, n) provided for a normal word line WL (m, n). In FIG. 5, row decoder RD (m, n) has a three-input NAND gate NAm. n and the inverter INVm. n.
[0102]
NAND gate NAm. n receives decoder enable signal BSn (m), one bit of predecode signal Xi (i = 1-4), and one bit of predecode signal Xj (j = 1-4), and receives given signal BSn (m). ), And outputs an L level signal when Xi and Xj are all at H level. Predecode signals Xi and Xj are generated by predecoding an external row address signal by a row predecoder (not shown).
[0103]
The inverter INVm. n has its source connected to receive the high voltage VPP, and has its gate connected to the NAND gate NAm. n, the drain of which is connected to the corresponding word line WL (m, n), the source of which receives the ground potential VSS, and the gate of which receives the NAND gate NAm. An n-channel MOS transistor QN receiving the output signal of n and having its drain connected to the corresponding word line WL (m, n) is included.
[0104]
NAND gate NAm. n outputs an H level signal of the high voltage VPP level when not selected. NAND gate NAm. n may operate with the high voltage VPP as the operating power supply voltage when each of the signals Xi, Xj and BSn (m) is a signal at the high voltage VPP level. Alternatively, NAND gate NAm. n is a level conversion for converting an H level signal of the operation power supply voltage level into a signal of a high voltage VPP level when the signals BSn (m), Xa and Xi are selected and the signal is at the operation power supply voltage level. It may have a function.
[0105]
FIG. 6 is a diagram specifically showing a configuration of spare row decoder SRD (s, n). 6, spare row decoder SRD (s, n) has the same configuration as row decoder RD (m, n) shown in FIG. 5, and has one bit of signal BSEn signal, predecode signal Xi and predecode signal Xj. NAND gate NAm. n and the NAND gates NAs. n receiving the output signal of the inverter INVs. n.
[0106]
The inverter INVs. n includes a p-channel MOS transistor QPs and an n-channel MOS transistor QNs. The inverter INVs. n operates with the high voltage VPP as one operation power supply voltage. NAND gate NAs. n outputs a signal of L level when applied signals BSEn, Xi and Xj are all at H level, and inverters INVs. The output signal from n becomes high voltage VPP level, and spread word line SWL (s, n) is set to the selected state.
[0107]
As can be clearly seen from FIGS. 5 and 6, row decoder RD (m, n) and spare row decoder SRD (s, n) have the same logical configuration as each other. With the same logical configuration, no access delay occurs even when a spare word line is selected, and the same layout pattern is repeated for row decoder RD (m, n) and spare row decoder SRD (s, n). The layout area can be reduced, and the layout can be facilitated.
[0108]
FIG. 7 is a diagram exemplarily showing the flow of signals related to word line selection. Memory array designation signals BS1'-BS4 'are applied to second program circuit 12. First program circuit 10 generates a signal SEn indicating whether or not a corresponding spare word line SWL (s, n) is to be used, and supplies it to second program circuit 12. Second program circuit 12 generates spare decoder enable signal BSEn according to signals BS1'-BS4 'and BSEn. Gate 15 corresponds to inverter IVm and NOR gate NOn (m) shown in FIG. 3, receives a corresponding memory array designating signal BSm 'and a decoder enable signal BSEn, and supplies a corresponding row decoder RD (m, n) to corresponding row decoder RD (m, n). The signal BSn (m) is provided.
[0109]
Predecode signals Xi and Xj are commonly applied to row decoder RD (m, n) and spare row decoder SRD (s, n). That is, row decoder RD (m, n) and spare row decoder SRD (s, n) provided on the word line of the same row address receive the same combination of predecode signals Xi and Xj, and receive signal BSn (m) And BSEn enable one of them.
[0110]
FIG. 8 is a diagram showing the overall arrangement of the row decoder and the spare row decoder. In FIG. 8, row decoders RD (1,1) -RD (1,16) provided for word lines WL (1,1) -WL (1,16) of memory array MA1 and memory cell array MA4, respectively. Row decoders RD (4,1) -RD (4,16) provided for word lines WL (4,1) -WL (4,16), and spare word lines SWL (s, 1) of spare memory array SMA. ) -SWL (s, 16) are representatively shown as spare row decoders SRD (s, 1) to SRD (s, 16).
[0111]
The first-stage three-input NAND gates NA (1,1) -NA (1,16) of the row decoders RD (1,1) to RD (1,16) have their first inputs on the 16-bit bus 20a. Signals BS1 (1) -BS16 (1) are received, respectively. The first-stage NAND gates NA (4,1) -NA (4,16) of the row decoders RD (4,1) -RD (4,16) provide signals on the 16-bit signal bus 20d to their first inputs. Receive BS4 (1) -BS4 (16). The first-stage three-input NAND gates NA (s, 1) -NA (s, 16) of the spare row decoders SRD (s, 1) -SRD (s, 16) each have a 16-bit signal bus 20e connected to its first input. It receives the above signals BSE1-BSE16, respectively.
[0112]
The spare word line SWL (s, n) can be replaced with only one word line WL (1, n) -WL (4, n), that is, WL (m, n).
[0113]
When signal BSEn is activated, signal BSn (m) is deactivated. Thereby, when the spare word line SWL (s, n) is selected, the selection of the corresponding word line WL (m, n) is prohibited.
[0114]
FIG. 9 is a diagram showing a configuration for programming the switching element SW1. In the configuration shown in FIG. 9, switching element SW1 is connected between p-channel MOS transistor PTa connected between high voltage supply line 1a and local high voltage line 21a, and between intermediate voltage VBL supply line 1b and local voltage line 21b. It includes a p-channel MOS transistor PTb connected thereto and a p-channel MOS transistor PTc connected between another intermediate voltage VCP supply line 1c and local voltage line 21c. Local lines 21a, 21b and 21c transmit high voltage VPP, intermediate voltage (bit line precharge / equalize voltage) VBL and another intermediate voltage (cell plate voltage) VCP to spare memory array SMA, respectively.
[0115]
Program circuit 22 for programming switching element SW1 includes a fuse element Fw connected between high voltage supply line 1a and node 22a, and a high resistance resistance element Rw connected between node 22a and a ground node. . Node 22a is connected to the gates of MOS transistors PTa, PTb and PTc.
[0116]
When spare memory array SMA is not used, fuse element Fw maintains the conductive state, node 22a is set to the high voltage VPP level, and MOS transistors PTa, PTb and PTc are all turned off. Thus, the supply of the voltages VPP, VBL and VCP to the spare memory array is prohibited.
[0117]
When spare memory array SMA is used, fuse element Fw is blown, node 22a is discharged to the ground potential level by pull-down resistor Rw, MOS transistors PTa-PTc are all turned on, and voltage is applied to spare memory array SMA. VCP, VBL and VPP are supplied. Thereby, spare memory array SMA is brought into an operable state.
[0118]
FIG. 10 is a diagram showing each configuration of the switching element SW1. In the configuration shown in FIG. 10, switching elements SW1a and SW1b are provided for sense amplifier SA. Sense amplifier SA is provided for bit lines BL and / BL, and has an N sense amplifier NSA formed of cross-coupled n-channel MOS transistors and a P sense amplifier formed of cross-coupled p-channel MOS transistors. Includes PSA. N sense amplifier NSA receives ground potential Vss applied on local switch line 21e via n channel MOS transistor NSD which is turned on in response to N sense amplifier activation signal φSN. P sense amplifier PSA receives power supply voltage Vcc applied on local power supply line 21d via p channel MOS transistor PSD which is turned on in response to φSP.
[0119]
Switching element SW1a formed of n-channel MOS transistor NTd is provided for local ground line 21e, and switching element SW1b formed of p-channel MOS transistor PTd is provided for local power supply line 21d. When conducting, switching elements SW1a and SW1b transmit ground potential Vss on ground line 1d and operating power supply voltage Vcc on power supply line 1d to local ground line 21e and local power supply line 21d, respectively. The on / off program of switching elements SW1a and SW1b is realized by a configuration shown in FIG. 9 in which a signal at node 22a is received by an inverter. A configuration in which a switching element is further provided for sense amplifier activation signals φSP and φSN may be used.
[0120]
FIG. 11 is a diagram showing another configuration of a circuit related to word line selection. In the configuration shown in FIG. 11, a two-way system is applied to row decoder RD (m, n) and spare row decoder SRD (s, n).
[0121]
Row decoder RD (m, n) receives NAND signal NAn. n. One bit of the predecode signal Xi (i = 1-4) and one bit of the predecode signal Xk (k = 5-6) are also the NAND gate NAm. n. NAND gate NAm. n simultaneously designates adjacent word lines WL1 (m, n) and WL2 (m, n).
[0122]
NAND gate NAm. A 2-way decoder is provided at the output of n to select one of two adjacent word lines WL1 (m, n) and WL2 (m, n). This 2-way decoder is provided for word line WL1 (m, n), and is provided for n-channel MOS transistor QNmn1 which is turned on in response to way signal RX1, and for word line WL2 (m, n). And an n-channel MOS transistor QNmn2 which is turned on in response to another way signal RX2. Way signals RX1 and RX2 generated from the 1-bit address signal are alternatively activated. Way signal RX1 specifies a group of word lines WL1 (m, n), and way signal RX2 specifies a group of word lines WL2 (m, n). According to way signals RX1 and RX2, one of MOS transistors Qmn1 and Qmn2 is turned on, and corresponding NAND gate NAm. n output signals.
[0123]
Word drivers WDmn1 and WDmn2 are provided between the way decoder (transistors Qmn1 and Qmn2) and word lines WL1 (m, n) and WL2 (m, n). Word drivers WDmn1 and WDmn2 all have the same configuration, and FIG. 11 representatively shows only the configuration of word driver WD111. Word driver WD111 inverts and amplifies a signal applied from NAND gate NA1.1 via MOS transistor QN1.1.1 to amplify and apply the resulting signal to word line WL1 (1,1), and inverter INV1. .. p-channel MOS transistor QP1.1.2 for transmitting high voltage VPP to the input portion of inverter INV1.1.1 in response to an output signal of inverter INV1.1.1, and inverter INV1.1 in response to reset signal RST. .1 includes a p-channel MOS transistor QP1.1.1 for precharging the input portion to the high voltage VPP level. In the configuration shown in FIG. 11, signals BSEn, BSn (m), Xi, Xk, RX1 and RX2 are signals at the operating power supply voltage VCC level, and NAND gates NAm. n operates as the operation power supply voltage of the operation power supply voltage VCC. On the other hand, the inverter INVm. n. 1 and INVm. n. 2 operates using the high voltage VPP as the operating power supply voltage.
[0124]
For spare word lines SWL1 (s, n) and SWL2 (s, n), NAND gates NAs. There are provided a spare row decoder SRD (s, n) composed of n, a way decoder composed of n-channel MOS transistors QNsn1 and QNsn2, and word drivers WDSn1 and WDSn2. MOS transistors QNSn1 and QNSn2 receive way signals RX1 and RX2 at their respective gates. As is apparent from the configuration shown in FIG. 11, word line WL1 (m, n) or WL2 (m, n) is provided for spare word line SWL1 (s, n) or SWL2 (s, n). It has the same configuration as the spare word line selection circuit. Next, the operation will be briefly described.
[0125]
During the standby operation, the reset signal RST is at the L level, and the inverter INVm. n. 1 and INVm. n. 2 inputs are precharged to the high voltage VPP level. Signals RX1 and RX2 are both at L level, and MOS transistors QNmn1, QNmn2, QNSn1 and QNSn2 are all turned off. When the memory cycle starts, signal RST rises to the H level, and MOS transistor QPM. N. 1.1 is turned off. However, MOS transistor QPm. n. 1.2 (QPm.n.2.2) is turned on, and the inverter INVm. n. 1 (INVmn.2) is maintained at the high voltage VPP level.
[0126]
According to the address signal, NAND gate NAm. n. 1, NAm. n. 2, NAs. n. 1 and NAs. n. 2 outputs an L-level signal indicating the selected state. 2-way decoder selects one of word lines WL1 (m, n) and WL2 (m, n) or one of spare word lines SWL1 (s, n) and SWL2 (s, n) according to way decode signals RX1 and RX2. I do. When NAND gate NA1.1 outputs a signal at L level and signal RX1 is at H level, the input of inverter INV1.1.1 is discharged to ground potential level by NAND gate NA1.1, and inverters INV1.1. 1 transmits a signal at the high voltage VPP level to the word line WL (1, 1). At this time, MOS transistor QP1.1.2 is turned off accordingly.
[0127]
When NAND gate NA (1,1) outputs an H level signal of operating power supply voltage VCC level and signal RX1 is at the same H level, MOS transistor QN1.1.1 has its source and gate at the same voltage level. , And is turned on. Therefore, in this state, high voltage VPP is not transmitted to NAND gate NA (1,1).
[0128]
When spare row decoder SRD (s, n) is selected, the same operation as when the above-described row decoder is selected is performed.
[0129]
The following advantages can be obtained by using the way decoding method as shown in FIG. NAND gate NAm. n or NAs. n is provided for two word lines WL1 (m, n) and WL2 (m, n) or two spare word lines SWL1 (s, n) and SWL2 (s, n), and the NAND gate NAm. n and NAs. The pitch condition of n is relaxed.
[0130]
Even if the number of word lines included in one memory array increases to, for example, 32, the size of the NAND gate does not change. That is, the 3-input NAND gate can be used as it is as a row decoder for such a memory array having 32 word lines. This can suppress an increase in the area occupied by the row decoder.
[0131]
FIG. 12 is a diagram showing a flow of a test process of the semiconductor memory device according to the present invention. A method for detecting a defective array or a defective word line and relieving it will be described with reference to the flowchart shown in FIG.
[0132]
In step S1, an Icc2 test is performed on each of memory arrays MA1-MA4 in array units. In this Icc2, it is checked whether the standby current Icc2 consumed by the semiconductor memory device in the standby mode exceeds a predetermined value. This standby current Icc2 is a current consumed in one memory array.
[0133]
If it is determined that the memory array MAn is defective, the defective memory array MAm is replaced with the spare memory array SMA (Step S2). Next, the fuse element Fm provided for the memory array MAm is blown, the switching element SW1 is turned on, and the replacement of the internal voltage source is performed (step S3). Next, an Icc2 test is performed on spare memory array SMA (step S4). In this case, a configuration may be used in which a defective array address is replaced with a memory array power supply at the time of replacement with a spare memory array, or a configuration in which a spare array address is externally applied may be used. If the memory device is determined to be defective by the Icc2 test in step S4, the memory device is determined to be defective (chip failure) and is treated as a defective product.
[0134]
When the Icc2 test for the spare memory array indicates a good state, the Icc2 test for another memory array is executed (steps S1 and S5). If another memory array is determined to be defective again, the spare memory array is already in use and this new defective memory array cannot be remedied, so this storage device is determined to be defective. Is done.
[0135]
After step S5, a functional test such as a test for checking whether or not the memory cell stores data normally is performed on the individual word lines of the memory array and the spare array excluding the defective memory array. (Step S6).
[0136]
When a defective word line is found, it is first determined whether this defective word line can be replaced with a spare word line. If the corresponding spare word line has already been used, this storage device is determined to be defective. Here, even if the memory array replacement is performed in step S2, the function test is performed on the memory array that has not been replaced. This functional test is also performed on the spare array.
[0137]
If the defective word line can be replaced with a spare word line, a link blow to the program circuit shown in FIG. 2 is performed (step S7).
[0138]
This link blow (cutting of the fuse element) is executed for all the defective word lines, and after all the defective word line addresses are programmed, the defective word line is normally replaced with the corresponding spare word line. Then, a post test is performed to identify whether the operation is normal or not (step S8).
[0139]
If it is determined in steps S6 and S8 that all the storage devices are non-defective, the semiconductor storage device is determined to be non-defective (pass chip). If the storage device is determined to be defective in the test of step S6 or S8, it is disposed of as a chip failure.
[0140]
As described above, the semiconductor memory device can perform both replacement in array units and replacement in word line units, which greatly increases the product yield.
[0141]
Here, in the Icc2 test, the current flowing through the power supply pin is only monitored externally, and the time required for the Icc2 test is negligible compared to the time required for the functional test. Therefore, the total time required for the redundancy test is almost the same as the time required for the conventional redundancy method in which only word line replacement is performed.
[0142]
FIG. 13 is a diagram showing a configuration for executing the Icc2 test in array units. 13, row decode circuits (row decoder blocks) RD1-RD4 receive high voltage VPP on internal high voltage line 1a via fuse elements F1P-F4P and switching elements T1P-T4P, respectively. Although switching elements T1P-T4P are shown formed by n-channel MOS transistors, these switching elements T1P-T4P may be formed by p-channel MOS transistors. Switching elements T1P-T4P are selectively turned on in response to control signals VPBS1-VPBS4, respectively.
[0143]
Spare row decoder circuit (spare row decoder block) SRD receives internal high voltage VPP on high voltage line 1a via switching elements SW1P and SW2P. The on / off state of the switching element SW1P is programmed as shown in FIG. Switching element SW2P is selectively turned on in response to control signal VPSBS. Memory arrays MA1-MA4 receive intermediate voltage VBL on internal voltage line 1b via switching elements T1b-T4b and fuse elements F1b-F4b, respectively. Fuse elements F1b-F4b correspond to fuse elements F1-F4 shown in FIG. Switching elements SW1b-SW4b are selectively turned on in response to control signals VBBS1-VBBS4.
[0144]
Spare memory array SMA receives intermediate voltage VBL via switching elements SW1b and SW2b. The switching element SW1b corresponds to the switching element SW1 shown in FIG. 1 or the switching element PTb shown in FIG. 9, and its ON state is programmed. Switching element SW2b is turned on in response to control signal VBSBS when spare memory array SMA is used. Switching elements T1b-T4b, SW1b and SW2b may be formed by p-channel MOS transistors. Although not explicitly shown in FIG. 13, a configuration for cell plate voltage VCP is provided similarly. Next, the operation will be briefly described.
[0145]
Control signals VPBS1 to VPBS4, VPSBS, VBBS1 to VBBS4 and VBBSBS are set to an active state of an H level in an operation mode other than the Icc2 test mode, as will be described later in detail. The on state of switching elements SW1p and SW1b is programmed when a spare memory array is used.
[0146]
In the Icc2 test, control signal VPBSm or VPSBS, VBBSm or VBSBS is selectively activated according to the array subjected to the Icc2 test. For example, when the Icc2 test is performed on memory array MA2, only control signals VPBS2 and VBBS2 (and VCBS2) are activated, and the remaining control signals are deactivated. Externally, a current flowing through a power supply pin (not shown) is monitored.
[0147]
FIG. 14 is a block diagram schematically showing an entire configuration of a semiconductor memory device according to the present invention. 14, the storage device includes a memory array unit 100 including memory arrays MA1-MA4, a row decode circuit 104 including a row decoder RD (m, n) (and a word driver (WD)), and a spare row decoder SRD ( s, n). These components have configurations similar to those described above.
[0148]
The storage device further includes a sense amplifier circuit 110 including a sense amplifier provided for each column (each bit line pair) of memory array unit 100 and spare array unit 102, and a column for selecting the columns of array units 100 and 102. A decoder (CD) 112 is included.
[0149]
A voltage control circuit 108 for supplying internal power supply voltages VPP, VBL and VCP to the array units 100 and 102 and the decoder circuits 104 and 106 in array units is provided. This voltage control circuit 108 corresponds to the fuse element and the switching element shown in FIG.
[0150]
The semiconductor memory device further responds to an Icc test detector 120 for detecting that the Icc2 test has been designated, and to an external row address strobe signal ext / RSA and an Icc test detection signal / ICCTEST from Icc test detector 120. RAS buffer 122 for generating internal row address strobe signals int / RAS and int / RAST.
[0151]
Signal int / RAST changes according to external row address strobe signal ext / RAS even in the Icc2 test mode operation. On the other hand, signal int / RAS is set to the inactive H level in the Icc2 test mode operation regardless of the state of external row address strobe signal ext / RAS.
[0152]
The semiconductor memory device further includes a row address buffer 124 for receiving an external address signal exAb designating a memory array in response to signal int / RAST and generating an internal array address signal, and an internal array address in response to signal int / RAST. A row predecoder 125 which predecodes a signal to generate an array request (designation) signal BSm ', and an address which takes in an external address signal exAw specifying a word line in response to signal int / RAST and generates an internal row address signal Buffer 126 and a row predecoder 127 for predecoding the internal row address signal in response to signal int / RAST to generate row predecode signals Xi and Xj. Row predecode signals Xi and Xj are applied to row decoder circuit 104 and spare decoder circuit 106.
[0153]
The semiconductor memory device further includes a CAS buffer 130 for generating internal column address strobe signal int / CAS in response to external column address strobe signal ext / CAS, and an external column address in response to signals int / RAS and int / CAS. A column column address buffer 132 that takes in signal exAi and generates an internal column address signal, and a column predecoder 134 that predecodes the internal column address signal, generates a column predecode signal, and applies it to column decoder 122.
[0154]
Word line / sense amplifier control circuit 128 controls activation / inactivation of decode circuits 104 and 106 and sense amplifier circuit 110 in response to signal int / RAS from RAS buffer 122.
[0155]
The semiconductor memory device further includes a WE buffer 135 for generating a column decode enable signal and a read / write mode designating signal in response to external column address strobe signal int / CAS and external write enable signal ex / WE, and read / write. A read / write control circuit 136 for generating a read control signal and a write control signal in response to a mode designating signal, and amplifying data read from a selected memory cell in response to the read control signal to generate an I / O signal It includes a preamplifier 137 applied to buffer 139 and a write driver 138 for writing data applied from I / O buffer 139 to a selected memory cell in response to a write control signal.
[0156]
The storage device further includes an internal voltage generator 140 for generating external voltages VPP, VBL and VCP, and ICC array designation signals VCBS, VBBS and VPBS, or signals VCBSm and VCBS in response to signal / ICCTEST and array request signal BSm '. It includes an Icc test control circuit 150 that generates a set of VCSBS, VBBSm and VBBSBS, and a set of VPPBm and VPSB, respectively.
[0157]
Spare control circuit 142 corresponds to program circuits 10 and 12 shown in FIG. Gate circuit 15 for generating array designation signal BSn (m) is not clearly shown in FIG.
[0158]
Internal voltage generator 140 may include a step-down circuit that steps down an externally applied power supply voltage to generate an internal power supply voltage.
[0159]
In the configuration shown in FIG. 14, in the Icc2 test mode, signal int / RAS is maintained in an inactive state, and address buffer 126, row predecoder 127, row decoder circuit 104, column address buffer 132 and column decode circuit The column selection circuit such as 112 does not operate even if the external row address strobe signal ext / RAS is set to the active L level.
[0160]
On the other hand, signal int / RAST changes according to external signal ext / RAS even in this Icc2 test mode, and address buffer 124 and row predecoder 125 generate array request signal BSm 'according to external address signal exAb. That is, in the Icc2 test mode, Icc test control circuit 150 generates control signals VCES, VPBS and VBBS in accordance with array request signal BSm ', and only the designated memory array or spare memory array receives internal voltages VPP, VBL and VCP. Receiving the Icc2 test.
[0161]
FIG. 15 shows an example of the configuration of Icc test control circuit 150 shown in FIG. In FIG. 15, control circuit 150 includes an array selector 151 for generating signals VPBSm, VBBSmVCBSm in response to signals / ICCTEST and BSm ', and a spare array designation in response to signals int / RAST, / ICCTEST and address signal Ay. Spare control circuit 152 for generating signal BSS and spare array selector 153 for generating signals VPSBS, VCSBS and VBSDS for spare memory array SMA in response to signals BSS and / ICCTEST.
[0162]
Selectors 151 and 153 are activated when signal / ICCTEST is activated to an L level. When signal / ICCTEST is in the inactive state of H level and the Icc2 test mode is not specified, selectors 151 and 153 are disabled (inactive state), and signals VPBSm, VCBSm, VPSBS, and VBSBS are set. , And VCSBS are maintained at the H level. The logic for selectors 151 and 153 is easily implemented, for example, by an OR gate receiving signals BSm '(BSS) and / ICCTEST.
[0163]
Spare control circuit 152 generates a spare array designating signal BSS when an address signal Ay other than a block address (array designating address) is brought into a predetermined state at the time of activation of signals / ICCTEST and int / RAST. The spare control circuit 152 may include a decoder. The signal Ay may be provided via an unused pin, or a configuration generated based on a combination of states of a predetermined signal (control signal and / or address signal) may be used. Array selector 151 is provided for each of memory arrays MA1-MA4.
[0164]
FIG. 16 is a diagram showing an example of the configuration of the RAS buffer 122 shown in FIG. In FIG. 16, RAS buffer 122 receives a ground potential and an external row address strobe signal ext / RAS, a two-input NOR gate 161, an inverter 162 receiving an output signal of NOR gate 161 to generate a signal int / RAST, A NAND gate 163 receives the output signal of NOR gate 161 and signal / ICCTEST from ICC test detector 120 to generate signal int / RAS. Next, the operation of RAS buffer 122 will be described with reference to the operation waveform diagram of FIG.
[0165]
When signal / ICCTEST is at H level, NAND gate 163 functions as an inverter, and both signals int / RAS and int / RAST change according to external row address strobe signal ext / RAS. Therefore, the NOR gate 161 functions as a simple buffer.
[0166]
In the Icc2 test mode, signal / ICCTEST is set to the active state of L level, and NAND gate 163 maintains signal int / RAS at H level regardless of the state of external row address strobe signal ext / RAS. On the other hand, signal int / RAST changes according to external signal ext / RAS.
[0167]
When signal ext / RAS falls to L level, signal int / RAST attains L level, and (array) address signal ext. Ab is latched, and array request signal BSm 'is generated via address buffer 124 and row predecoder 125.
[0168]
Here, in order to bring address buffer 124 and row predecoder 125 into a standby state during the operation of Icc2 test mode, a latch circuit for latching their output signals is provided at the output portions of array selectors 151 and 153 shown in FIG. It may be.
[0169]
FIG. 18 is a diagram showing an example of the configuration of the ICC test detector 120 shown in FIG. 14 and FIG. In FIG. 18, ICC test detector 120 includes a test mode detector 170 for generating test mode designating signal TE in response to signals ext / RAS, ext / CAS and ext / WE, a test mode detection signal TE and a specific address. ICCTEST generator 172 for generating Icc2 test mode designating signal / ICCTEST in response to signal extAn. Next, the operation of the test detector 120 will be described with reference to the operation waveform diagram of FIG.
[0170]
Test mode detector 170 detects a write CAS before RAS (WCBR) condition in which external signals ext / WE and ext / CAS are both set to L level before external signal ext / RAS, and test mode of H level is set. Generates (activates) the designated signal TE. This write CAS before RAS condition is well known in the field of DRAM (Dynamic Random Access Memory), and is a standard of JEDEC (Joint Electronic Device Engineering Counsel) for specifying a test mode. Used.
[0171]
ICCTEST generator 172 is activated by active test mode designating signal TE. When specific address signal extAn rises to, for example, a super VIH level higher than a normal H level in this state, ICCTEST generator 172 generates an L level signal / ICCDEST. As a result, the Icc2 test mode is designated. By combining the WCBR condition and the address key with the super VIH condition, it is possible to enter the Icc2 test mode only when it is absolutely necessary, and to reliably prevent the Icc2 test operation mode from being mistakenly entered during normal operation. Is done.
[0172]
In the configuration shown in FIG. 18, signal / ICCTEST is generated by a combination of the WCBR condition and the address key, but a configuration is used in which a dedicated pad is provided and signal / ICCTEST is externally applied. An arrangement may be used in which the test is performed in a wafer test where all chips on the wafer are tested.
[0173]
FIG. 20A is a diagram showing a configuration for one bit of row address buffer 126 shown in FIG. In FIG. 20A, a row address buffer circuit (126) is cascaded in two stages with a transmission gate 181 transmitting an external address signal extAw onto signal line 186 in response to complementary address latch enable signals ALC and / ALC. A latch 182 including an inverter for latching a signal on signal line 186, an inverter 183 for inverting a signal on signal line 186, and a NOR gate 184 receiving address enable signal / AE and a signal on signal line 186; , And a NOR gate 185 receiving an address enable signal / AE and an output signal of inverter 183. NOR gate 185 outputs an internal address signal AW, and NOR gate 184 outputs an internal address signal / AW. The manner of generating signals ALC, / ALC, AE and / AE will be described later, but these signals ALC, / ALC, AE and / AE are generated in response to signal int / RAS. Next, the operation will be briefly described.
[0174]
In a standby state in which signal int / RAS is inactive, signals / ALC and / AE both attain an H level. In this state, transmission gate 181 is turned off, and NOR gates 184 and 185 output L-level signals / Aw and Aw.
[0175]
In the active cycle, signals ALC and / ALC are generated in the form of a one-shot pulse, during which transmission gate 181 is turned on. Thus, the external signal extAw is transmitted on the signal line 186 and latched by the latch 182. Next, when signal / AE attains L level, NOR gates 184 and 185 operate as inverters and output internal address signals / Aw and Aw, respectively.
[0176]
FIG. 20B is a diagram showing a 1-bit configuration of row (array) address buffer 124. This row address buffer circuit (124) has the same configuration as the row address buffer circuit 126 shown in FIG. 20A. The operation will be described only briefly, simply because the applied signals are different.
[0177]
Transmission gate 191 is turned on when array address latch enable signals ALCB and / ALCB are at H and L levels, respectively, and transmits external (array) address signal extAb onto signal line 196. The signals ALCB and / ALCB are also generated in the form of a one-shot pulse when activated. Latch 192 latches the signal transmitted on signal line 196 via transmission gate 191.
[0178]
When array address enable signal / AEB is at L level, NOR gates 194 and 195 function as inverters, and generate internal array address signals / Ab and Ab in accordance with the address signal latched by latch 192, respectively. NOR gates 194 and 195 output an L level signal when signal / AEB is at an H level in a standby state. Here, the inverter 193 inverts the signal on the signal line 196 and supplies the inverted signal to the NOR gate 195.
[0179]
Signals ALCB, / ALCB and / AEB are generated in response to signal int / RAST, as described below.
[0180]
FIG. 21A is a diagram showing a configuration for generating signals ALC and ALCB. Since signals ALC and ALCB are both generated by circuits having the same configuration, FIG. 21A shows only a configuration for generating signal ALC. In FIG. 21A, delay circuit 200 delays signal int / RAS (int / RAST) for a predetermined period and supplies it to inverter 201. Inverter 201 inverts the output signal of delay circuit 200 and supplies the inverted signal to one input of NOR gate 202. Signal int / RAS (int / RAST) is applied to the other input of NOR gate 202. Signal ALC (ALCB) is generated from NOR gate 202, and signal / ALC (/ ALCB) is generated from inverter 203 receiving the output signal of NOR gate 202. Next, the operation of the circuit shown in FIG. 21A will be described with reference to the operation waveform diagram of FIG. 21B.
[0181]
When signal int / RAS (int / RAST) is at H level, signal ALC from NOR gate 202 goes to L level. When signal int / RAS (int / RAST) falls to L level, the output signal from delay circuit 200 goes to L level after a predetermined delay time has elapsed, and the output signal of inverter 201 rises to H level. NOR gate 202 outputs an H level signal when signal int / RAS (int / RAST) and the output signal of inverter 201 are both at L level. Therefore, signal ALC (ALCD) is at H level for a predetermined delay time of delay circuit 200 after signal int / RAS (int / RAST) falls, during which transmission gate 181 and transmission gate 181 shown in FIGS. 191 is turned on.
[0182]
FIG. 22A is a diagram showing a configuration of a circuit for generating signals / AE and / AEB. Since address enable signals / AE and / AEB are generated from circuits having the same configuration, FIG. 22A shows only a circuit configuration for generating one of signals / AE and / AEB.
[0183]
22A, an address enable signal generating system includes an inverter 210 that receives and inverts a signal int / RAS (int / RAST), a delay circuit 211 that delays an output signal of the inverter 210 for a predetermined time, and an output signal of the inverter 210. And a NAND gate 212 receiving an output signal of delay circuit 211. Signal / AE (/ AEB) is output from NAND gate 212. Next, the operation of the circuit shown in FIG. 22A will be described with reference to an operation waveform diagram of FIG. 22B.
[0184]
When signal int / RAS (int / RAST) is at H level, the output signal from inverter 210 is at L level, and signal / AE (/ AEB) from NAND gate 212 is at H level.
[0185]
When signal int / RAS (int / RAST) falls to H level, the output signal of inverter 210 rises to H level. When a predetermined time (delay time of relay circuit 211) elapses after the output signal of inverter 210 rises, the output signal of delay circuit 211 rises to the H level, and the signals applied to both inputs of NAND gate 212 are both inputted. H level, and signal / AE (/ AEB) from NAND gate 212 falls to L level. When signal int / RAS (int / RAST) rises to H level, signal / AE (/ AEB) rises to H level in response to the rise.
[0186]
FIG. 23 is a diagram showing the configuration of another embodiment for realizing the Icc2 test in array units according to the present invention. In FIG. 23, an alternative configuration of ICC test control circuit 150 is shown. In FIG. 23, mode detector 220 is provided to determine which of the high voltage VPP test mode, the intermediate voltage VBL test mode and the cell plate voltage VCP test mode has been designated in accordance with signal WCBR and the address key. . The mode detector 220 is enabled when the signal / ICCTEST is in an active state, and takes in and latches the signal WCBR and the address key in response to the signal int / RAST. The signal WCBR corresponds to the signals ext / CAS, ext / RAS, and ext / WE that satisfy the write, CAS, before, and RAS conditions. The address key indicates an address signal applied to a specific address input pin terminal.
[0187]
Array selector 151 includes a high voltage mode array selector 151P, an intermediate voltage array selector 151B, and a cell plate voltage array selector 151C. One of selectors 151P, 151B and 151C is enabled in response to the output signal of mode detector 220. Selectors 151P, 151B and 151C generate control signals VPBSm, VBBSm and VCBSm according to array request signal BSm 'and the output signal of mode detector 220, respectively. Signal VPBSm specifies a memory array that receives the voltage test mode, signal VBBSm specifies a memory array that receives the intermediate voltage test mode, and signal VCBSm specifies a memory array that receives the cell plate voltage test mode.
[0188]
Spare array detector 153 includes a spare array selector 153P for high voltage VPP, a spare array selector 153B for intermediate voltage VBL, and a spare array selector 153C for cell plate voltage VCP. One of the selectors 153P, 153B and 153C is enabled according to the output of the mode detector 220. Selectors 153P, 153B and 153C output control signals VPSBS, VBSBS and VCSBS, respectively, when enabled in response to the output signal of spare control circuit 152.
[0189]
In the Icc2 test mode, the high voltage VPP mode, the intermediate voltage VBL mode, and the cell plate mode VCP mode are sequentially executed for each memory array, or one test mode is executed for all memory arrays, and then another test mode is executed. (VPP, VBL and VCP test modes) are again executed for all the memory arrays. By performing the Icc2 test for each of the internal voltages in this manner, the leakage current sources during the Icc2 test are classified into the high voltage VPP generation source, the intermediate voltage VBL generation source, and the cell plate voltage VCP generation source. This is extremely effective in performing failure analysis.
[0190]
In the configuration shown in FIGS. 15 and 23, when a spare memory array is selected in the Icc2 test mode, array controller 151 does not clearly show, but spare control is performed as shown by a broken line arrow in FIG. The disable state is set based on the output signal of the circuit 152.
[0191]
The configuration shown in FIGS. 15 and 23 is provided with a plurality of spare memory arrays, and can be easily expanded to a configuration in which spare control circuit 152 selects one spare memory array from the plurality of spare memory arrays. it can. In this case, the spare control circuit 152 does not need to be provided. When such a spare control circuit 152 is not provided, an array request signal BSm 'designating a memory array to be replaced with a spare array is generated by programming a fuse element at the time of block replacement in step S2 shown in FIG. By using a configuration for transferring data to the spare array selector 153, a spare array can be selected.
[0192]
FIG. 24 is a diagram schematically showing an overall configuration of a semiconductor memory device according to still another embodiment of the present invention. In the configuration shown in FIG. 24, the semiconductor memory device includes four memory blocks MB1-MB4. Each of memory blocks MB1-MB4 includes four memory arrays MAbm (b = 1-4, m = 1-4) and four spare arrays SMAbm. That is, the configuration shown in FIG. 24 has a configuration in which a plurality of memory arrays and spare arrays of the semiconductor memory device described above are provided as one memory block. Activation of the memory block and the memory array is appropriately determined by the configuration of the data input / output pin terminals.
[0193]
Memory array MAbm receives internal voltages (VPP, VBL and VCP) on internal voltage line 1-b via switching element TZbm, and spare memory array SMAbm switches the internal voltage on internal voltage line 1-b again. Received via element TZb (m + 4). Switching elements TZb1-TZb8 are turned on and off by 8-bit control signal VBSb.
[0194]
FIG. 25 shows a structure for generating a control signal for supplying internal voltages such as high voltage VPP, intermediate voltages VBL and VCP to each memory array or spare memory array in the structure shown in FIG. 25, block decoder 300 receives a block address signal AB designating memory block MB (MB1-MB4), and takes in and decodes block address signal AB in response to signal int / RAST to decode internal block designating signal. Occurs.
[0195]
Array decoder 302 corresponds to block decoder 125 shown in FIG. 14, receives array address signal AD, takes in and decodes array address signal AD in response to signal int / RAST, and designates a memory array in each memory block. The internal array request signal BSm 'is generated.
[0196]
ICC test detector 120 corresponds to detector 120 shown in FIGS. 14 and 18, and generates Icc2 test mode designation signal / ICCTEST in response to address key AD1 and signal WCBR indicating the WCBR condition.
[0197]
Spare array ICC test detector 304 detects that an Icc2 test for the spare array has been requested in response to address key ADh and signal WCBR.
[0198]
Control signal VBSbm for memory array MAbm of memory block MBb is generated by NAND gate 318 and inverter 320. NAND gate 318 includes a memory block designating signal from block decoder 300, an array request signal BSm 'from array decoder 302, an Icc2 test mode designating signal / ICCTEST applied via inverter 310, and a spare array ICC test detector. And receives a spare array request signal / ICS provided from 304. Inverter 320 inverts the output signal of NAND gate 318 to generate control signal VBSbm.
[0199]
Control signal VSDSbm for spare memory array SMAbm of memory block MBb is generated by NAND gate 314 and inverter 316. NAND gate 314 is supplied via block designation signal from block decoder 300, array request signal BSm 'from array decoder 302, Icc2 test mode designation signal / ICCTEST supplied via inverter 310, and inverter 312. Spare array request signal / ICS is received. Next, the operation of the configuration shown in FIG. 25 will be briefly described.
[0200]
When external row address strobe signal ext / RAST falls to L level, block decoder 300 and array decoder 302 respectively take in and apply the applied address signal and decode (int / RAST changes according to external signal ext / RAS). . In the configuration shown in FIG. 25, internal row address strobe signal int / RAS is controlled by signal / ICCTEST. The signal int / RAS inhibits a row selecting operation in the memory array or the spare array in the Icc2 test mode. Memory block and memory array selecting operation is performed according to signal int / RAST shown in FIG.
[0201]
When the Icc2 test mode is designated by specific address key ADk and signal WBCR, signal / ICCTEST from Icc2 test detector 120 is activated at an L level, and the output signal of inverter 310 rises to an H level. At this time, if a spare array is not designated, signal / ICS from spare array ICC test detector 304 is at an inactive H level. Next, block decode 300 and array decode 302 decode block address AB and array address AD, respectively, and generate a block designation signal and an array request signal. Thereby, an Icc2 test is performed on memory array MAbm specified by array request signal BSm 'in a memory block specified by the memory block specifying signal. This is because signal VBSbm from inverter 320 attains an H level, and internal voltages (VPP, VCP and VBL) are supplied only to a specified memory array in the specified memory block. In unselected memory blocks and unselected memory arrays, signal VBSbm attains L level, and no internal voltage is supplied.
[0202]
On the other hand, the signal / ICS from spare array ICC test detector 304 is at H level, the output signal of inverter 312 is at L level, and NAND gate 314 is disabled. The array control signal VSBSbm becomes L level, and the supply of the internal voltage to the spare array is prohibited. When performing an Icc2 test on a spare array, first, signals ADh and WCBR are set to a specific state, and signal / ICS from spare array ICC test detector 304 attains an L level. In this state, NAND gate 318 is disabled, and control signal VBSbm for memory array MAbm is at the inactive L level.
[0203]
On the other hand, inverter 312 outputs an H level signal, and NAND gate 314 outputs an L level signal according to the output signals from decoders 300 and 302. Thereby, control signal VSBSbm for the spare array designated by array decoder 302 in the selected memory block is activated to the H level. An Icc2 test is performed on the designated spare memory array SMAbm.
[0204]
When the Icc2 test is not performed, signal / ICCTEST is set to H level. When performing a function test, it is necessary to supply an internal voltage to memory array MAbm and / or spare memory array SMAbm. In order to realize this internal voltage supply, an OR gate receiving signal / ICCTEST at one input and receiving the output of the corresponding inverter at the other input is provided at the output of each of inverters 320 and 316. Thus, when a function test for detecting an individual (individual word line) defect is performed on each memory array after the completion of the Icc2 test in array units, even if signal / ICCTEST is set to H level, each memory array and spare memory array are An internal voltage can be supplied, and a functional test can be reliably performed.
[0205]
If a defective spare array is detected, the defective spare array is separated by cutting its fuse element from the internal voltage line. Although FIG. 24 does not show a fuse element provided for the memory array, a fuse element is provided for each memory array and spare array in series with the switching element.
[0206]
FIG. 26 shows a configuration for realizing a function test of spare memory array SMAbm. FIG. 26 representatively shows spare row decoder SRDb (m, n) included in spare row decoder block SRDb provided for the spare memory array block of memory block MAb. Spare test array decoder 320 is enabled by test mode designating signal TE, and generates a spare array designating signal according to signal WCBR and a specific address key (ADh).
[0207]
Program circuit 321 corresponds to program circuits 10 and 12 shown in FIG. 2, and generates a programmed spare array designation signal BSn (m). This program circuit 321 is provided for each spare row decoder SRDb (m, n).
[0208]
Multiplexer 322 selects one of the output signal of decoder 320 and the output signal of program circuit 312 according to test mode designating signal TE. In the functional test mode, test mode designating signal TE is in an active state, and multiplexer 322 selects an output signal of spare test array decoder 320 and supplies the signal to spare row decoder SRDb (m, n).
[0209]
Spare row decoders SRDb (m, n) are provided for spare word lines WLb (s, n) in the corresponding spare array, respectively. Although not explicitly shown in FIG. 26, spare row decoder SRDb (m, n) receives a row predecode signal output from the row predecoder as shown at 127 in FIG. This row predecoder is provided for each of memory blocks MB1-MB4. Only the row predecoder provided for the memory block specified by the block address signal is enabled, and a function test of the memory array or the spare memory array is executed in the specified memory block.
[0210]
In the above-described configuration, only one memory block is designated. However, in a configuration in which multi-bit data is input / output, a configuration in which four memory blocks MB1-MB4 are designated at the same time is used. Is also good. In the case of such a multi-bit data configuration, the block decoder 300 shown in FIG. 25 has a configuration in which one memory block is designated in the Icc2 test mode according to a specific address key similarly to the spare test array decoder 320 shown in FIG. By using the Icc2 test, it is possible to perform the Icc2 test in array units, and further to perform the Icc2 test in block units.
[0211]
In the configuration shown in FIG. 24, memory block MBb may include eight or more memory arrays, and the number of spare memory arrays included in one memory block is not limited to four. Further, the memory array and the spare memory array may be configured to include 16 or more word lines.
[0212]
FIG. 27 is a diagram schematically showing an overall configuration of a semiconductor memory device according to still another embodiment of the present invention. In the configuration shown in FIG. 27, each of memory arrays MA1-MA4 includes a normal word line region WLm (m = 1-4) and a redundant word line region SNWLm. Similarly, spare memory array SMA includes a spare word line region SWL and a spare redundant word line region SRWL.
[0213]
Memory arrays MA1-MA4 and spare memory array SMA have the same configuration, and each of normal word line regions WL1-WL4 has a configuration similar to that shown in FIG. , And a plurality of normal word lines (16 lines) associated with the spare word lines in the spare word line region SWL included in the spare memory array SMA in a one-to-one manner. A redundant word line included in redundant word line region RWLm provided in each of memory arrays MA1-MA4 can be replaced with a normal word line included in normal word line region WLm in the same memory array MAb. Spare redundant word lines in spare redundant word line region SRWL can be replaced with spare word lines in spare word line region WL. Each of redundant word line regions RWL1-RWL4 and SRWL includes one or more redundant word lines.
[0214]
Row decoder blocks RD1-RD4 are provided for normal word line regions WL1-WL4, respectively, and redundant row decoder blocks SND1-SND4 are provided for redundant word line regions RWL1-RWL4, respectively. Each of row decoder blocks RD1-RD4 includes a normal row decoder provided corresponding to each normal word line. The configuration of the row decoders included in row decoder blocks RD1-RD4 is the same as that shown in FIG. Each of redundant row decoder blocks SND1-SND4 includes a redundant row decoder provided corresponding to a redundant word line in corresponding redundant word line region RWL1-RWL4. The configuration of this redundant row decoder will be described later.
[0215]
A spare row decoder block SRD is provided commonly for spare word line region SWL and spare redundant word line region SRWL. Block SRD includes a spare row decoder provided for spare word lines SWL (s, 1) -SWL (s, 16) and a spare redundant decoder provided for spare redundant word lines in spare redundant word line region SRWL. including. The spare row decoder has the same configuration as that shown in FIG.
[0216]
Internal voltage VI (VPP, VBL, VCP) on internal transmission line 1 is supplied to each of memory arrays MA1-MA4 via link elements (fuse elements) F1-F4 which can be blown. Spare memory array SMA is supplied with internal voltage VI via switching element SW1. The setting of the on / off state of these fuse elements F1 to F4 and switching element SW1 is performed in the same manner as in the above-described embodiment. Next, relief of a "bad" normal word line in the configuration shown in FIG. 27 will be described.
[0219]
To simplify the description, redundant word line regions RWL1 to RWL4 each include one redundant word line RWL (m, 1), and spare redundant word line region SRWL also includes one spare redundant word line. It is assumed that SRWL (s, 1) is included.
[0218]
As shown in FIG. 28, when there are two repairable defective normal word lines WL (1,4) and WL (1,8) in the normal word line region WL1 of the memory array MA1, these are as follows. Will be rescued in this way. First, the word line WL (1,4) is replaced with a spare word line SWL (s, 4) included in the spare word line region SWL of the spare memory array SMA, and the word line WL (1,8) is Replaced with redundant word line RWL (1, 1) in redundant word line region RWL1 included in MA1. Thereby, even when it is determined that the word line WL (m, 8) is defective in another memory array, the defective word line WL (m, 8) is replaced with the spare word line SWL ( s, 8), the efficiency of repairing the defective word line is improved.
[0219]
When the spare word line SWL (s, 4) is defective, the spare word line SWL (s, 4) is replaced with a spare redundant word line SRWL (s, 1). The replacement of the spare word line will be described later.
[0220]
By employing the above-described replacement method, even when a plurality of word lines are defective at the same row address, these defective word lines can be relieved.
[0221]
Next, consider a state in which one memory array MA1 includes a repairable defective normal word line WL (1, 4) and a memory array MA2 includes a repairable defective normal word line WL (2, 4). In this case, as shown in FIG. 29, word line WL (1,4) is replaced with spare word line SWL (s, 4), and word line WL (2,4) is replaced with redundant word line RWL of memory array MA2 itself. Replaced with (2,1).
[0222]
If there is only one normal word line that can be repaired in each of memory arrays MA1-MA4, the defective normal word line is replaced with a redundant word line in the corresponding redundant word line region, and the spare memory array is A configuration in which the switching element SW1 is maintained in the off state without using the same may be used. In such a case, current consumption in spare memory array SMA can be eliminated, and current consumption can be reduced.
[0223]
When a defective normal word line that cannot be repaired exists in a certain memory array, this memory array is replaced with a spare memory array SMA (array replacement). Also in this case, even when there are defective normal word lines that can be rescued in the remaining memory arrays, rescue can be performed using the redundant word lines in the corresponding redundant word line regions.
[0224]
FIG. 30 shows a configuration for realizing word line replacement in each of memory arrays MA1-MA4. 30, defective address program circuit LP includes four link program circuits L1-L4 (corresponding to LINK1-LINK4) provided corresponding to memory arrays MA1-MA4, respectively. Each of link program circuits L1-L4 has a configuration similar to that of the circuit shown in FIG. 35, and a defective row address is programmed by blowing a fuse element corresponding to a defective address.
[0225]
Each of link program circuits L1-L4 has a defect indicating a defective normal word line to be replaced with a redundant word line (RWL (1,1) -RWL (4,1)) of a corresponding memory array (MA1-MA4). Storing the row address data, comparing the applied (pre-decoded) row address signal with the stored bad row address data, and providing a signal indicating whether the programmed bad row has been addressed. Output.
[0226]
Output signals of link program circuits L1-L4 of defective address program circuit LP are applied in parallel to determination gate DC. The determination gate DC corresponds to the NOR gate NO31 and the inverter INV31 shown in FIG. When the defective address program circuit LP indicates that the defective normal word line has been addressed, the determination gate DC outputs an active state (H level) signal.
[0227]
Redundant decoder SNDm is provided corresponding to redundant word line RWL (m, 1) included in corresponding redundant word line region RWLm, and receives and receives an output signal of determination gate DC and an array designation signal BSm '. When both signals are active, corresponding redundancy word line RWL (m, 1) is driven to a selected state (high voltage VPP level).
[0228]
FIG. 31 shows a configuration for realizing replacement of a spare word line or a spare redundant word line. The configuration shown in FIG. 31 corresponds to the configuration shown in FIG. In the configuration shown in FIG. 31, a pull-up resistor RPn having a large resistance value is provided between a node supplying high voltage VPP and signal line 5. The other configuration shown in FIG. 31 is the same as the configuration shown in FIG. 2. Corresponding portions have the same reference characters allotted, and detailed description thereof will be omitted. The structure shown in FIG. 31 is provided corresponding to spare word lines SWL (s, 1) -SWL (s, 16) and spare redundant word line SRWL (s, 1).
[0229]
The method of programming the program circuits 10 and 12 is the same as the method of programming in the configuration shown in FIG. If spare word line SWL (s, n) is defective, fuse element Fn. 1, Fn. 2, Fn. 3 and Fn, 4 are all cut. Thereby, signal line 5 is connected to NAND gate NAn. 1-NAn. 4 and its potential is pulled up to a high voltage VPP level by a pull-up resistor RPn. Signal BSEn output from inverter INVn is fixed at L level, and the corresponding spare word line SWL (s, n) is always in a non-selected state. In program circuits 10 and 12 provided for spare redundant word line SRWL (s, 1), fuses are selected such that array designating signal BSm 'designating a memory array using a corresponding defective spare word line is selected. The device is programmed. Thus, replacement of a defective spare word line by a spare redundant word line is realized.
[0230]
Here, as will be described later, the row address itself of the defective spare word line is programmed by another link circuit (having the same configuration as the link program circuit shown in FIG. 30).
[0231]
FIG. 32 schematically shows an entire configuration of a row selection system in a configuration in which a redundant word line region is provided in each memory array. In FIG. 32, to simplify the drawing, normal word line WL (m, n), redundant normal word line RWL (m, 1), spare word line SWL (s, n) and spare redundant word line SRWL (s) , 1) are only representatively shown.
[0232]
Address buffer 1 receives an external address signal and generates an internal address signal. The external address signal includes a block address signal for specifying a memory array and a row address signal for specifying a word line address (row address) in the memory array. Block decoder 2 decodes the block address signal supplied from address buffer 1, and generates a block designating signal (array request signal) BSm '.
[0233]
Row predecoder RPD predecodes the internal row address signal applied from address buffer 1, and generates row predecode signals Xi and Xj (see FIGS. 5 and 6).
[0234]
Bad row address program circuit LP includes four link program circuits L1-L4 as shown in FIG. 30, and stores (programmed) bad row address data stored therein in a row pre-decoder RPD. The signal is compared with the decoded signal and a signal indicating the result of the comparison is generated.
[0235]
Discrimination gate DC includes a NOR gate and an inverter as shown in FIG. 35, and generates a redundancy decoder enable signal SEE according to the output signal of defective row address program circuit NP.
[0236]
Spare program circuit STD provided for spare word line SWL (s, n) has a configuration shown in FIG. 31, includes a NAND gate and an inverter, and uses a corresponding spare word line SWL (s, n). When the array is designated by block designation signal BSm ', spare decoder enable signal BSEn is activated. Redundant program circuit SSRD provided for spare redundant word line SRWL (s, 1) also has the configuration shown in FIG. 31 and has the same configuration as spare program circuit SPD, and spare redundant word line SRWL (s, 1). ), The spare redundant decoder enable signal BSEs is activated when the memory array using ()) is designated by the block designating signal BSm '.
[0237]
Inverter IVm inverts block designating signal BSm 'from block decoder 2. This configuration is the same as the configuration shown in FIG.
[0238]
Gate GD corresponds to NOR gate NOn (m) shown in FIG. 3, and receives signals BSm, BSEn, BSEs and SEE. Gate GD generates an active word line enable signal BSn (m) when signals BSEm, BSEs and SEE are all inactive and signal BSm is active.
[0239]
A link program circuit L5 is provided for spare redundant decoder SRD (s, s). The link program circuit L5 has the same configuration as the link program circuits LINK1 to LINK4 shown in FIG. 35, stores a defective spare word line address by programming (cutting) its fuse element, and receives a predecode signal supplied from a row predecoder RPD. And the programmed row spare word line address data, and outputs a signal according to the comparison result. By providing the link program circuit L5, a defective spare word line can be relieved using a spare redundant word line.
[0240]
Redundant decoder SNDm includes a NAND gate and an inverter similarly to the configuration shown in FIG. 35, receives signals BSm and SEE, and when both signals BSm and SEE are active, corresponding redundant word line RWL (m, 1) Is driven to the selected state.
[0241]
Row decoder RD (m, n) has the same configuration as the row decoder shown in FIG. 5, and the predecode signal from row predecoder RPD specifies the row address of normal word line WL (m, n) and signal BSn ( When m) is in the active state, the corresponding normal word line WL (m, n) is driven to the selected state.
[0242]
Spare row decode SRD (s, n) has the same configuration as that shown in FIG. 6 and includes a NAND gate and an inverter, and a row predecode signal from row predecoder RPD receives a corresponding spare word line SWL (s, n). When the row address of n) is designated and the signal BSEm is in the active state, the corresponding spare word line SWL (s, n) is driven to the selected state.
[0243]
Spare redundant row decode SRD (s, n) has the same configuration as redundant row decoder SNDm, and when both the output signal of link program circuit L5 and the output signal BSEs of redundant program circuit SSPD are active, the corresponding spare redundant word line Drive SRWL (s, 1) to the selected state.
[0244]
Next, the operation of the configuration shown in FIG. 32 will be specifically described with reference to FIGS. 28 and 29 together.
[0245]
When defective normal word line WL (1, 4) is designated (see FIG. 28), a block designating signal designating memory array MA1 is programmed in program circuit SPD, and signal BSEn is activated. , The gate GD is disabled. Thereby, signal BSn (m) is deactivated, and all normal word lines WL (m, 4) are deselected. On the other hand, spare row decoder SRD (s, 4) is enabled by signal DSEn (n = 4 in this case), and selects corresponding spare word line SWL (s, 4) according to the row predecode signal output from row predecoder RPD. Drive to state.
[0246]
In this case, as shown in FIG. 29, when the word line WL (2, 4) is defective, the row address “2” for the word line WL (2, 4) is stored in the program circuit LP. The signal SEE is activated by LP and DC. However, block specifying signal BS2 output from inverter IVm (m = 2) is inactive (memory array MA1 is specified), and redundant row decoder SNDm is disabled, so that redundant word is disabled. Line RWL (2, 1) maintains the non-selected state.
[0247]
If the normal word line WL (2, 4) is addressed (see FIG. 29), the memory array MA1 is programmed as the output signal BSE4 from the spare program circuit SPD, and the memory array MA2 is designated now. Therefore, spare word line SWL (s, 4) is not selected (spare row decoder SRD (s, 4) is disabled).
[0248]
On the other hand, signal SEE is activated by program circuit LP and determination gate DC, block designating signal BS2 designating memory array MA2 is also activated, redundant row decoder SNDm is activated, and redundant word line RWL (2, 1 ) Is selected. That is, the defective normal word line WL (2, 4) is replaced with the redundant word line RWL (2, 1).
[0249]
When spare word line SWL (s, n) is replaced with spare redundant word line SRWL (s, 1), signal BSEn is inactive when spare word line SWL (s, n) is designated, On the other hand, signal BSEs is activated. The output signal of link program circuit L5 is activated, and decoder SRD (s, s) drives corresponding spare redundant word line SRWL (s, s) to the selected state. At this time, the gate DD is disabled by the signal BSEs, and the normal word line WL (m, n) is in a non-selected state.
[0250]
In the above description, redundant word line regions WL1-WL4 and spare redundant word line region SRWL are described as including only one redundant word line. However, the number of redundant word lines provided in each region may be two or more. In this case, one redundant word line is easily selected from a plurality of redundant word lines by expanding the configuration shown in FIG. The configuration is realized.
[0251]
Instead of using the link program circuits L1-L4 and L5, a redundant word line rescue method according to so-called "shift redundancy" may be used. The structure in which the memory array includes normal word lines and redundant word lines as shown in FIG. 27 may be used in combination with another structure for performing an Icc2 test.
[0252]
【The invention's effect】
As described above, according to the present invention, the spare array and the memory array include the same number of word lines, and if there is no defective word line, the spare array word line and the memory array word line are paired. Since the correspondence is made in one mode, both replacement in word line units and replacement in array units can be easily performed.
[0253]
By providing a switching element for each array, an Icc2 test can be performed for each array, and a defective array can be detected at high speed.
[0254]
That is, in the semiconductor memory device according to the first aspect, the word line included in each memory array and the word line included in at least one spare word line are uniquely associated with each other when no defective word line exists. Therefore, word line replacement or array replacement can be easily realized with a simple circuit configuration in accordance with the defective mode of the defective word line, the defective word line relief efficiency is improved, and the product yield is greatly improved.
[0255]
In the semiconductor memory device according to the second aspect, each of the memory array and the spare array is provided with a redundant word line, and each word line of the memory array is a redundant word line included in a spare word line or a spare redundant word line of the spare array or the memory array itself. Since the word line can be replaced with a word line, the number of defective word lines that can be repaired is greatly increased, and the efficiency of repairing the defective word line is improved.
[0256]
In the semiconductor memory device according to the third aspect, a row decoder provided for a memory array for selecting a word line and a spare decoder provided for a spare array for selecting a spare word line have the same logical configuration. And a row address signal can be applied to both of them in common, thereby simplifying the control and configuration of word line replacement. Further, the same layout pattern can be repeated for the row decoder and the spare decoder, so that the layout of the decoder is simplified and the occupied area is reduced. Access delay does not increase.
[0257]
The semiconductor memory device according to claim 4, wherein the internal voltage is supplied to each memory array via a fuse element and the internal voltage is supplied to a spare array via a switching element. The defective array can be easily replaced by programming the elements and switching elements.
[0258]
In the semiconductor memory device according to the fifth aspect, the internal voltage is supplied to each memory array via a fuse element, and the internal voltage is supplied to a spare array via a switching element. When only possible defective word lines are present, all the fuse elements are turned on and the switching elements are turned on, so that replacement can be performed in word line units.
[0259]
In the semiconductor memory device according to the sixth aspect, in the standby current test mode, the operation of the block decoder is performed and the operation of the row decoder is inhibited, so that generation of the row address signal is inhibited, and Since only the designating signal is generated and the switching element is selectively turned on to supply the internal voltage only to the array designated by the array designating signal, a standby current test can be performed for each array. Detecting a defective array can be performed easily and at high speed.
[0260]
In the semiconductor memory device according to the seventh aspect, in the standby current test mode, the operation of the row selection related circuit is prohibited and only the array selection related circuit is operated, so that the standby current test in array units is performed. Can be easily performed.
[0261]
In the semiconductor memory device according to the present invention, a spare array designating signal generating means is provided, and in a standby current test mode, a spare array is designated according to a spare array designating signal from the spare array designating signal generating means to designate an internal voltage. Since the supply of the internal voltage to the spare array and the supply of the internal voltage to the other arrays are prohibited, a standby current test can be performed on the spare array, and good / defective of the spare array can be detected at high speed. This eliminates the need for a step of replacing a defective word line with a spare word line in the defective spare array, thereby shortening the test time of the semiconductor memory device.
[0262]
10. The semiconductor memory device according to claim 9, wherein a plurality of memory blocks each including a plurality of memory arrays and at least one spare array are provided, and a defective word line is replaced with a spare word line for each of the plurality of memory blocks. Since the replacement control circuit is provided, a defective word line / defective array can be relieved in each of the memory blocks even in a semiconductor memory device having a plurality of memory blocks, and the product yield is greatly improved.
[0263]
In the semiconductor memory device test method according to the tenth aspect, a standby current test is performed for each array, and when a defective array exists, the standby array is replaced with a spare array, a standby current for the spare array is performed, and then standby for all arrays is performed. Since the configuration is such that a functional test is performed after the completion of the current test to remedy a defective word line, both replacement in units of word lines and replacement in units of arrays can be easily realized. When a defective spare array is detected, the semiconductor memory device is determined to be defective. Therefore, it is not necessary to replace a defective word line with a spare word line in the defective spare array, and the test time of the semiconductor memory device is greatly reduced. Is done.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a configuration of a main part of a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a diagram showing a configuration of a program circuit for enabling a spare row decoder shown in FIG. 1;
FIG. 3 is a diagram schematically showing a configuration of a circuit for generating a signal for enabling a row decoder shown in FIG. 1;
FIG. 4 is a diagram illustrating a correspondence relationship between the configuration shown in FIGS. 2 and 3 and a word line and a spare word line.
FIG. 5 is a diagram showing a configuration of a row decoder shown in FIG.
FIG. 6 is a diagram showing a configuration of a spare row decoder shown in FIG. 1;
FIG. 7 is a diagram for explaining a signal flow in a row selection system in the configuration shown in FIG. 1;
FIG. 8 is a diagram showing an overall arrangement of a row decoder and a spare row decoder shown in FIG. 1;
FIG. 9 is a diagram illustrating an example of a configuration of a switching element illustrated in FIG. 1;
FIG. 10 is a diagram showing another configuration of the switching element shown in FIG.
11 is a diagram showing another configuration of the row decoder and the spare decoder shown in FIG.
FIG. 12 is a flowchart illustrating a method for testing a semiconductor memory device according to the present invention.
13 is a diagram showing a configuration of a semiconductor memory device for realizing the test method shown in FIG.
14 is a block diagram schematically showing an overall configuration of the semiconductor memory device shown in FIG.
FIG. 15 is a diagram schematically showing a configuration of an ICC test control circuit shown in FIG. 14;
16 is a diagram showing a configuration of the RAS buffer shown in FIG.
17 is a signal waveform diagram representing an operation of the RAS buffer shown in FIG.
FIG. 18 is a diagram showing a configuration of the ICC test detector shown in FIG.
19 is a signal waveform diagram representing an operation of the ICC test detector shown in FIG.
20 is a diagram showing a configuration of a row address buffer shown in FIG.
21 is a signal waveform diagram representing a configuration and an operation of a circuit for generating an array latch enable signal shown in FIG.
FIG. 22 is a signal waveform diagram representing a circuit configuration and an operation for generating the address enable signal shown in FIG. 20.
23 is a diagram showing a configuration of the ICC test control circuit shown in FIG.
FIG. 24 schematically shows an entire configuration of a semiconductor memory device according to another embodiment of the present invention.
25 is a diagram showing a configuration for generating a switching element control signal shown in FIG. 24.
FIG. 26 shows a structure for performing an Icc2 test of a spare array.
FIG. 27 schematically shows an entire configuration of a semiconductor memory device according to still another embodiment of the present invention.
28 is a view illustrating a method of relieving a defective word line in the semiconductor memory device shown in FIG. 27;
29 is a diagram showing a method of relieving a defective word line in the semiconductor memory device shown in FIG.
30 is a diagram schematically showing a configuration of a program circuit for the redundant row decoder shown in FIG. 27;
FIG. 31 shows a structure of a program circuit for the spare row decoder shown in FIG. 27.
32 is a diagram schematically showing a configuration of a row selection system in the semiconductor memory device shown in FIG. 27;
FIG. 33 schematically shows an entire configuration of a conventional semiconductor memory device.
FIG. 34 schematically shows a configuration of a row selection system in a conventional semiconductor memory device.
FIG. 35 is a diagram showing the configuration of a row selection system in a conventional semiconductor memory device in more detail.
FIG. 36 shows a structure of a row decoder and a spare row decoder in a conventional semiconductor memory device.
FIG. 37 is a diagram showing a configuration of a portion related to one column of memory cells in a conventional semiconductor memory device.
FIG. 38 is a diagram illustrating a problem in a conventional semiconductor memory device.
FIG. 39 is a drawing schematically showing another configuration of a conventional semiconductor memory device.
[Explanation of symbols]
1 internal voltage line, F1 to F4 fuse element, SW1 switching element, RD (1,1) to RD (4,16) row decoder, SRD (s, 1) to SRD (s, 16) spare row decoder, 10th 1 program circuit, 12 second program, 2 address buffer, 3 block decoder, 1a, 1b, 1c internal voltage line, SW1a, SW1b switching element, SA sense amplifier, T1P to T4P, T1b-T4b switching element, SW1P, SW2P, SW2b switching element, 100 memory array section, 102 spare array section, 104 row decoder, 106 spare decoder circuit, 108 voltage control circuit, 110 sense amplifier circuit, 122 RAS buffer 124 row address buffer, 126 row address buffer, 125, 127 lines Coder, 128 word line / sense amplifier control circuit, 120 ICC test detector, 140 internal voltage generator, 150 ICC test control circuit, 151 array selector, 153 spare array selector, 220 mode detector, MB1-MB4 memory block , MA11-MA44 memory array, SMA11-SMA44 spare memory array, 300 block decoder, 302 array decoder, 304 spare array ICC test detector, 320 spare test array decoder, 321 program circuit, 318 NAND gate, 314 NAND gate, RWL1- RWL4 redundant word line area, SRWL spare redundant word line area, SND1-SND4 redundant row decode circuit, LP defective row address program circuit, SPD spare word line program Circuit, SSPD spare redundancy program circuit.

Claims (10)

A plurality of memories each including a plurality of memory cells arranged in rows and columns and a plurality of word lines provided corresponding to each of the rows and connected to the memory cells of the corresponding rows respectively An array,
A plurality of memory cells arranged in a matrix of rows and columns, a plurality of memory cells arranged in correspondence with the respective rows, each connected to a corresponding memory cell of the corresponding row, and further including a word line included in each of the memory arrays. At least one spare memory array including the same number of spare word lines, wherein each of the word lines in each of the memory arrays has a defective word line in neither the memory array nor the spare memory array; Uniquely associated with a spare word line of the spare memory array;
A semiconductor memory device comprising: a replacement control circuit for replacing a defective word line with a corresponding spare word line when a defective word line exists in a memory array of the plurality of memory arrays. A plurality of memory cells each arranged in rows and columns, a plurality of word lines arranged corresponding to each row and connected to the memory cells of the corresponding rows, A plurality of memory arrays including at least one redundant word line to which cells are connected;
A plurality of memory cells arranged in a matrix of rows and columns, a plurality of memory cells arranged in correspondence with each of the rows, each connected to a memory cell of a corresponding row, and further including a word line included in each of the memory arrays. And at least one spare memory array including the same number of spare word lines, wherein each of the word lines in each of the memory arrays has a defective word line in neither the memory array nor the spare memory array. Uniquely associated with a spare word line of the spare memory array;
A replacement control circuit for replacing the defective word line with a corresponding spare word line when a defective word line is present in a memory array of the plurality of memory arrays;
When said plurality of defective word lines in the memory array certain of the memory array is present, and a redundancy replacement circuit for replacing the redundant word line in the memory array with the the the defective word line, the semiconductor memory device. The replacement control circuit,
A plurality of spare row decoders provided corresponding to the respective spare word lines, for decoding a given row address signal and generating a spare word line drive signal on the corresponding spare word line according to the decoding result;
A plurality of row decoders provided for each of the plurality of word lines in each of the memory arrays, for decoding a given row address signal, and for generating a word line drive signal on the corresponding word line in accordance with the decoding result; With
2. The semiconductor memory device according to claim 1, wherein each of said plurality of row decoders has the same logic gate connection arrangement as each of said plurality of spare row decoders. Further, when a defective memory array is present among the plurality of memory arrays, the defective memory array is separated from an internal voltage transmitting means for transmitting a predetermined internal voltage, and the internal voltage transmitting line is connected to the spare memory array. 4. The semiconductor memory device according to claim 1, further comprising a voltage supply control unit. When only the defective word line that can be remedied by replacement is found in any of the plurality of memory arrays, a voltage control element for supplying a predetermined internal voltage to each of the plurality of memory arrays is further provided. The semiconductor memory device according to claim 1. A standby means for generating a standby current test mode instruction signal;
An address determination circuit for generating an array instruction signal for designating a memory array and inhibiting generation of a row address signal in response to the standby current test mode instruction signal;
6. The connection control circuit according to claim 1, further comprising a connection control circuit that supplies a predetermined internal voltage to a memory array specified by the array instruction signal in response to the standby current mode instruction signal and the array instruction signal. Semiconductor storage device. Further, a row selecting means for generating a row specifying signal in accordance with a row address signal specifying a row in each of the plurality of memory arrays, an array selecting means for generating an array specifying signal in accordance with the array address signal, and activation of a standby current test mode instruction signal 2. The semiconductor memory device according to claim 1, further comprising selection control means for enabling array selection means and disabling row selection means in response to the activation. Means for generating a spare array instruction signal for designating the spare memory array;
In response to the standby current test mode instruction signal and the spare array instruction signal, a predetermined internal voltage is applied to the spare array specified by the spare array instruction signal while prohibiting application of a predetermined internal voltage to the plurality of memory arrays. 7. The semiconductor memory device according to claim 6, further comprising: means for supplying a voltage. 9. The memory according to claim 1, wherein a plurality of memory blocks each including the plurality of memory arrays and the at least one spare array are provided, and the replacement control circuit is provided corresponding to each of the memory blocks. 13. The semiconductor memory device according to claim 1. A plurality of memory arrays each having a plurality of memory cells arranged in rows and columns, at least one spare memory array having the same number of rows and columns of memory cells as the respective memory arrays, and an internal voltage A method for testing a semiconductor memory device comprising:
Separating an array other than the array designated by the array designating signal from the internal voltage transmission line according to the array designating signal, and performing a standby current test on the array designated by the array designating signal;
Performing a standby current test on the spare array by connecting only the spare array to the internal voltage line when the memory array is determined to be defective because the standby current is larger than a predetermined value in the standby current test;
When the standby current test is performed on all of the plurality of memory arrays, performing a functional test to determine whether or not a defective row exists in any of the plurality of memory arrays;
Replacing the row in the spare array with the defective row when the defective row can be replaced with a row in the spare array.

Images