JP4766961B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having redundant rows and columns accessible before replacement.

  A redundancy technique is known as a technique for improving the manufacturing yield of a semiconductor memory device. This redundancy technology is to program a specific address into a redundancy circuit by fusing a polycrystalline polysilicon fuse element formed on a semiconductor chip with a laser beam, etc., thereby replacing a normal memory cell with a redundancy memory cell. It is.

  However, with the recent high integration, there is a problem that the manufactured semiconductor memory device cannot be remedied as a non-defective product because a defect exists in the redundant memory cell to be replaced. . As a method for solving such a problem, for example, Japanese Patent Publication No. 4-68719 discloses an example of a semiconductor memory device in which a spare memory cell can be inspected in advance prior to a repair process.

FIG. 31 is a block diagram showing a configuration of the semiconductor memory device disclosed in the above publication. Referring to FIG. 31, this semiconductor memory device is responsive to a main memory 1 including a plurality of memory cells, a row decoder 3 for selecting one of word lines WL in response to a row address AR, and a column address AC. A column decoder 5 for selecting one of the bit lines BL, a sense amplifier 6 for amplifying data read from the main body memory 1, and an output buffer 7 are provided. This semiconductor memory device further selects spare memory 2 including a plurality of spare memory cells and one of spare memory word lines SWL in response to spare row enable signals SPE1 to SPE4 or test signals TEST1 'to TEST4'. A spare decoder 40 and a defective address detection circuit 80 that generates the spare row enable signals SPE1 to SPE4 when the replacement address is programmable and the row address AR matches the programmed replacement address.

  In normal operation, the row decoder 3 selects one of the word lines WL in response to a row address AR given from the outside. As a result, data is read onto the bit line BL from the memory cell connected to the word line. Next, in response to a column address AC given from the outside, the column decoder 5 selects one of the bit lines BL. As a result, the data on the bit line is amplified by the sense amplifier 6 and further output to the outside via the output buffer 7. In such normal operation, the defective address detection circuit 80 is in an inactive state, and the spare decoder 40 is also in an inactive state. Therefore, spare memory word line SWL is in a non-selected state.

  On the other hand, in the access operation of the spare memory cell, the address of the defective memory cell is programmed in advance in the basic circuit 81 including the fuse element. When such a defective address is detected, the spare row enable signals SPE1 to SPE4 from the basic circuit 81 become H level, and thereby the spare decoder 40 is activated. At the same time, the row decoder 3 is inactivated. The activated spare decoder 40 selects one of the spare memory word lines SWL. As a result, data is read onto bit line BL from the spare memory cell connected to spare memory word line SWL. Next, as in the normal operation, the column decoder 5 selects one of the bit lines BL in response to a column address AC given from the outside, and the data on the selected bit line BL is amplified by the sense amplifier 6. Further, it is output to the outside via the output buffer 7.

Next, an inspection method of the spare memory 2 by this semiconductor memory device will be described. FIG. 32 shows a test mode detection circuit used in this semiconductor memory device. The test mode detection circuit includes an input pad PD to which an address signal is applied, an inverter 36 that inverts the signal applied to the input pad PD and supplies the inverted signal to an internal address buffer , and an inverter 37 for generating an internal test signal. . The inverter 37 includes a load P-channel MOS transistor 38 and a drive N-channel field transistor 39. The threshold voltage of N channel field transistor 39 is set to a value (about 9 V) higher than power supply voltage Vcc.

  FIG. 33 shows a test signal decoder circuit for generating internal test signals TEST1 'to TEST4' in response to internal test signal TEST and complementary signals A0, / A0, A1, and / A1 of the row address signal. Four spare memory word lines SWL1 to SWL4 are selectively driven in accordance with such a combination of four complementary signals A0, / A0, A1, and / A1.

  FIG. 34 shows a configuration of the basic circuit 81 in FIG. The basic circuit 81 includes a plurality of N channel MOS transistors 12 to 16 connected in parallel to each other, a plurality of fuse elements 18 to 22 connected in series with the corresponding N channel MOS transistors, and the fuse elements 18. To P-channel MOS transistor 17 connected in common.

  In the test operation of the spare memory, a voltage (for example, 10 V) higher than the threshold voltage of N channel field transistor 39 is applied to input pad PD. As a result, the output signal (internal test signal / TEST) of the inverter 37 becomes a low potential. Inverted signal TEST is applied to the test signal decoder circuit, whereby one of test signals TEST1 'to TEST4' is activated in response to address signals A0 and A1.

For example, when (A0, A1) = (1, 1), the test signal TEST1 ′ is at the H level, and the other test signals TEST2 ′ to TEST4 ′ are maintained at the L level. Therefore, one spare memory word line SWL1 is selected in response to such internal test signals TEST1 'to TEST4'. In response to the internal test signals TEST1 'to TEST4', the normal row decoder 3 is inactivated. The subsequent operation is the same as when a spare memory cell is accessed. Therefore, according to such a semiconductor memory device, a spare memory cell can be tested without fusing the fuse element.
Japanese Examined Patent Publication No. 4-68719

  However, since the conventional semiconductor memory device described above requires one internal test signal for one OR gate 41 for selecting one spare memory word line, a large number of signal lines are required. Therefore, since a wide area is required for the signal line, there is a problem that the chip size is increased.

  Further, there is a problem that the size of the NOR gate 82 to which the spare row enable signals SPE1 to SPE4 and the internal test signals TEST1 ′ to TEST4 ′ are applied increases. Even if the NOR gate 82 is divided, the number of logic gates increases as the number of spare memory cells to be selected increases, so that there is still a problem that the chip size increases.

  In recent highly integrated semiconductor memory devices (for example, 16 Mbit dynamic RAM), a large number of spare memory cells are arranged not only in the row direction but also in the column direction. You cannot simply access both rows and columns in advance.

  In particular, if spare memory cells are provided in both row and column directions, it is necessary to test spare memory cells located at the intersection of the redundant row and redundant column in order to replace the redundant row and redundant column at the same time. However, such a test cannot be performed in such a configuration.

  In the test mode detection circuit of FIG. 32, a high voltage must be continuously applied to the input pad PD over the entire period during the test mode of the spare memory. For this reason, the input pad PD cannot use an address pin used for selecting a spare memory cell, and must be provided individually for the spare memory cell.

Assuming that the defective address detection circuit 80 described above is arranged in each memory array block in a semiconductor memory device capable of division operation, a function for a spare memory cell also using an address for selecting a memory array block to be operated A test must be done. Therefore, it is necessary to consider the relationship between the address used for block selection and the address for the spare memory cell.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having redundant rows and redundant columns that can be accessed prior to replacement.

  Another object of the present invention is to provide a semiconductor memory device having a mode for testing redundant rows and redundant columns in response to a special combination of control signals.

  Still another object of the present invention is to provide a semiconductor memory device having redundant rows and redundant columns capable of multi-bit testing.

  A semiconductor memory device having a redundant row that can be accessed prior to replacement is realized while suppressing an increase in chip area.

  Still another object of the present invention is to realize a semiconductor memory device having a redundant column accessible prior to replacement while suppressing an increase in chip area.

The semiconductor memory device according to the present invention includes: (a) a plurality of word lines; (b) a plurality of normal bit line pairs arranged to intersect the word lines; and (c) a pair of the word lines and the normal bit line pairs. A plurality of normal memory cells arranged corresponding to the intersection; (d) a plurality of normal column selection gate pairs provided corresponding to the normal bit line pairs, each connected to a corresponding normal bit line pair; e) first and second redundant bit line pairs arranged crossing the word line, and (f) arranged corresponding to the intersection of the word line and the first and second redundant bit line pairs. A plurality of redundant memory cells; (g) a first redundant column selection gate pair connected to the first redundant bit line pair; and (h) a second redundant bit connected to the second redundant bit line pair. A plurality of blocks each including a redundant column selection gate pair, the plurality of blocks A plurality of normal column selection lines provided corresponding to the normal column selection gate pairs, each connected to the respective control electrodes of the normal column selection gate pairs in the corresponding plurality of blocks, the first redundancy in the plurality of blocks A first redundant column selection line connected to each control electrode of the column selection gate pair, and a second redundant column selection line connected to each control electrode of the second redundant column selection gate pair in the plurality of blocks Normal column selecting means for selecting one of the normal column selection lines in response to a column address signal supplied from the outside, and a column address signal supplied from the outside with a programmable first column replacement address. First program means for generating a first coincidence signal when it coincides with one column replacement address, and a first redundant column in response to a first coincidence signal provided from the first program means A first detecting means for generating a sexifying signal; a second for generating a second match signal when the second column replacement address is programmable and the column address signal matches the second column replacement address; Program means, second detection means for generating a second redundant column activation signal in response to a second coincidence signal provided from the second program means, and responding to the first redundant column activation signal Redundant column selection means for selecting the first redundant column selection line and selecting the second redundant column selection line in response to the second redundant column activation signal, and the first and second Deactivating means for deactivating the normal column selecting means in response to one of the coincidence signals, and the first program means includes the first bit line pair of the plurality of blocks for the first bit line pair. Can be replaced with redundant bit line pairs The second program means can replace any of the normal bit line pairs of the plurality of blocks with the second redundant bit line pair, and the first program means can be used together with the first column replacement address. A part of the first row replacement address is programmable, the column address signal matches the first column replacement address, and a part of the row address signal supplied from the outside is the first row replacement address. The first match signal is generated when a part of the second row replacement address is programmable together with the second column replacement address, and the second column replacement address is programmable. address signal coincides with the second column replacement addresses, and that occur with the second coincidence signal when a portion of the row address signal coincides with the portion of the second row replacement address .

  The semiconductor memory device has three test modes. In the first test mode, the normal row selection unit is deactivated and the redundant row selection unit is activated in response to the row test signal, so that the redundant row memory cell can be accessed prior to replacement. . In the second test mode, the normal column selecting means is inactivated and the redundant column selecting means is activated in response to the column test signal, so that the redundant column memory cell can be accessed prior to replacement. . In the third test mode, the normal row selection unit is deactivated in response to the row test signal, the redundant row selection unit is activated, and the normal column selection unit is deactivated in response to the column test signal. At the same time, the redundant column selection means is activated, so that the redundant matrix memory cells can be accessed prior to replacement.

  Preferably, the semiconductor memory device further includes test signal generating means for generating the row test signal and / or the column test signal in response to a control signal applied from the outside in addition to the above configuration.

  In the semiconductor memory device, in addition to the operation of claim 1, a row test signal and a column test signal are responsive to control signals such as a row address strobe signal, a column address strobe signal, a write enable signal, and an address key signal. Since one or both of them are generated internally, it is possible to test the function of redundant rows and columns even in a molded semiconductor memory device.

  More preferably, in addition to the above-described configuration, the semiconductor memory device responds to one row address signal and one column address signal, and a plurality of data from one of the normal memory cells is parallelized. The parallel reading means for reading the data and the data read by the parallel reading means in response to a predetermined multi-bit test signal are detected to match each other. And a match / mismatch detection means for generating a match / mismatch detection signal indicating a first value and a second value different from the first value when one of the data does not match the other data, The test signal generating means further generates the multi-bit test signal in response to a control signal given from the outside.

  In the semiconductor memory device, in addition to the operation of claim 2, a plurality of data are read in parallel in response to one row address signal and one column address signal, and all of the read data is also read. Are detected, it is possible to perform a multi-bit test of redundant rows and columns.

  A semiconductor memory device according to another configuration of the present invention includes a plurality of blocks, a normal word line selection unit, a first program unit, a first detection unit, a first row replacement control unit, a second program unit, and a second program unit. Detection means, second row replacement control means, redundant word line selection means, and inactivation means. Each of the plurality of blocks includes a plurality of normal word lines, a plurality of normal row decoders, first and second redundant word lines, a redundant row decoder, a plurality of bit line pairs, a plurality of normal memory cells, and a plurality of redundancy Includes memory cells. Each of the plurality of normal row decoders is provided corresponding to the first number of normal word lines among the plurality of normal word lines, and is provided corresponding to the corresponding first number of normal word lines. The corresponding first number of normal word lines are selectively driven in response to the number of normal word line driving signals. A second redundant word line provided corresponding to the redundant row decoder and the first and second redundant word lines, driving the first redundant word line in response to a first redundant word line drive signal; The second redundant word line is driven in response to the drive signal. The plurality of bit line pairs are arranged to intersect the plurality of normal word lines and the first and second redundant word lines. The plurality of normal memory cells are arranged corresponding to the intersections of the normal word line and the bit line pair. A plurality of redundant memory cells are arranged corresponding to the intersections of the first and second redundant word lines and the bit line pair. The normal word line selection means supplies the first number of normal word line drive signals to each of the normal row decoders in the plurality of blocks in response to a row address signal given from the outside. The first program means can be programmed with a first row replacement address. The first detection means detects whether or not the row address signal matches the first row replacement address programmed in the first program means, and activates the first redundant row when they match. Generate a signal. The first row replacement control means forces the first detection means to generate the first redundant row activation signal in response to a predetermined row test signal and the row address signal. Control. The second program means can be programmed with a second row replacement address. The second detecting means detects whether or not the row address signal matches the second row replacement address programmed in the second program means, and activates a second redundant row when they match. Generate a signal. The second row replacement control means forcibly controls the second detection means so as to generate the second redundant row activation signal in response to the row test signal and the row address signal. The redundant word line selection means sends the first redundant word line drive signal to each of the redundant row decoders in the plurality of blocks in response to the first redundant row activation signal given from the first detection means. The second redundant word line drive signal is supplied to each of the redundant row decoders in the plurality of blocks in response to the second redundant row activation signal supplied from the second detecting means. The inactivation means inactivates the normal word line selection means in response to one of the first and second redundant row activation signals.

  In the semiconductor memory device, the first or second redundant row activation signal is generated in response to the row test signal and the row address signal, thereby inactivating the normal word line selection means and the first. And the second redundant word line is selectively driven. In this way, redundant rows are integrated into two systems and replaced with normal rows in response to programmed row addresses, so that a large number of signal lines are not required, and an increase in chip area is suppressed.

  A semiconductor memory device according to another configuration of the present invention includes a plurality of blocks, a plurality of normal column selection lines, a first redundant column selection line, a second redundant column selection line, a normal column selection means, a first program means, First detection means, first column replacement control means, second program means, second detection means, second column replacement control means, redundant column selection means, and inactivation means are provided. Each of the plurality of blocks includes a plurality of word lines, a plurality of normal bit line pairs, a plurality of normal memory cells, a plurality of normal column selection gate pairs, first and second redundant bit line pairs, and a plurality of redundant memory cells. , A first redundant column selection gate pair, and a second redundant column selection gate pair. The plurality of normal bit line pairs are arranged to cross the word line. The plurality of normal memory cells are arranged corresponding to the intersections of the word line and the normal bit line pair. The plurality of normal column selection gate pairs are provided corresponding to the normal bit line pairs. Each normal column selection gate pair is connected to a corresponding normal bit line pair. The first and second redundant bit line pairs are arranged to cross the word line. The plurality of redundant memory cells are arranged corresponding to the intersections of the word lines and the first and second redundant bit line pairs. The first redundant column selection gate pair is connected to the first redundant bit line pair. The second redundant column selection gate pair is connected to the second redundant bit line pair. The plurality of normal column selection lines are provided corresponding to the plurality of normal column selection gate pairs. Each of the normal column selection lines is connected to each control electrode of the normal column selection gate pair in the corresponding plurality of blocks. The first redundant column selection line is connected to each control electrode of the first redundant column selection gate pair in the plurality of blocks. The second redundant column selection line is connected to each control electrode of the second redundant column selection gate pair in the plurality of blocks. The normal column selection means selects one of the normal column selection lines in response to a column address signal given from the outside. The first column means can be programmed with a first column replacement address. The first program means generates a first coincidence signal when an externally applied column address signal coincides with the first column replacement address. The first detecting means generates a first redundant column activation signal in response to a first coincidence signal supplied from the first program means. The first column replacement control means forces the first detection means to generate the first redundant column activation signal in response to a predetermined column test signal and the column address signal. Control. The second column means can be programmed with a second column replacement address. The second program means generates a second coincidence signal when the column address signal coincides with the second column replacement address. The second detection means generates a second redundant column activation signal in response to the second coincidence signal supplied from the second program means. The second column replacement control means forcibly controls the second detection means to generate the second redundant column activation signal in response to the column test signal and the column address signal. The redundant column selection means selects the first redundant column selection line in response to the first redundant column activation signal given from the first detection means, and the second detection means given from the second detection means. The second redundant column selection line is selected in response to the second redundant column activation signal. The activating means deactivates the normal column selecting means in response to any of the first and second coincidence signals and the column test signal.

  In the semiconductor memory device, the first or second redundant column activation signal is generated in response to the column test signal and the column address signal, thereby inactivating the normal column selection unit and the first or second column activation signal. The second redundant column selection line is selected. In this way, redundant columns are integrated into two systems and replaced with normal columns in response to programmed column addresses, so that a large number of signal lines are not required, and an increase in chip area is suppressed.

  A semiconductor memory device according to another configuration of the present invention includes a plurality of blocks, normal word line selection means, switching pads, first program means, first detection means, first row replacement control means, and second program means. , Second detection means, second row replacement control means, redundant word line selection means, and inactivation means. Each of the plurality of blocks is configured in the same manner as in the fourth aspect. The normal word line selection means, the first program means, the first detection means, the second program means, the second detection means, the redundant word line selection means, and the activation means are also the same as in the fourth aspect. It has a function. However, the first row replacement control means generates the first redundant row activation signal in response to a predetermined row test signal and the first potential of the switching pad. The detection means is forcibly controlled. The second row replacement control means generates the second redundant row activation signal in response to the row test signal and a second potential different from the first potential of the switching pad. The detection means is forcibly controlled.

  In the semiconductor memory device, the first or second redundant row activation signal is generated in response to the row test signal and the potential of the switching pad, thereby inactivating the normal word line selection means and the first. The first and second redundant word lines are selectively driven. Therefore, an increase in chip area can be suppressed, and a redundant row can be replaced with a normal row by the switching pad.

  A semiconductor memory device according to another configuration of the present invention includes a plurality of blocks, a plurality of normal column selection lines, a first redundant column selection line, a second redundant column selection line, a normal column selection means, a switching pad, a first pad Program means, first detection means, first column replacement control means, second program means, second detection means, second column replacement control means, redundant column selection means, and inactivation means are provided. Each of the blocks is configured in the same manner as in the fifth aspect. The plurality of normal column selection lines, the first redundant column selection line, the second redundant column selection line, the normal column selection means, the first program means, the first detection means, the second program means, and the second detection The means, the redundant column selection means, and the inactivation means have the same functions as in the fifth aspect. However, the first column replacement control means generates the first redundant column activation signal in response to a predetermined column test signal and the first potential of the switching pad. The detection means is forcibly controlled. The second column replacement control means generates the second redundant column activation signal in response to the column test signal and a second potential different from the first potential of the switching pad. The two detection means are forcibly controlled.

  In the semiconductor memory device, the first or second redundant column activation signal is generated in response to the column test signal and the potential of the switching pad, thereby inactivating the normal column selection means and the first. The first or second redundant column selection line is selected. Therefore, an increase in the chip area can be suppressed, and the redundant column can be replaced with the normal column by the switching pad.

  According to the semiconductor memory device of the present invention, the redundant row selection means is activated in response to a predetermined row test signal, and the redundant column selection means is activated in response to a predetermined column test signal. Therefore, it is possible to perform a pass / fail judgment test for a redundant row before replacing a normal row with a defect with a redundant row, and before replacing a normal column with a defect with a redundant column, A pass / fail judgment test can be performed. Therefore, by replacing the normal row with the redundant row or the normal column with the redundant column, the semiconductor memory device can be reliably relieved, so that the manufacturing yield can be further improved.

  Further, one or both of the row test signal and the column test signal are internally generated in response to an externally applied control signal. Therefore, even after the semiconductor memory device is packaged by a resin mold, a redundant row is generated. In addition, it is possible to perform a pass / fail judgment test for redundant columns.

  Further, since the multi-bit test can be performed on the data read from the redundant row and the redundant column, the time required for the quality determination test as described above is shortened.

  According to the semiconductor memory device of the present invention, since the first and second redundant word lines are selectively driven in response to a predetermined row test signal and row address signal, the normal word line is made redundant. A pass / fail judgment test of the redundant word line can be performed before replacement with the word line. In addition, since the plurality of redundant word lines are integrated into two systems and the plurality of redundant word lines are not individually driven, the chip area is not increased by the signal lines for driving the redundant word lines during the test.

  Further, according to the semiconductor memory device of the present invention, the first and second redundant column selection lines are selectively driven in response to a predetermined column test signal and column address signal. Before the line pair is replaced with the redundant bit line pair, a pass / fail judgment test of the redundant bit line pair can be performed. In addition, since signals for selecting a plurality of redundant bit line pairs are concentrated in two systems, the chip area is not increased by the signal lines for that purpose.

  Alternatively, according to the semiconductor memory device of the present invention, the first and second redundant word lines are selectively driven in response to a predetermined row test signal and the potential of the switching pad. Prior to replacing a line with a redundant word line, a pass / fail judgment test of the redundant word line can be performed. In addition, the selection of a plurality of redundant word lines is integrated into two systems, and the two systems can be selected by controlling the voltage of the switching pad by applying an external address signal. An increase in the chip area is suppressed, and a pass / fail discrimination test is further facilitated.

  According to the semiconductor memory device of the present invention, the first and second redundant column selection lines are selectively driven in response to a predetermined column test signal and the potential of the switching pad. Before the bit line pair is replaced with the redundant bit line pair, a pass / fail judgment test of the redundant bit line pair can be performed. In addition, since a plurality of redundant bit line pairs are integrated into two systems and are switched to two systems by controlling the voltage of the switching pad, an increase in chip area due to signal lines for driving the redundant bit line pairs is suppressed. And such a quality determination test is further facilitated.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
(1) Overall configuration of semiconductor memory device (FIG. 1)
1 is a block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention. Referring to FIG. 1, this semiconductor memory device includes a normal memory cell array (hereinafter simply referred to as “memory cell array”) including a plurality of normal memory cells (hereinafter simply referred to as “normal memory cells”). (Referred to as “normal memory cell array”), a redundant row memory cell array 101 including a plurality of redundant row memory cells, a redundant column memory cell array 102 including a plurality of redundant column memory cells, and a plurality of redundant column row memories. A redundant column row memory cell array 103 including cells. A plurality of normal word lines (hereinafter simply referred to as “normal word lines” WL0 to WLn) WL0 to WLn are arranged across the memory cell array 100 and the redundant column memory cell array 102. A plurality of redundant word lines SWL0 to SWLm are arranged across the column row memory cell array 103. On the other hand, a plurality of column select lines CSL0 to CSLj are arranged across the memory cell array 100 and the redundant row memory cell array 101, and a plurality of redundant column select lines SCSL0 to SCSLi are arranged across the redundant column memory cell array 102 and the redundant column row memory cell array 103. Yes.

  The semiconductor memory device further includes a sense refresh amplifier input / output control circuit 104 that amplifies data read from the memory cell array 100 and the redundant row memory cell array 101 and controls input / output of data, and a redundant column memory cell array 102 and redundant column. A redundant sense refresh amplifier input / output control circuit 105 that amplifies data read from the row memory cell array 103 and controls data input / output is provided.

  This semiconductor memory device further includes a row decoder 106 for selecting one of word lines WL0 to WLn in response to internal row address signals RA0 to RAp and complementary signals / RA0 to / RAp, and word lines WL0 to WL0. A redundant row decoder 107 is provided to select one of the redundant word lines SWL0 to SWLm when a defect exists in any of WLn or when the function of the redundant row is tested.

  This semiconductor memory device further includes a column decoder 108 for selecting one of column selection lines CSL0-CSLj in response to internal column address signals CA0-CAq and its complementary signals / CA0- / CAq, and a column selection line A redundant column decoder 109 is provided for selecting one of the redundant column selection lines SCSL0 to SCSLi when a defect exists in any of CSL0 to CSLj or when the function of the redundant column is tested.

  The semiconductor memory device further supplies internal row address signals RA0 to RAp, / RA0 to / RAp to row decoder 106 and redundant row decoder 107 in response to externally applied address signals A0 to Ap, and also to an internal column. A row and column address buffer 110 that supplies address signals CA0 to CAq, / CA0 to / CAq to column decoder 108 and redundant column decoder 109, and various responses in response to row address strobe signal / RAS and column address strobe signal / CAS A clock generation circuit 111 for generating an internal control signal, a logic gate 117 for receiving a write enable signal / WE, and data DQ0 to DQr externally applied in response to an output signal of the logic gate 117 are input to a sense refresh amplifier. Output control Input buffer 114 supplied to path 104 and redundant sense refresh amplifier input / output control circuit 105, and sense refresh amplifier input / output control circuit 104 and redundant sense refresh amplifier in response to the output signal and output enable signal / OE of logic gate 117 An output buffer 115 for outputting data from the input / output control circuit 105 to the outside, and a data degeneration circuit 116 for performing a JEDEC standard multi-bit test are provided.

  As a feature of the present invention, the semiconductor memory device further includes a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, external address signals A1 and A2, and a test address key signal TA3. In response to .about.TA5, test mode control circuit 112 for selectively generating redundant row test activation signal TEST1, redundant column test activation signal / TEST2, and multi-bit test activation signal TMB, and redundant row test activation signal TEST1. In response to redundant column test activation signal / TEST2, auxiliary row address signals RAs1 and RAs2, and auxiliary column address signals CAs1 and CAs2, redundant row decoder activation signals SRF0 and SRF1 and redundant column decoder activation signals SCE0 to SCE0. And a redundant memory control circuit 113 for generating ei. Here, external address signals A 1 and A 2 are directly applied to test mode control circuit 112. The row and column address buffer 110 supplies address key signals TA3 to TA5 for selecting a test mode to the test mode control circuit 112 in response to external address signals A3 to A5 (not shown). Redundant memory control circuit 113 includes a program circuit in which a replacement address can be programmed and its address detection circuit as usual, and in response to auxiliary row address signals RAs1 and RAs2 when a new redundant row test activation signal TEST1 is applied. Redundant row decoder activation signals SRF0 and SRF1 are selectively activated, and redundant column decoder activation signals SCE0 to SCEi in response to auxiliary column address signals CAs1 and CAs2 when redundant column test activation signal / TEST2 is applied. Is selectively activated.

(2) Test mode control circuit (Figure 2)
FIG. 2 is a block diagram showing a configuration of test mode control circuit 112 in FIG. Referring to FIG. 2, test mode control circuit 112 detects predetermined timings of externally applied row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal / WE, and provides a test mode. External clock detection circuit 122 for generating activation signal FE, address key latch control signal FSE, and test mode reset signal / FR, and states of address pins A1 and A2 in response to these signals FE, FSE and / FR A test group detection circuit 120 for detecting and generating special test group signals / TGA and / TGB, an address key latch circuit 121 for latching address key signals TA3 to TA5 in response to signals FSE and / FR, and latched Signals LV3, LV4, HV3, HV4 Address key predecoder 123 to predecode, special test group signals / TGA, / TGB, address key predecode signals H3H4, H3L4, L3H4, L3L4 from address key predecoder 123, and address key latch circuit 121 latched A special test mode clock decoder 128 which decodes signal HV5 and thereby generates redundant row test activation signal TEST1, redundant column test activation signal / TEST2, and multi-bit test activation signal TMB is provided.

  Here, in the test group detection circuit 120, the voltage applied to the address pins A1 and A2 is at the H level, the L level, or the super H level (the super H level is higher than the normal H level). It detects whether it exists, and outputs test group signals / TGA and / TGB. Address key latch circuit 121 detects whether the voltage applied to the address pins corresponding to address key signals TA3 to TA5 is at the H level or the L level. When the voltage is at the H level, the address key latch circuit 121 is at the H level. Address key latch signals HV3 to HV5 are output, and when the voltage is at L level, H level address key latch signals LV3 to LV5 are output. Address key predecoder 123 includes four NOR gates 124 to 127, and outputs address key predecode signals H3H4, H3L4, L3H4, and L3L4 in response to address key latch signals HV3, HV4, LV3, and LV4. For example, predecode signal H3H4 is at H level when address key latch signal HV3 is at H level and address key latch signal HV4 is at H level. Since the address key predecoder 123 uses complementary address key latch signals LV3, HV3 or LV4, HV4, one NOR gate generates one predecode signal.

(2.1) External clock detection circuit (Fig. 3)
FIG. 3 is a circuit diagram showing a configuration of the external clock detection circuit in FIG. The external clock detection circuit 122 includes a WCBR (/ WE, / CAS before / RAS) timing which is a set timing in a multi-bit test mode, and an ROR (/ RAS only refresh) or CBR (/ CAS before / RAS) which is a reset timing. ) Detect refresh timing.

Referring to FIG. 3, external clock detection circuit 122 includes delay circuit 1221a, clocked inverter control circuit 1221b having logic gate 1221ba, inverters 1221bb and 1221bc, WBR (/ WE before / RAS) detection circuit 1221c, Is provided. Delay circuit 1221a outputs delayed signal D / RAS of row address strobe signal / RAS. Clocked inverter control circuit 1221b is the row address strobe signal / RAS is the fall to L level, the H level to want under stood L level with the delay of the delay signal D / RAS is the row address strobe signal / RAS Clocked inverter control signal CLC and its inverted signal / CLC are output. Logic gate 1221ba outputs an H level signal when both row address strobe signal / RAS and delayed signal D / RAS attain an L level. WBR detection circuit 1221c receives write enable signal / WE and clocked inverter control signals CLC and / CLC, write enable signal / WE first goes to L level, and row address strobe signal / RAS goes to L level. Then, the WBR detection signal / WBR which becomes L level is output. The WBR detection circuit 1221c sets the WBR detection signal / WBR to the same logic as the write enable signal / WE when the clocked inverter control signals CLC and / CLC are at the H level and the L level, respectively. When / CLC becomes L level and H level, respectively, the WBR detection signal / WBR at that time is held.

The external clock detecting circuit 122 further includes column address strobe signal / CAS, receives the clocked inverter control signals CLC and / CLC, column address strobe signal / CAS becomes earlier and L level, the row address strobe signal / A CBR detection circuit 1221d that outputs a CBR detection signal / CBR that becomes L level when RAS becomes L level is provided. The CBR detection circuit 1221d includes a clocked inverter 1221da, an inverter 1221db, and a clocked inverter 1221dc. The CBR detection circuit 1221d sets the CBR detection signal / CBR to the same logic as the column address strobe signal / CAS when the clocked inverter control signals CLC and / CLC are at the H level and the L level, respectively. When / CLC becomes L level and H level, respectively, the CBR detection signal / CBR at that time is held.

  The external clock detection circuit 122 further receives a row address strobe signal / RAS, a delay signal D / RAS thereof, a WBR detection signal / WBR and a CBR detection signal / CBR, and outputs a WCBR timing detection signal WCBR, and outputs a WCBR timing detection circuit 1221e. Is provided. This WCBR timing detection circuit 1221e includes a NOR gate 1221ea that outputs an H level signal when the row address strobe signal / RAS and its delay signal D / RAS are both at L level, an inverter 1221eb, a NAND gate 1221ec, and a NOR gate. 1221ed. Therefore, in WCBR timing detection circuit 1221e, WBR detection circuit / WBR and CBR detection signal / CBR are at L level, that is, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are at WCBR timing. When input, delay signal D / RAS is set to H level in response to L level following row address strobe signal / RAS, and is set to L level when row address strobe signal / RAS rises to H level. The WCBR timing detection signal WCBR which is reset to is output.

External clock detection circuit 122 further receives row address strobe signal / RAS, its delay signal D / RAS, column address strobe signal / CAS, WBR detection signal / WBR and CBR detection signal / CBR, and receives reset timing detection signal / RST. Is provided with a reset timing detection circuit 1221f. This reset timing detection signal / RST includes a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE that are input at the CBR refresh timing, so that the WBR detection signal / WBR is at the H level and the CBR detection signal / or CBR becomes L level, or when the row address strobe signal / RAS and column address strobe signal / CAS are input at RO R timing, a row address strobe signal / RAS is a predetermined time period from the rise to the H level L Become a level.

  The reset timing detection circuit 1221f receives a row address strobe signal / RAS, its delay signal D / RAS, a WBR detection signal / WBR and a CBR detection signal / CBR, and outputs a CBR refresh timing detection signal CBRR. 1221 g. The CBR refresh timing detection signal CBRR includes a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable signal / WE inputted at the CBR refresh timing, the WBR detection signal / WBR is at the H level, and the CBR detection signal When / CBR goes to L level, the row address strobe signal / RAS goes to L level and then goes to H level for a predetermined period. The CBR refresh timing detection circuit 1221g includes an inverter 1221ga, a NOR gate 1221gb, an inverter 1221gc, a NOR gate 1221gd, a NOR gate 1221ge, a NOR gate 1221gf, and a NOR gate 1221gg. NOR gates 1221ge and 1221gf form a flip-flop circuit.

  The reset timing detection circuit 1221f further includes an ROR refresh timing detection circuit 1221h and a NOR gate 1221fa. The ROR refresh timing detection circuit 1221h includes an inverter 1221ha, a NAND gate 1221hb, a NOR gate 1221hc, a NOR gate 1221hd, a NOR gate 1221he, an inverter 1221hf, and a NOR gate 1221hg. NOR gates 1221hd and 1221he constitute a flip-flop circuit. ROR refresh timing detection circuit 1221h receives row address strobe signal / RAS, delay signal D / RAS and column address strobe signal / CAS, and outputs ROR timing detection signal ROR. When the row address strobe signal / RAS and the column address strobe signal / CAS are input at the ROR timing, the ROR timing detection signal ROR is at the H level for a predetermined period after the row address strobe signal / RAS rises to the H level. . The NOR gate 1221fa receives the CBR refresh timing detection signal CBRR and the ROR timing detection signal ROR and outputs a reset timing detection signal / RST. This reset timing detection signal / RST is at L level when at least one of CBR refresh timing detection signal CBRR and ROR timing detection signal ROR is at H level.

  The external clock detection circuit 122 further includes a set / reset circuit 1221i that receives the WCBR timing detection signal WCBR and the reset timing detection signal / RST and outputs the timing detection signal TDA. The set / reset circuit 1221i includes an inverter 1221ia, a NAND gate 1221ib, and a NAND gate 1221ic. NAND gates 1221ib and 1221ic constitute a flip-flop circuit. Therefore, when row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at WCBR timing, WCBR timing detection signal WCBR is at H level and reset timing detection signal / RST is at H level. The timing detection signal TDA is set to H level. On the other hand, the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are input at the CBR refresh timing or the ROR timing, and the WCBR timing is detected when the row address strobe signal / RAS rises to the H level. When signal WCBR is at L level and reset timing detection signal / RST is at L level, timing detection signal TDA is reset to L level.

  The external clock detection circuit 122 further includes a timing detection signal latch circuit 1221j that receives the timing detection signal TDA and the clocked inverter control signals CLC and / CLC and outputs the timing detection latch signal LTDA. The timing detection latch circuit 1221j includes a clocked inverter 1221ja, an inverter 1221jb, and a clocked inverter 1221jc. Therefore, when clocked inverter control signals CLC and / CLC are at the H level and L level, respectively, timing detection latch signal LTDA has the same logic as timing detection signal TDA. On the other hand, when clocked inverter control signals CLC and / CLC attain L level and H level, respectively, timing detection latch signal LTDA at that time is held.

  The external clock detection circuit 122 further includes a pulse generation circuit 1221k that receives the row address strobe signal / RAS and outputs a pulse signal / FSEX. The pulse generation circuit 1221k includes a delay circuit 1221ka, an inverter 1221kb, a delay circuit 1221kc, and a NAND gate 1221kb. Therefore, after a predetermined time elapses after row address strobe signal / RAS falls to L level, pulse signal / FSEX falls to L level for a predetermined time.

  External clock detection circuit 122 further receives timing detection signal TDA, timing detection latch signal LTDA and pulse signal / FSEX, and outputs test mode reset signal / FR, address key latch control signal FSE and test mode activation signal FE. A timing detection signal generation circuit 1221m is provided. The timing detection signal generation circuit 1221m includes inverters 1221ma and 1221mb, a NAND gate 1221mc, and inverters 1221md, 1221me, and 1221mf. Therefore, test mode reset signal / FR is an inverted signal of timing detection signal TDA. Address key latch control signal FSE is at H level when timing detection signal TDA is at H level, pulse signal / FSEX is at L level, and timing detection latch signal LTDA is at L level. Test mode activation signal FE has the same logic as timing detection latch signal LTDA.

  FIG. 4 is a timing chart showing the setting operation of the external clock detection circuit 122 at the WCBR timing. FIG. 5 is a timing chart showing the reset operation of the external clock detection circuit 122 at the CBR refresh timing or ROR timing. As shown in FIG. 4, when row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at the WCBR timing, test mode reset signal / FR is set to L level. . On the other hand, as shown in FIG. 5, when these signals / RAS, / CAS and / WE are input at the CBR refresh timing or ROR timing, in response to the rise of row address strobe signal / RAS to the H level, Test mode reset signal / FR is reset to H level.

  As shown in FIG. 4, when these signals / RAS, / CAS and / WE are input at the WCBR timing, the address is changed after a predetermined time has elapsed since the row address strobe signal / RAS fell to the L level. The key latch control signal FSE becomes H level for a predetermined period.

  As shown in FIG. 4, when these signals / RAS, / CAS and / WE are input at the WCBR timing, test mode activation signal FE rises to the H level of row address strobe signal / RAS. In response to H level. On the other hand, as shown in FIG. 5, when these signals / RAS, / CAS and / WE are input at the CBR refresh timing or ROR timing, in response to the rise of row address strobe signal / RAS to the H level, Test mode activation signal FE is at L level.

(2.2) Test group detection circuit (Fig. 6)
FIG. 6 is a block diagram showing a configuration of the test group detection circuit 120 in FIG. Referring to FIG. 6, test group detection circuit 120 includes high voltage detection circuits 130 and 132, row address buffers 131 and 133, and a test group decoder 134. The high voltage detection circuit 130 detects whether or not the voltage of the address pin A1 is higher than the super H level, and outputs the high voltage detection signal SV1F of H level when the voltage is higher than the super H level. The high voltage detection circuit 132 operates in the same manner as the high voltage detection circuit 130. Row address buffer 131 receives address signal A1 and outputs output signal / RA1FA. The row address buffer 133 operates in the same manner as the row address buffer 131. Test group decoder 134 takes in high voltage detection signals SV1F and SV2F when address latch control signal FSE is at H level, and outputs special test group signals / TGA and / TGB.

(2.2.1) High voltage detection circuit (Fig. 7)
FIG. 7 is a circuit diagram showing an example of the high voltage detection circuit 130 in FIG. Referring to FIG. 7, high voltage detection circuit 130 includes n N-channel MOS transistors 1301 and N-channel MOS transistors 1302 that are diode-junctioned. N channel MOS transistor 1301 has a threshold value Vt. Therefore, when a voltage (super H level) higher than power supply voltage Vcc by n × Vt is applied to address pin A1, high voltage detection signal SV1F becomes a normal H level.

(2.2.2) Test group decoder (Fig. 8)
FIG. 8 is a circuit diagram showing a configuration of test group decoder 134 in FIG. Referring to FIG. 8, this test group decoder 134 includes inverters 1341, 1345, 1347, 1353, 1355, clocked inverters 1342, 1343, 1350, 1351, NOR gates 1344 , 1346, 1352 , 1354, AND gate 1348. , 1349 , NAND gates 1356 and 1357. NOR gate 1344 and inverter 1345, NOR gate 1346 and inverter 1347, NOR gate 1352 and inverter 1353, and NOR gate 1354 and inverter 1355 constitute a latch circuit, respectively.

  Clocked inverters 1342, 1343, 1350 and 1351 operate in response to the address latch control signal FSE at the H level. Thus, when the high voltage detection signal SV1F is at H level, the address key latch signal SV1 is at H level, and when the high voltage detection signal SV2F is at H level, the address key latch signal SV2 is at H level. When the output signal / RA1FA of the row address buffer 131 is at H level, the address key latch signal HV1 is at H level, and when the output signal / RA2FA of the row address buffer 133 is at H level, the address key latch signal HV2 is at H level. . Therefore, the three states of the voltage applied to the address pins can be detected by the combination of the address key latch signals SV1, SV2, HV1, and HV2. For example, when address key latch signal SVn (n = 1, 2) is at H level and address key latch signal HVn (n = 1, 2) is at L level, the voltage at the address pin is at super H level. When the address key latch signal SVn is at the L level and the address key latch signal HVn is at the H level, the voltage at the address pin is a normal H level. Further, when address key latch signal SVn is at L level and address key latch signal HVn is at L level, the voltage at the address pin is at L level. Note that address key latch signals SVn and HVn do not simultaneously become H level.

  Special test group signals / TGA and / TGB are generated according to a combination of address key latch signals SVn and HVn. Special test group signal / TGA is at L level when test mode activation signal FE and address key latch signals SV1 and HV2 are all at H level. Special test group signal / TGB is at L level when test mode activation signal FE and address key latch signals SV2 and HV1 are all at H level.

  Therefore, special test group signals / TGA, / TGB are activated when two kinds of voltages are applied to two address pins. If one of the voltages is L level within the normal use range, the special test group signals / TGA and / TGB are not activated even if the other voltage is super H level. Furthermore, when only one type of voltage is applied, special test group signals / TGA, / TGB are not activated at any level. Therefore, even if a high voltage is applied to the address pins by mistake, the semiconductor memory device does not enter the special test mode.

(2.3) Address key latch circuit (Fig. 9)
FIG. 9 is a circuit diagram showing a configuration of address key latch circuit 121 in FIG. Referring to FIG. 9, address key latch circuit 121 includes inverters 1211, 1216, 1218, 1220, 1221 to 1223, clocked inverters 1212 to 1214, and NOR gates 1215, 1217 and 1219. NOR gate 1215 and inverter 1216, NOR gate 1217 and inverter 1218, and NOR gate 1219 and inverter 1220 constitute a latch circuit, respectively.

  Address key latch circuit 121 further includes three row address buffers (not shown) that receive address key signals TA3 to TA5 and output inverted signals / RA3FA to / RA5FA, respectively.

  While the address latch control signal FSE is at the H level, the output signals / RA3FA to / RA5FA of the address buffer are taken in, respectively, whereby the address key latch signals HV3 to HV5 and LV3 to LV5 are latched. These signals continue to be latched until the test mode reset signal / FR becomes H level. Further, the output signal / RAnFA (N = 3, 4, 5) of the row address buffer becomes L level when an H level is applied to the address pin, and becomes H level when an L level is applied to the address pin. Therefore, when the H level is applied to the address pin, the address key latch signal HVn becomes H level and the address key latch signal LVn becomes L level. On the other hand, when L level is applied to the address pin, the address key latch signal HVn becomes L level, and the address key latch signal LVn becomes H level.

(2.4) Special test mode clock decoder (Figure 10)
FIG. 10 is a circuit diagram showing a configuration of special test mode clock decoder 128 in FIG. Referring to FIG. 10, special test mode clock decoder 128 includes a circuit for generating multi-bit test activation signal TMB and a circuit for generating redundant row test activation signal TEST1 and redundant column test activation signal / TEST2. Prepare. This multi-bit test activation signal generating circuit includes inverters 1281, 1284, 1288, 1289, NAND gates 1282 , 1 286, 1287, an AND gate 1285, and a NOR gate 1283. On the other hand, the redundant row and a redundant column test activation signal generating circuit comprises a NOR gate 1290,1291,1292,1293, inverters 1294,12 95 and 1296.

  When address pins A1 and A2 are supplied with L level voltage and super H level within the normal range and signals / RAS, / CAS, / WE are input at WCBR timing, multi-bit test activation signal TMB Is always activated to H level, and this semiconductor memory device does not enter the special test mode. In addition, when evaluating the characteristics of the semiconductor memory device in the special test mode, if the margin evaluation of the semiconductor memory device is performed in the multi-bit test mode, the test time is greatly shortened. Accordingly, in order to enable a multi-bit test even in the special test mode, the multi-bit test mode can be set also by an address key. In this embodiment, when the voltages of the address pins A1, A2 and A5 are super H level, H level and H level, respectively, or when they are H level, super H level and H level, a multi-bit test is possible. Become.

  FIG. 11 is a timing chart showing the set operation of the test mode control circuit in which redundant row activation signal TEST1, redundant column activation signal / TEFT2 and multi-bit test activation signal TMB are all activated by WCBR timing. As shown in FIGS. 11D to 11H, a super H level (indicated by S in FIG. 11) is applied to the address pin A1, and an H level voltage is applied to the address pins A2 to A5, respectively. 11A to 11C, when the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are input at the WCBR timing, as shown in FIGS. The key latch signal SV1 becomes H level, the address key latch signal HV1 becomes L level, the address key latch signal SV2 becomes L level, the address key latch signal HV2 becomes H level, the address key latch signal HV3 becomes H level, and the address The key latch signal LV3 becomes L level, and the address key latch signal H 4 becomes H level, the address key latch signal LV4 becomes L level, the address key latch signal HV5 becomes H level, further address key latch signal LV5 has an L level. As a result, the special test group signal / TGA is ready to be activated.

  These address key latch signals are predecoded by the address key predecoder 123 and further decoded by the special mode clock decoder 128. Then, when test mode activation signal FE rises in response to the rise of row address strobe signal / RAS, special test group signal / TGA becomes active (L level), thereby causing redundant row test activation signal TEST1, redundant test signal RED. Column test activation signal / TEST2 and multi-bit test activation signal TMB are sequentially activated.

  FIG. 12 shows the reset operation of the test mode control circuit in which redundant row test activation signal TEST1, redundant column test activation signal / TEST2, and multi-bit test activation signal TMB are all inactivated by ROR or CBR refresh timing. It is a timing chart. As shown in FIGS. 12A to 12C, the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are input at the ROR or CBR refresh timing, and then the row address strobe signal. When / RAS rises, test mode reset signal / FR becomes H level as shown in FIG. When test mode reset signal / FR goes to H level, all address key latch signals go to L level, so test mode activation signal FE also goes to L level as shown in FIG. Therefore, as shown in FIGS. 12F to 12H, all of redundant row test activation signal TEST1, redundant column test activation signal / TEST2, and multi-bit test activation signal TMB are inactivated.

  To summarize the above description, the decoding table of the test mode control circuit 112 is as shown in Table 1 below. In Table 1, S indicates a super H level, H indicates a normal H (logic high) level, and L indicates an L (logic low) level.

  In this embodiment, the special test mode that can be set by the special test group signal / TGB is only the multi-bit test mode. However, other special test modes may be set. Needless to say, any combination of address keys can be set.

(3) Memory cell array and its peripheral circuits (FIGS. 13 and 14)
FIG. 13 is a block diagram showing in detail the configuration of memory cell arrays 100 to 103 and their peripheral circuits in FIG. Referring to FIG. 13, memory cell array 100 and redundant row memory cell array 101 in FIG. 1 are divided into 16 memory cell array blocks MCA1 to MCA16. The redundant column memory cell array 102 and the redundant column row memory cell array 103 in FIG. 1 are divided into 16 redundant column memory cell array blocks SMCA1 to SMCA16. The sense refresh amplifier input / output control circuit 104 in FIG. 1 is divided into 17 sense refresh amplifier input / output control circuit blocks SA1A to SA17A. The redundant sense refresh amplifier input / output control circuit 105 in FIG. 1 is divided into 17 redundant sense refresh amplifier input / output control circuit blocks SSA1A to SSA17A.

  The row decoder 106 in FIG. 1 includes 16 row decoders RDC1 to RDC16 and 16 level conversion circuits LC1 to LC16. The redundant row decoder 107 in FIG. 1 includes 16 redundant row decoders SRDC1 to SRDC16 and 16 redundant level conversion circuits SLC1 to SLC16. Row decoders RDC1 to RDC16 and redundant row decoders SRDC1 to SRDC16 are arranged corresponding to memory cell arrays MCA1 to MCA16. Each of row decoders RDC1 to RDC16 is connected to four normal word lines WLi, and drives one of the four normal word lines in response to word line drive signals RX0 to RX3. Each of redundant row decoders SRDC1 to SRDC16 is connected to two redundant word lines SWLj, and drives one of the two redundant word lines in response to redundant word line drive signals SRX0 and SRX1.

  Each of level conversion circuits LC1-LC16 converts word line drive signals RXF0-RXF3 at the power supply voltage level into word line drive signals RX0-RX3 at the boosted voltage level, and supplies them to the corresponding row decoder. Each of redundancy level conversion circuits SLC1-SLC16 converts redundant word line drive signals SRF0 and SRF1 at the power supply voltage level into redundant word line drive signals SRX0 and SRX1 at the boosted voltage level, and supplies them to the corresponding redundant row decoder. .

  The word line drive signals RXF0 to RXF3 are generated by the RX decoder 142 shown in FIG. The redundant word line drive signals SRF0 and SRF1 are generated by the redundant RX decoder 143 shown in FIG. RX decoder 142 is activated in response to RX decoder activation signal / RXT, thereby generating one word line drive signal according to complementary row address signals RAD0, / RAD0 and RAD1, / RAD1. Here, RC decoder activation signal / RXT is generated by delaying row address strobe signal / RAS. Redundant RX decoder 143 generates one redundant word line drive signal in accordance with redundant row address detection signals SRA and SRB.

  The column decoder 108 in FIG. 1 includes the Y upper predecoder 140, the Y lower predecoder 141, and the column decoder CDC shown in FIG. The Y lower predecoder 141 generates predecode signals Y4 to Y15 by predecoding complementary column address signals CDA2, / CDA2 to CAD6, / CAD6. Y upper predecoder 140 is activated in response to column decoder activation signal CDE and normal column activation signals NCEA and NCEB, and further predecodes complementary column address signals CAD7, / CAD7 and CAD8, / CAD8. Predecode signals Y16 to Y23 are generated. The column decoder CDC activates any one of the column selection lines CSLi in response to these predecode signals Y4 to Y23.

  Redundant column decoder SCDC is connected to four redundant column selection lines SCSLA, SSCLB, SCSLC and SCSLD, and activates two redundant column selection lines in response to four redundant column activation signals SCEA, SCEB, SCEC and SCED. . Here, since redundant column activation signals SCEA and SCEC simultaneously become H level, corresponding redundant column selection lines SCSLA and SCSLC are simultaneously activated. Redundant column activation signals SCEB and SCED are simultaneously at the H level, and corresponding redundant column selection lines SSCLB and SCSLD are simultaneously activated.

  FIG. 14 is a wiring diagram showing one of the blocks MCA1, SMCA1, SA1A, SSA1A to MCA16, SMCA16, SA17A, and SSA17A in FIG. Referring to FIG. 14, a plurality of bit line pairs BL, / BL are arranged crossing a plurality of word lines WL0 to WL8 and four redundant word lines SWL0 to SWL3.

  A plurality of normal memory cells MC are arranged corresponding to the intersections of the normal bit line pair BL, / BL and the normal word lines WL0 to WL8. Normally, the memory cell MC is represented by a circle without hatching. A plurality of redundant row memory cells RMC are arranged corresponding to the intersections between the normal bit line pair BL, / BL and the redundant word lines SWL0 to SWL3. The redundant row memory cell RMC is represented by a circle hatched in the horizontal direction. A plurality of redundant column memory cells CMC are arranged corresponding to the intersections between the redundant bit line pair BL / BL and the normal word lines WL0 to WL8. The redundant column memory cell CMC is represented by a circle hatched in the vertical direction. Further, a plurality of redundant row column memory cells RCMC are arranged corresponding to the intersections between the redundant bit line pair BL, / BL and the redundant word lines SWL0 to SWL3. The redundant row column memory cell RCMC is represented by a circle hatched in the horizontal and vertical directions.

  A plurality of normal sense refresh amplifiers SA0-SA3 are arranged corresponding to the plurality of normal bit line pairs BL, / BL. A plurality of redundant sense refresh amplifiers SSA0 to SSA3 are arranged corresponding to the redundant bit line pairs BL and / BL.

  Two local input / output line pairs LIO1, / LIO1 and LIO3, / LIO3 are arranged on one side of such a memory cell array, and two local input / output line pairs LIO0, / LIO0 and LIO2, / LIO2 are arranged on the other side. Is arranged. Two column select gates CS are arranged corresponding to each of the normal sense refresh amplifiers SA0 to SA3. Two redundant column selection gates CS are arranged corresponding to each of redundant sense refresh amplifiers SSA0 to SSA3.

  One normal column selection line CSL255 is arranged corresponding to the four normal sense refresh amplifiers SA0 to SA3, and one redundant column selection line SCSL1 is arranged corresponding to the four redundant sense refresh amplifiers SSA0 to SSA3. Yes.

  A shape dummy word line dmy is arranged along the word line WL0, and a shape dummy word line dmy is arranged along the redundant word line SWL3.

(4) Row system circuit (4.1) Row decoder (FIG. 15)
FIG. 15 is a circuit diagram showing one configuration of row decoders RDC1 to RDC16 in FIG. Referring to FIG. 15, one row decoder includes four drive circuits 150 connected to corresponding four word lines WL0 to WL3, N channel MOS transistors 152 to 155, 158, and P channel MOS transistor 151, respectively. , 156, 157. Each drive circuit 150 includes N channel MOS transistors 159 to 161. Row decoder precharge signal / RDP is applied to the gate electrode of P channel MOS transistor 151. Block select signal RBS is applied to the gate electrode of N channel MOS transistor 155. X predecode signals XC, XA, and XB are applied to the gate electrodes of N channel MOS transistors 152 to 154, respectively.

  Here, when row decoder precharge signal / RDP becomes L level during the row-related precharge period, node NA is precharged to boosted voltage Vpp level. As a result, all the word lines WL0 to WL3 are inactivated. Next, when the row address strobe signal / RAS goes to L level, the row decoder precharge signal / RDP goes to H level, so that a specific row decoder depends on the combination of the block select signal RBS and the X predecode signals XA to XC. Selected. Then, a corresponding one word line is selected according to the selectively supplied word line activation signals RX0 to RX3. For example, when word line drive signal RX0 is supplied, the voltage of corresponding word line WL0 rises to the boosted voltage Vpp level.

(4.2) Redundant row decoder (FIG. 16)
FIG. 16 is a circuit diagram showing one configuration of redundant row decoders SRDC1 to SRDC16 in FIG. Referring to FIG. 16, one redundant row decoder includes two drive circuits 162 connected to corresponding two redundant word lines SWL0 and SWL1, respectively, N channel MOS transistors 167, 168, 171 and P channel. MOS transistors 166, 169, and 170 are provided. Each drive circuit 162 includes N channel MOS transistors 163 to 165. Here, a signal RADE0 indicating even or odd number is applied to the gate electrode of N channel MOS transistor 167. Redundant row decoders SRDC1 to SRDC16 operate in substantially the same manner as normal decoders RDC1 to RDC16. When a normal word line is selected, redundant word line drive signals SRX0 and SRX1 are both maintained at the L level, so that redundant word lines SWL0 and SWL1 are not activated. However, when a later-described redundant row address detection circuit detects a match between an externally applied row address signal and a programmed replacement address, one of redundant row address detection signals SRA and SRB becomes H level, and RX The decoder 142 is inactivated. Accordingly, the normal word line drive signals RXF0 to RXF3 are all at the L level. On the other hand, when redundant row address detection signal SRA becomes H level, corresponding redundant word line drive signal SRF0 becomes H level, and when redundant row address detection signal SRB becomes H level, corresponding redundant word line drive signal SRF1 becomes H level. It becomes. Therefore, four redundant word lines in the selected memory cell array block are activated two by two in response to signal RADE0.

(4.3) RX decoder and redundant RX decoder (FIG. 17)
FIG. 17 is a circuit diagram showing a configuration of RX decoder 142 and redundant RX decoder 143 in FIG. Referring to FIG. 17, RX decoder 142 includes NAND gates 1421 to 1424, 1429 to 1432, NOR gates 1425 to 1 428, and inverters 1433 to 1436. One input node of NAND gates 1429 to 1432 is connected to NOR gate 1437 receiving redundant row address detection signals SRA and SRB.

  Therefore, RX decoder 142 is activated when redundant row address detection signals SRA and SRB are both at the L level. When RX decoder activation signal / RXT falls to the L level, the word address is applied according to row address signals / RAD0, / RAD1, RAD0, / RAD1, / RAD0, RAD1 and RAD0, RAD1 applied to NAND gates 1421-1424, respectively. Any one of the line drive signals RXF0 to RXF3 is activated to H level.

  The redundant RX decoder 143 includes inverters 1438, 1441, 1442, and NAND gates 1439, 1440. Therefore, when redundant row address detection signal SRA becomes H level, corresponding redundant word line drive signal SRF0 is activated to H level in response to RX decoder activation signal / RXT. Since this H level redundant row address detection signal SRA is also applied to NOR gate 1437, RX decoder 142 is inactivated. On the other hand, when redundant row address detection signal SRB becomes H level, corresponding redundant word line drive signal SRF1 is activated to H level in response to RX decoder activation signal / RXT. Since this H level redundant row address detection signal SRP is also applied to NOR gate 1437, RX decoder 142 is inactivated.

(4.4) Redundant row address program circuit and redundant row address detection circuit (FIGS. 18 to 20)
FIG. 18 is a circuit diagram showing a configuration of a redundant row address program circuit included in redundant memory control circuit 113 of FIG. Referring to FIG. 18, the redundant row address program circuit includes eight program units 180. Each of the program units 180 includes 14 fuse elements 181 commonly connected to a signal line for one link signal, and 14 N-channel MOS transistors each connected in series with the corresponding fuse element 181. 182. Row address signals RAD1, / RAD1 to RAD7, / RAD7 are applied to the gate electrodes of these N channel MOS transistors 182, respectively.

Three N channel MOS transistors 183 or 184, 185 or 186, and 187 or 188 are connected between each link signal line and the ground node. A row address signal / RAD8 is applied to each gate electrode of N channel MOS transistor 183. A row address signal RAD8 is applied to each gate electrode of N channel MOS transistor 184. The row address signal / RAD9 is applied to a gate electrode of the N-channel MOS transistors 185 and 186 corresponding to the link signal L INK0, LINK1. Row address signal / RAD10 is applied to the gate electrodes of N channel MOS transistors 187 and 188 corresponding to link signals LINK0 and LINK1. Row address signal RAD9 is applied to the gate electrodes of N-channel MOS transistors 185 and 186 corresponding to link signals LINK2 and LINK3. Row address signal / RAD10 is applied to the gate electrodes of N channel MOS transistors 187 and 188 corresponding to link signals LINK2 and LINK3. Row address signal / RAD9 is applied to the gate electrodes of N channel MOS transistors 185 and 186 corresponding to link signals LINK4 and LINK5. Row address signal RAD10 is applied to the gate electrodes of N-channel MOS transistors 187 and 188 corresponding to link signals LINK4 and LINK5. Row address signal RAD9 is applied to the gate electrodes of N-channel MOS transistors 185 and 186 corresponding to link signals LINK6 and LINK7. Row address signal RAD10 is applied to the gate electrodes of N-channel MOS transistors 187 and 188 corresponding to link signals LINK6 and LINK7.

  FIG. 19 is a circuit diagram showing a configuration of a first redundant row address detection circuit included in redundant memory control circuit 113 of FIG. This redundant row address detection circuit is provided corresponding to the redundant row address program circuit shown in FIG. Referring to FIG. 19, this redundant row address detection circuit includes two detection units 190. Each of detection units 190 includes P-channel MOS transistors 1901, 1902, an inverter 1903, and a NOR gate 1904. The redundant row address detection circuit further includes a NAND gate 191, inverters 192 and 194, and a NOR gate 193. Row address signals RAD6 and / RAD7 are applied to NAND gate 191 and redundant row test activation signal TEST1 is applied to inverter 192.

  This redundant row address detection circuit further includes a NAND gate 195 that receives the outputs of two NOR gates 1904 and the output of inverter 194. This NAND gate 195 outputs a redundant row address detection signal SRA.

  FIG. 20 is a circuit diagram showing a configuration of a second redundant row address detection circuit included in redundant memory control circuit 113 of FIG. This redundant row address detection circuit is provided corresponding to another redundant row address program circuit included in redundant memory control circuit 113. Referring to FIG. 20, the second redundant row address detection circuit is configured in substantially the same manner as the first redundant row address detection circuit shown in FIG. However, row address signals / RAD6 and RAD7 are applied to NAND gate 191. The NAND gate 195 outputs a redundant row address detection signal SRB.

  The redundant row precharge signal SRPC shown in FIG. 19 and FIG. 20 becomes L level in response to the rise of the row address strobe signal / RAS, whereby the signal lines for all the link signals LINK0 to LINK7 are supplied with the power supply voltage. Precharged to Vcc level. Therefore, redundant row address detection signals SRA and SRB are both at the H level.

  In a state where all of fuse elements 181 shown in FIG. 18 are not blown, that is, in a state where no replacement address is programmed, link signals LINK0 to LINK7 are all set to the L level regardless of which address signal is applied. Become. On the other hand, when the fuse element 181 corresponding to one of the complementary row address signals RAD1, / RAD1 to RAD7, / RAD7 is blown, that is, when the replacement address is programmed, an unprogrammed address is given. When this is done, all the link signals LINK0 to LINK7 are at the L level. However, when the programmed address is given, the link signals LINK0 to LINK7 are maintained at the H level. This is because if the fuse element 181 is blown, the signal line for the link signal is not discharged even if the N-channel MOS transistor 182 corresponding to the fuse element 181 is turned on.

  As described above, when the redundant row test mode is not set (when the redundant row test activation signal TEST1 is at L level), one of the redundant row address detection signals SRA and SRB is activated according to the link signals LINK0 to LINK7. And the other is inactivated. Therefore, when an unprogrammed address signal is applied, one of redundant row address detection signals SRA and SRB becomes L level, and when a programmed address signal is applied, one of redundant row address detection signals SRA and SRB is applied. Is maintained at the H level.

  Next, the operation when the redundant row test mode is set (when the redundant row test activation signal TEST1 is at the H level) will be described. In this case, redundant row address detection signal SRA is activated to H level if both row address signals / RAD7 and RAD6 applied to NAND gate 191 in FIG. 19 are at H level regardless of link signals LINK0 to LINK7. . At this time, since L level row address signals RAD7 and / RAD6 are both applied to NAND gate 191 in FIG. 20, redundant row address detection signal SRB is inactivated to L level.

  On the other hand, if row address signals RAD7 and / RAD6 applied to NAND gate 191 in FIG. 20 are both at H level, redundant row address detection signal SRB is activated to H level. At this time, since L level row address signals / RAD7 and RAD6 are both applied to NAND gate 191 in FIG. 19, redundant row address detection signal SRA is inactivated to L level.

  Here, the complementary row address signals RAD6, / RAD6 and RAD7, / RAD7 used in the program unit 180 are also used for detecting such a redundant row test mode. This is because the address to be programmed becomes unnecessary by forcibly activating the SRB. Therefore, since redundant RX decoder 143 is provided to select redundant row address detection signals SRA and SRB in accordance with the unnecessary address, it is located at the intersection of the redundant row and the redundant column depending on the combination of externally applied addresses. It is possible to perform a functional test on all the redundant row memory cells except the redundant row memory cell.

In this embodiment, the case where two redundant row address detection signals SRA and SRB are used has been described. Here, since seven program row addresses RAD1 to RAD7 are used, they are given from the outside. 2 ^seven redundant row address sense signal can be selectively activated in accordance with the address. However, the configuration using the number of redundant row address detection signals equal to the number of main clocks supplied to the redundant row decoder is optimal. Such a configuration does not require the addition of a new control signal, and also increases the area even for repetitive circuits having the largest layout area constraints, such as row decoders, redundant row decoders, column decoders, and redundant column decoders. Because there is no.

(5) Column circuit (5.1) Y low order predecoder (FIG. 21)
FIG. 21 is a circuit diagram showing a configuration of Y lower predecoder 141 in FIG. Referring to FIG. 21, this Y lower predecoder 141 includes six predecode units 200 and 201. Each of the predecode units 200 includes NAND gates 2001 and 2002 and inverters 2003 to 2008. Each of the predecode units 201 includes NAND gates 2011 and 2012 and inverters 2013 to 2018. Therefore, this Y lower predecoder 141 generates predecode signals Y4 to Y15 in response to complementary column address signals CAD2, / CAD2 to CAD6, / CAD6.

(5.2) Y upper predecoder (FIG. 22)
FIG. 22 is a circuit diagram showing a configuration of Y upper predecoder 140 in FIG. Referring to FIG. 22, this Y upper predecoder 140 includes two predecoding units 202. Each of the predecode units 202 includes NAND gates 2021 to 2024 and 2029 to 2032 and inverters 2025 to 2028 and 2033 to 2036. Both of these predecode units 202 are activated in response to a column decode activation signal CDE obtained by delaying row address strobe signal RAS. One of the predecode units 202 is activated in response to a normal column activation signal NCEA generated when a redundant row address is not detected, and the other predecode unit 202 is responsive to a normal column activation signal NCEB. Activated. Therefore, Y upper predecoder 140 responds to applied complementary column address signals CAD7, / CAD7 to CAD9, / CAD9 when column decode activation signal CDE and normal column activation signals NCEA and NCEB are at the H level. Thus, predecode signals Y16 to Y23 are generated. When a later-described redundant column address detection circuit detects a replacement address programmed in a later-described redundant column address program circuit, the normal column activation signal NCEA or NCEB goes to L level, thereby predecoding signals Y16 to Y19 or Y20 to Y23. Becomes L level.

(5.3) Redundant column address detection circuit and redundant column address program circuit (FIGS. 23 and 24)
FIG. 23 is a circuit diagram showing a configuration of a redundant column address detection circuit included in redundant memory control circuit 113 of FIG. Referring to FIG. 23, the redundant column address detection circuit includes NAND gates 2041, 2042, 2046 to 2051, inverters 2044, 2045, 2052 to 2054, and a NOR gate 2043. In this redundant column address detection circuit, normal column activation is performed in response to defective column address detection signals / SCEA0, / SCEA1, / SCEB0, / SCEB1 and redundant column test activation signal / TEST2 provided from a redundant column address program circuit described later. An NCE signal NCE is generated. Redundant column activation signals in response to defective column address detection signals / SCEA0, / SCEA1, / SCEB0, / SCEB1, complementary column address signals CAD7, / CAD7, CAD8, / CAD8 and redundant column test activation signal / TEST2 SCEA and SCEB are generated.

FIG. 24 is a circuit diagram showing a configuration of a redundant column address program circuit included in redundant memory control circuit 113 of FIG. Referring to FIG. 24, the redundant column address program circuit includes three detection units 206. Each of the detection units 206 includes two program units 207 and a NOR gate 2061. Each program unit includes P channel MOS transistors 2071, 2075, 2079, N channel MOS transistors 2072, 2073, 2076, 2077, and fuse elements 2074, 2078. This redundant column address program circuit further includes P channel MOS transistors 2081, 2091, 2094, 2098, fuse elements 2082, 2085, 2087, 2089, 2097, N channel MOS transistors 2083, 2084, 2086, 2088, 2090, 2095, 2096. Inverters 2092 and 2093, a program unit 207, a NOR gate 2099, and a NAND gate 2100. Redundant column precharge signal / SCPC is applied to the gate electrodes of P channel MOS transistor 2081 and N channel MOS transistor 2084. Addresses to be programmed are composed of complementary column address signals CAD2, / CAD2 to CAD9, / CAD9 and predecode signals X24 to X27 generated in response to complementary row address signals RAD8, / RAD8, RAD9, / RAD9. . This corresponds to dividing the redundant column memory cell connected to one redundant column selection line into four in response to the predecode signals X24 to X27. Since there is a low probability that a defect occurs in the same Y line beyond the memory cell array block sandwiched between the sense refresh amplifier bands, the random Y line is advantageous in improving the yield by the degree of freedom. It is also possible address the failure of the column decoder if blown fuse element 2082,2085,2087,20 89 corresponding to the predecode signal X24~X27 simultaneously. When not in the redundant column test mode, when the replacement address is not programmed or when an address different from the replacement address is given, all the defective column address detection signals / SCE become H level, and the output signal / NAND of the NAND gate 2046 Both TAC and output signal / TBD of NAND gate 2047 attain H level. Therefore, redundant column activation signals SCEA and SCEB are both at L level. At this time, the normal column activation signal NCE is activated with the H level.

  When not in the redundant column test mode (when the redundant column test activation signal / TEST2 is at the H level), the defective column address detection signal / SCE is at the L level when the applied address signal matches the programmed address. . As a result, one of redundant column activation signals SCEA and SCEB is activated to H level.

  Next, the case of redundant column test mode (when redundant column test activation signal / TEST2 is at L level) will be described. In this case, when both column address signals / CAD7 and CAD8 are at H level, output signal / TAC of NAND gate 2046 is at L level, and redundant column activation signal SCEA is thereby activated to H level. On the other hand, when column address signals CAD7 and / CAD8 are both at the H level, output signal / TBD of NAND gate 2047 attains the L level, whereby redundant column activation signal SCEB is activated to the H level. At the same time, the normal column activation signal NCE becomes L level, and the normal column selection line CSLi is thereby unselected.

Here, the reason for using the complementary column addresses CAD7, / CAD7, CAD8, / CAD8 is the same as in the redundant row test mode described above. By forcibly activating redundant column activation signals SCEA and SCEB, the address to be programmed becomes unnecessary. Therefore, by providing a decoding circuit that selects redundant column activation signals SCEA and SCEB according to unnecessary addresses, redundant column memory cells located at the intersections of redundant rows and redundant columns can be obtained only by a combination of externally applied address signals. It is possible to perform a function test on all the redundant column memory cells except for the above. Here, since the memory cell array blocks selected by redundant column activation signals SCEA, SCEB and SCEC, SCED belong to different memory planes, redundant column activation signals SCEA and SCEC are forcibly activated simultaneously. The selected memory cell array block does not compete. Here, the memory plane is switched by column address signal CAD9 or / CAD9 applied to the gate electrodes of P channel MOS transistor 2094 and N channel MOS transistor 2096 shown in FIG. Similarly to redundant column activation signals SCEA and SCEC, there is no problem even if redundant column activation signals SCEB and SCED are simultaneously activated forcibly.

  Thus, when the redundant row test activation signal / TEST2 becomes L level, the normal column activation signal NCE is forcibly set to L level regardless of the defective column address detection signals / SCEA0, / SCEA1, SCEB0, / SCEB1. . When redundant column test activation signal / TEST2 becomes L level, the complementary column address signals CAD7, / CAD7, CAD8, / CAD8 are used regardless of the defective column address detection signals / SCEA0, / SCEA1, / SCEB0, / SCEB1. Redundant column activation signals SCEA and SCEB are selectively activated.

Here, the case where there are four redundant column activation signals SCEA to SCED has been described. However, since seven program addresses CAD2, / CAD2 to CAD8, / CAD8 are used here, according to the address signal given from the outside 2 ⁷ redundant column activation signals can be selected. However, the configuration using the number of column address signals equal to the number of redundant column activation signals given to the redundant column decoder SCDC is optimal. Further, as described above, if there are redundant column activation signals as combinations corresponding to different column planes, assuming that the number of the planes is N, a configuration using 1 / N redundant column activation signals is provided. It becomes possible. If the number of redundant column activation signals is optimized in this way, it is not necessary to add a new control signal, thereby suppressing an increase in the area of the column decoder.

(5.4) Column decoder and redundant column decoder (FIGS. 25 and 26)
FIG. 25 is a circuit diagram showing a configuration of one column decoder. This column decoder includes a NAND gate 210 and an inverter 211. Therefore, the corresponding column selection line CSL is activated in response to the three Y predecode signals Y i , Yj, Yk.

Figure 26 is a circuit diagram showing the configuration of a redundant column decoder SCDC in FIG 3. Referring to FIG. 26, redundant column decoder SCDC includes eight inverters 212 and 213. Therefore, when one of redundant column activation signals SCEA-SCED is activated, a redundant column selection line corresponding to the activated redundant column activation signal is activated among redundant column selection lines SCSLA-SCSLD. The Since redundant row memory cell RMC shown in FIGS. 13 and 14 is replaced with normal memory cell MC in the same memory cell array block, data from any memory cell is input / output through the same local input / output line pair. The Similarly, since redundant column memory cell CMC is also replaced with normal memory cell MC in the same memory cell array block, data from any memory cell is input / output through the same local input / output line pair. Therefore, regardless of the hierarchical structure of the subsequent data, that is, even if these local input / output line pairs are connected to the global input / output lines, all of normal memory cells, redundant memory cells, read systems and write systems are configured. No changes are required. For this reason, even when a multi-bit test, which is a JEDC standard, data can be easily degenerated, three types of redundant memory cell tests (redundant row memory cell test, redundant column memory cell test, The multi-bit test can be applied to any of the redundant row column memory cell tests.

(6) Redundant Memory Cell Functional Test Method Hereinafter, a redundant memory cell functional test method in the die sort test will be described taking a 16M DRAM of 2K refresh cycle in a × 8 bit configuration as an example. Here, the redundant row is controlled by two redundant row address detection signals SRA and SRB, and the redundant column is controlled by four redundant column activation signals SCEA to SCED. Redundant column activation signals SCEA and SCEB and redundant column activation signals SCEC and SCED correspond to different column address spaces. That is, even if the redundant column activation signals SCEA and SCEC are forcibly activated at the same time, these signals control different column address spaces, so that no problem occurs. Similarly, even if the redundant column activation signals SCEB and SCED are forcibly activated at the same time, these signals control different column address spaces, so that no problem occurs. Therefore, it is possible to combine redundant column activation signals SCEA and SCEC and redundant column activation signals SCEB and SCED, thereby integrating redundant columns into two systems.

(6.1) First, a redundant memory cell test method will be described.
(6.1.1) Super H level, H level, H level, L level, and L level are input to address pins A1 to A5 at WCBR timing, respectively, and the redundant row memory test mode is set.

  (6.1.2) Next, the redundant memory cell controlled by the redundant row address detection signal SRA is tested. Here, since addresses other than those used for the program are used, the row address signals RA0, RA8, RA9, RA10 and RA11 are set to L level and the row address signal RA6 is set to H level. Here, all column addresses CA0 to CA9 are used. A functional test is performed using the normal H level and L level in such a limited address space. At this time, if there is a defect in the redundant row memory cell, the defective row address is stored in memory. For example, let this defective address be XA1.

  (6.1.3) Next, the redundant memory cell controlled by the redundant row address detection signal SRB is tested. After the functional test over the entire address space described in (6.1.2) above is completed, the row address signal RA7 is set to H level, the row address signal RA6 is set to L level, and other row addresses RA0, RA8, RA9, A functional test is performed using RA10 and all column addresses CA0 to CA9. If there is a defect at this time, the defective row address is stored in memory. For example, let this defective address be XB1.

  (6.1.4) Reset the redundant row test mode. Input ROR timing or CBR timing.

(6.2) Next, a test method for redundant column memory cells will be described.
(6.2.1) First, the redundant column test mode is set. At the WCBR timing, a super H level, a normal H level, and an L level are input to address pins A1 to A5, respectively. This address key sets the redundant column memory test mode.

  (6.2.2) Next, redundant column memory cells controlled by redundant column activation signals SCEA and SCED are tested. Since addresses other than those used for the program are used, the column address CA8 is set to the H level, the column address CA7 is set to the L level, the column addresses CA0, CA1, and CA9 are used, and all the row addresses RA0 to RA10 are used. . A functional test is performed using the normal H level and L level in such a limited address space. If there is a defect at this time, the defective column address is stored in memory. For example, assume that this defective address is (X25, XAC1).

  (6.2.3) Then, redundant column memory cells controlled by redundant column activation signals SCEB and SCED are tested. After completion of the functional test over the entire address space described in (6.2.2) above, the column address CA8 is set to the L level, the column address CA7 is set to the H level, and the column addresses CA0, CA1, CA9 and all the row addresses are set. A function test is performed using addresses RA0 to RA10. If there is a defect at this time, the defective column address is stored in memory. For example, assume that this defective address is (X26, XBD1).

  (6.2.4) Finally, the redundant column test mode is reset by inputting the ROR timing or the CBR timing.

  (6.3) Next, a method for testing a memory cell located at the intersection of a redundant row and a redundant column will be described.

  (6.3.1) First, the redundant row test mode and the redundant column test mode are set simultaneously. At the WCBR timing, a super H level, a normal H level, a normal H level, a normal H level, and an L level are input to the address pins A1 to A5, respectively. With this address key, the redundant row test mode and the redundant column test mode can be set simultaneously.

  (6.3.2) Test the intersection memory cells controlled by redundant column activation signals SCEA and SCEC among the memory cells controlled by redundant row address detection signal SRA. In this case, the address space used by AND and the selected address (RA8, RA7, CA8, CA7) described in (6.1.2) and (6.2.3) above. The row address RA7 is set to the L level, the row address RA6 is set to the H level, and the row addresses RA0, RA8, RA9, and RA10 are used. The column address CA8 is set to the H level, the column address CA7 is set to the L level, and the column addresses CA0, CA1, and CA9 are used. A functional test is performed using the normal H level and L level in such a limited address space. If there is a defective address at this time, the defective row address and column address are stored in memory. For example, let this defective address be (X * A1, Y * AC1).

  (6.3.3) Next, among the memory cells controlled by the redundant row address detection signal, the intersection memory cells controlled by the redundant column activation signals SCEB and SCED are tested. After the functional test over the entire address space described in (6.3.2) is completed, the row address RA7 is set to L level, the row address RA6 is set to H level, and the row addresses RA0, RA8, RA9, and RA10 are used. At the same time, the column address CA8 is set to the L level, the column address CA7 is set to the H level, and the functional test is performed on all the spaces of the column addresses CA0, CA1, and CA9. If there is a defect at this time, the defective row address and column address are stored in memory. For example, assume that this defective address is (X * A2, Y * BD1).

  (6.3.4) Next, among the memory cells controlled by the redundant row address detection signal SRB, the intersection memory cells controlled by the redundant column activation signals SCEA and SCEC are tested. After completion of the function test for the entire space described in (6.3.3) above, the row address RA7 is set to the H level, the row address RA6 is set to the L level, the row addresses RA0, RA8, RA9, and RA10 are used. The column address CA8 is set to the H level, the column address CA7 is set to the L level, and a function test is performed on the entire space of the column addresses CA0, CA1, and CA9. If there is a defect at this time, the defective row address and column address are stored in memory. For example, let this defective address be (X * B1, Y * AC2).

  (6.3.5) Next, among the memory cells controlled by redundant row address detection signal SRB, the intersection memory cells controlled by redundant column activation signals SCEB and SCED are tested. After the functional test over the entire space described in (6.3.4) is completed, the row address RA7 is set to the H level, the row address RA6 is set to the L level, and the row addresses RA0, RA8, RA9, and RA10 are used. The column address CA8 is set to the L level, the column address CA7 is set to the H level, and the column addresses CA0, CA1, and CA9 are used to perform the function test on all address spaces. If there is a defect at this time, the defective row address and column address are stored in memory. For example, assume that this defective address is (X * B2, Y * BD2).

  (6.3.6) Finally, the redundant row test mode and the redundant column test mode are reset by inputting the ROR timing or the CBR timing.

  (6.3.7) Next, usable redundant rows and redundant columns are determined according to the obtained defective address information.

(6.3.8) Next, a function test is performed in the entire address space of the normal memory cell. If there is a defect at this time, the defective address is designated as an X line defect, Y
The line is defective and the address information is stored in memory. For example, let this X line defect be / X1, / X2, (X25, / Y1), (X26, / Y2).

  (6.3.9) Next, the result of (6.3.8) above is analyzed within the range of usable redundant rows and redundant columns. If the repair is possible, a repair code is output.

  (6.3.10) Next, the laser trimmer is programmed in accordance with the output relief code.

  (6.3.11) Finally, a functional test is performed on all the chips to discriminate between good and defective products.

  (6.3.12) The above-described procedure is an example, and the function test can be performed in the multi-bit test mode. If this multi-bit test mode is used, the test time is shortened, which is very effective. The order of the various test modes may be any order.

(7) Effects of First Embodiment (7.1) The special test mode is set by latching the address key. Since each special test mode activation signal is held using a latch circuit, a logic gate having a larger size is required if it is assembled at the end of the output logic gate (rising and falling speeds are taken into consideration). However, since the latch circuit is used in the closest position to the previous stage, only a small logic gate can be used, and the area can be reduced.

  (7.2) Furthermore, since it is test mode activation signal FE output at the rise of row address strobe signal / RAS that finally outputs the activation signal, special test mode to be activated up to that time Since the output of the main clock signal is prepared, it is difficult to make an erroneous setting.

  (7.3) Since the setting of the JEDEC standard multi-bit test is possible not only by the WCBR but also by the address key input, the composite special test mode with the multi-bit test can be easily realized.

  (7.4) Since the test group signal in the special test mode is activated by two normal H levels, that is, a normal H level and a super H level, the output buffer signal of the device and the address generation circuit when mounted. Misconfiguration due to differences in the levels of other drivers is unlikely.

  (7.5) Since a redundant row test mode and a redundant column test mode are provided, and these two modes can be set simultaneously, it is possible to realize a functional test of the memory cell at the intersection of the redundant row and the redundant column. . Therefore, since the function test of all the redundant memory cells can be performed, the function check of all the memory cells can be performed in advance before the relief process (before the fuse element is blown) during the die sort test. As a result, the yield can be reliably increased.

  (7.6) A redundant row memory cell and a redundant column memory cell exist in a memory cell array block sandwiched between sense refresh amplifier bands, and includes a redundant row decoder, a redundant column decoder, and a redundant sense refresh amplifier band. The cell and the redundant row memory cell exist on the same bit line, the normal memory cell and the redundant column memory cell exist on the same word line, and the memory cell data is input / output through the same local input / output line pair. Therefore, it is possible to easily perform the function test of the redundant memory cell by the multi-bit test.

  (7.7) A redundant row is selected using a redundant word line drive signal and is further consolidated into two systems, and the selection of these two systems is a combination of program address signals that need not be used. Therefore, it is not necessary to use a large number of switching signals. Further, the wiring is not increased.

  (7.8) A redundant column activation signal is used to select a redundant column, and four signals are not assigned to the same memory cell array block, that is, non-conflicting signals are selected simultaneously. Aggregated into two systems. Further, since the selection of the two systems is performed by a combination of program address signals that do not need to be used, it is not necessary to use a large number of switching signals. Further, the wiring is not increased.

  (7.9) Test mode determination, reset, selection, and switching are all performed according to the external signals / RAS, / CAS, / WE and the state of the address pins, so even if it is a molded product, a function test should be performed. Can do. In this case, it is possible to examine the influence of the chip due to subsequent molding or the like by particularly examining the access of the redundant memory cell or examining the redundant memory cell at the end of the memory cell array. Therefore, the manufacturing margin can be improved.

  (7.10) Since clock pins and address pins connected to external pins are used and other pads are not used, the chip area must be increased for pads where the pads are immediately connected to an increase in the chip, such as multi-bit products. It is possible to suppress.

[Embodiment 2]
FIG. 27 is a block diagram showing an overall configuration of a semiconductor memory device according to the second embodiment of the present invention. Unlike Embodiment 1 of FIG. 1, in Embodiment 2, switching voltage PR is applied to external pad 214 instead of address signals RAs1 and RAs2 for selecting redundant word line drive signals SRF0 and SRF1. Yes. Therefore, the two redundant rows are switched according to the voltage PR of the external pad 214. Further, switching voltage PC is applied to external pad 215 instead of address signals CAs1 and CAs2 for selecting redundant column activation signals SCE0 to SCEi. Therefore, the two redundant columns are switched according to the voltage PC of the external pad 215.

  FIG. 28 is a circuit diagram showing a configuration of a redundant row address detection circuit used in place of the redundant row address detection circuit of the first embodiment shown in FIG. Unlike Embodiment 1 of FIG. 19, in Embodiment 2, an external pad 214, a resistor 216 connected between external pad 214 and node PRR, a node to which external power supply voltage EVcc is applied, and node PRR are provided. P channel MOS transistor 217 connected between and NAND gate 218 receiving node PRR voltage and redundant row test activation signal TEST1. The size of this P channel MOS transistor is small, external power supply voltage EVcc is applied to its source electrode, and ground voltage is applied to its gate electrode. Therefore, the transistor 217 raises the voltage of the node PRR to the H level when the pad 214 is in a floating state. The output signal of NAND gate 218 is applied to one input node of NAND gate 195.

  In such a semiconductor memory device, when the redundant row test mode is not entered, since the redundant row test activation signal TEST1 is at the L level, the output signal of the NAND gate 218 is at the H level. Therefore, if the applied address matches the programmed replacement address, redundant row address detection signal SRB is activated to H level. On the other hand, when the given address does not match the programmed replacement address or the replacement address is not programmed, redundant row address detection signal SRB is inactivated to L level.

  FIG. 29 is a circuit diagram showing an overall configuration of a redundant row address detection circuit used in place of the redundant row address detection circuit of the first embodiment shown in FIG. Unlike the redundant row address detection circuit shown in FIG. 19, the redundant row address detection circuit according to the second embodiment includes an inverter 219 and a NAND gate 220. The voltage at node PRR shown in FIG. 29 is applied to one input node of NAND gate 220 through inverter 219. Redundant row test activation signal TEST 1 is applied to the other input node of NAND gate 220. The output signal of NAND gate 220 is applied to one input node of NAND gate 195. Therefore, when the redundant row test mode is not entered, the redundant row address detection circuit shown in FIG. 29 operates in the same manner as the redundant row address detection circuit shown in FIG.

  Next, when the redundant row test mode is entered, the redundant row test activation signal TEST1 becomes H level. When external pad 214 is in a floating state or H level is applied to external pad 214, redundant row address detection signal SRB is activated to H level, while redundant row address detection signal SRA remains inactive at L level. Has been. Next, when L level is applied to external pad 214, redundant row address detection signal SRA is activated to H level, and redundant row address detection signal SRB is inactivated to L level. Therefore, even if such a circuit configuration is adopted, the two redundant row address detection signals SRA and SRB can be forcibly switched. In this way, it is possible to test the function of all redundant row memory cells other than the intersection with the redundant column by switching the redundant row address detection signals SRA and SRB of the two systems by the external pad 214 and inputting the address signal from the outside. It becomes.

  FIG. 30 is a circuit diagram showing a configuration of a redundant column address detection circuit used in place of the redundant column address detection circuit shown in FIG. Unlike the first embodiment of FIG. 23, the redundant column address detection circuit of the second embodiment includes an external pad 215, inverters 2222 and 2225, a P-channel MOS transistor 2223, a resistor 2224, and NAND gates 2226 and 2227. Voltage PC of external pad 215 is applied to one input node of NAND gate 2226 through resistor 2224 and also applied to one input node of NAND gate 2227 through inverter 2225. The size of P channel MOS transistor 2223 is small, its source electrode is supplied with external power supply voltage EVcc, and its gate electrode is supplied with a ground voltage. Therefore, when external pad 215 is in a floating state, this P channel MOS transistor raises the voltage of node PCC to the H level.

  When the redundant column test mode is entered, redundant column test activation signal / TEST2 becomes L level, whereby NAND gates 2226 and 2227 are both activated. At this time, if external pad 215 is in a floating state or H level is applied to external pad 215, output signal / TAC of NAND gate 2226 goes to L level. Therefore, when column decode activation signal CDE becomes H level, redundant column activation signal SCEA is activated to H level. On the other hand, when L level is applied to external pad 215, output signal / TAC from NAND gate 2226 goes to H level and output signal / TBD from the NAND gate goes to L level. Therefore, when column decode activation signal CDE becomes H level, redundant column activation signal SCEB is activated to H level. When redundant column test activation signal / TEST2 becomes L level, redundant column activation signal NCE immediately becomes L level.

  In this way, the redundant column activation signals SCEA and SCEC of the two systems and the redundant column activation signals SECB and SCED are switched by the external pad 215. Therefore, if an address is given from the outside, all the points other than the intersection with the redundant row can be obtained. A functional test of the redundant column memory cell can be performed.

  Further, when the redundant row test mode and the redundant column test mode are entered at the same time, the applied voltages PR and PC of the external pads 214 and 215 are changed, and the addresses and lower addresses necessary for selecting the memory cell array block are input. Thus, it is possible to perform a function test of the redundant memory cell located at the intersection of the redundant row and the redundant column.

  In the second embodiment, a configuration has been described in which the redundant pad test mode and the redundant column test mode can be switched by the external pads 214 and 215. However, the redundant row test mode can be switched by an external pad, Even if the test mode can be switched by an externally applied address as in the first embodiment, all redundant memory cells can be tested in the same manner as in the first and second embodiments.

  Also, even if the redundant row test mode can be switched by an externally applied address and the redundant column test mode can be switched by an external pad, all redundant memory cells can be tested in the same manner as in the first and second embodiments. it can. According to the semiconductor memory device of the second embodiment, in addition to the same effects as the effects (7.1) to (7.8) of the first embodiment described above, each of the redundant row and redundant column systems By directly applying a probe or the like to the switching external pad, it is possible to perform a function test of the redundant memory cell during the die sort test. Therefore, it is possible to switch the redundant system more easily and reliably.

1 is a block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a test mode control circuit in FIG. 1. FIG. 3 is a block diagram showing a configuration of an external clock detection circuit in FIG. 2. 4 is a timing chart showing a set operation by WCBR of an external clock detection circuit 122 of FIG. 3. 4 is a timing chart showing a reset operation by ROR or CBR of the external clock detection circuit of FIG. 3. FIG. 3 is a block diagram showing a configuration of a test group detection circuit in FIG. 2. It is a circuit diagram which shows the structure of the high voltage detection circuit in FIG. It is a circuit diagram which shows the structure of the test group decoder in FIG. FIG. 3 is a circuit diagram showing a configuration of an address key latch circuit in FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a special test mode clock decoder in FIG. 2. 3 is a timing chart showing a set operation by the test mode control circuit of FIG. 2. 3 is a timing chart showing a reset operation by the test mode control circuit of FIG. 2. 2 is a block diagram showing a configuration of a memory cell array, a redundant row memory cell array, a redundant column memory cell array, a redundant column row memory cell array, and peripheral circuits thereof in FIG. FIG. 14 is a wiring diagram showing a configuration of each memory cell array block in FIG. 13. It is a circuit diagram which shows the structure of each row decoder in FIG. FIG. 14 is a circuit diagram showing a configuration of each redundant row decoder in FIG. 13. FIG. 14 is a circuit diagram illustrating configurations of an RX decoder and a redundant RX decoder in FIG. 13. FIG. 2 is a circuit diagram showing a configuration of a redundant row address program circuit included in the redundant memory control circuit in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a redundant row address detection circuit included in the redundant memory control circuit in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of another redundant row address detection circuit included in the redundant memory control circuit in FIG. 1. FIG. 14 is a circuit diagram showing a configuration of a Y lower predecoder in FIG. 13. FIG. 14 is a circuit diagram showing a configuration of a Y upper predecoder in FIG. 13. FIG. 2 is a circuit diagram showing a configuration of a redundant column address detection circuit included in the redundant memory control circuit in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a redundant column address program circuit included in the redundant memory control circuit in FIG. 1. It is a circuit diagram which shows a part of column decoder in FIG. FIG. 2 is a circuit diagram showing a configuration of a redundant column decoder in FIG. 1. It is a block diagram which shows the whole structure of the semiconductor memory device by Embodiment 2 of this invention. FIG. 28 is a circuit diagram showing a configuration of a redundant row address detection circuit included in the redundant memory control circuit in FIG. 27. FIG. 28 is a circuit diagram showing a configuration of another redundant row address detection circuit included in the redundant memory control circuit in FIG. 27. FIG. 28 is a circuit diagram showing a configuration of a redundant column address detection circuit included in the redundant memory control circuit in FIG. 27. FIG. 10 is a block diagram showing a configuration of a conventional semiconductor memory device capable of performing a pass / fail judgment test of a spare memory before replacement. FIG. 32 is a circuit diagram showing a configuration of a test mode detection circuit used in the semiconductor memory device of FIG. 31. FIG. 32 is a circuit diagram showing a configuration of a test signal decoder circuit used in the semiconductor memory device of FIG. 31. FIG. 32 is a circuit diagram showing a configuration of one basic circuit in FIG. 31.

Explanation of symbols

  100 normal memory cell array, 101 redundant row memory cell array, 102 redundant column memory cell array, 103 redundant column row memory cell array, 106, RDC1 to RDC16 row decoder, 107, SRDC1 to SRDC16 redundant row decoder, 108, CDC space column decoder, 109, SCDC redundant column decoder, WL0 to WLn word line, SWL0 to SWLm redundant word line, CSL0 to CSLj column selection line, SCSL0 to SCSLi, SCSLA, SSCLB, SCSLC, SCSLD redundant column selection line, 112 test mode control circuit, 113 redundant memory Control circuit, BL, / BL bit line pair, SA1 to SA3 sense refresh amplifier, SS0 to SSA3 redundant sense refresh amplifier, CS RAM selection gate, MC memory cell, RMC redundant row memory cell, CMC redundant column memory cell, RCMC redundant row column memory cell, 180,207 program unit, 190,206 detection unit, 214,215 external pad, TEST1 redundant row test activation Signal, / TEST2 redundant column test activation signal, TMB multi-bit test activation signal, SRA, SRB redundant row address detection signal, SCEA, SCEB, SCEC, SCED redundant column activation signal, RXF0, RXF1 normal word line drive signal, SRXF0, SRXF1 Redundant word line drive signal.

Claims (2)

(A) a plurality of word lines;
(B) a plurality of normal bit line pairs arranged crossing the word line;
(C) a plurality of normal memory cells arranged corresponding to the intersections of the word lines and the normal bit line pairs;
(D) a plurality of normal column selection gate pairs provided corresponding to the normal bit line pairs, each connected to a corresponding normal bit line pair;
(E) first and second redundant bit line pairs disposed across the word line;
(F) a plurality of redundant memory cells arranged corresponding to the intersections of the word line and the first and second redundant bit line pairs;
(G) a first redundant column selection gate pair connected to the first redundant bit line pair; and (h) a second redundant column selection gate pair connected to the second redundant bit line pair. Contains multiple blocks,
A plurality of normal column selection lines provided corresponding to the plurality of normal column selection gate pairs, each connected to a control electrode of each of the normal column selection gate pairs in the corresponding plurality of blocks;
A first redundant column selection line connected to each control electrode of the first redundant column selection gate pair in the plurality of blocks;
A second redundant column selection line connected to each control electrode of the second redundant column selection gate pair in the plurality of blocks;
Normal column selecting means for selecting one of the normal column selection lines in response to a column address signal given from the outside;
First program means for generating a first coincidence signal when a first column substitution address is programmable and a column address signal applied from the outside coincides with the first column substitution address;
First detection means for generating a first redundant column activation signal in response to a first coincidence signal provided from the first program means;
Second program means for generating a second match signal when a second column replacement address is programmable and the column address signal matches the second column replacement address;
Second detection means for generating a second redundant column activation signal in response to a second coincidence signal provided from the second program means;
A redundant column that selects the first redundant column selection line in response to a first redundant column activation signal and selects the second redundant column selection line in response to the second redundant column activation signal Selecting means, and inactivating means for inactivating the normal column selecting means in response to any of the first and second coincidence signals,
The first program means can replace any of the normal bit line pairs of the plurality of blocks with the first redundant bit line pair,
The second program means, Ri can der replaced with the plurality of any of the normal bit line pair both said second redundant bit line pairs of the block,
The first program means can program a part of the first row replacement address together with the first column replacement address, the column address signal matches the first column replacement address, and externally Generating a first match signal when a portion of a given row address signal matches a portion of the first row replacement address;
The second program means can program a part of a second row replacement address together with the second column replacement address, the column address signal matches the second column replacement address, and the row that occur the second coincidence signal when a portion of the address signal coincides with a part of the second row replacement address, the semiconductor memory device. The plurality of blocks are arranged in alignment with the extending direction of the normal bit line pair,
The plurality of normal column selection lines, the first redundant column selection line, and the second redundant column selection line are arranged along the extending direction of the normal bit line pair in common with respect to the plurality of blocks. ,
The semiconductor memory device further includes:
Provided corresponding to the block, arranged so as to sandwich the plurality of normal memory cells in the corresponding block in the extending direction of the pair of normal bit lines, and read from the plurality of normal memory cells in the corresponding block A plurality of normal sense refresh amplifier input / output control circuits for amplifying the received data;
Provided corresponding to the block, arranged so as to sandwich the plurality of redundant memory cells in the corresponding block in the extending direction of the normal bit line pair, and read from the plurality of redundant memory cells in the corresponding block 2. The semiconductor memory device according to claim 1, further comprising a plurality of redundant sense refresh amplifier input / output control circuits that amplify the data.

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