KR0181204B1 - Self-repair circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to a self repair circuit of a semiconductor memory device which simultaneously performs repair of a detected defective memory cell simultaneously with a test for detecting a defective memory cell after packaging a chip of the semiconductor memory device. The self repair circuit is usefully used in a semiconductor memory device having a plurality of normal memory cells and a plurality of spare memory cells. Defect memory cell detection means for supplying address signals of normal memory cells of the semiconductor memory device sequentially to detect defective memory cells and generating corresponding defect detection information and defective address signals, and a plurality of electrically fused fuses. And fuses the fuses corresponding to the defect address of the plurality of fuses in response to the input of the defect detection information and the input of the defect address signal to automatically program the defect address and to block the defect after the blocking of the defect detection information. And a spare decoding means for selecting a spare line connected to a spare memory cell corresponding to the defective address among the plurality of spare memory cells when an address is input. The self-repair circuit configured as described above comprises a normal memory cell test. Defects at the same time The repair operation corresponding to the cell is executed.

Description

Self Repair Circuit of Semiconductor Memory Device

1 is a block diagram of a self repair circuit of a semiconductor memory device according to the present invention.

2 is a circuit of a spare row circuit according to the present invention, which provides an electrical melt fuse.

Circuit diagram configured to enable low repair of defective memory chips simultaneously with wafer testing.

3 is one embodiment of an electrical fusion fuse used in the present invention.

4 is a detailed view of the spare row selector shown in FIG. 1, which is a circuit diagram for selecting one of several spare row decoders.

5 is an operation timing diagram for explaining the operation of FIG.

6 is a detailed view of a shift clock generator for generating the shift clock provided in FIG.

7 is a detailed view of a reset pulse generator according to the present invention.

8 is a detailed view of a flag pulse generator according to the present invention.

9 is an operation timing diagram for explaining the operation of FIG.

10 is a detailed view of a latch pulse generator in accordance with the present invention.

11 is a circuit of a spare column circuit according to the present invention, which provides an electrical melting fuse.

A circuit diagram configured to allow column repair of a defective memory cell at the same time as a wiper test.

12 is a detailed view of the column address fuse circuit CAF shown in FIG.

13 is an operation timing diagram for explaining the operation of FIG.

14 is a detailed diagram of a repair column address generator according to the present invention, which is included in the spare column circuit.

15 is a detailed view of a spare column selector according to the present invention, which is a circuit diagram for selecting one of several spare column decoders.

FIG. 16 is a detailed view of a shift clock generator for providing the shift clock shown in FIG.

17 is an operation timing diagram for explaining the operation of FIG.

FIG. 18 is a detailed view of the repair mode selector according to the present invention, which is one embodiment of the mode selector shown in FIG.

FIG. 19 is a timing diagram for explaining the operation of the repair mode selector shown in FIG. 18. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting and repairing defective memory cells of a semiconductor memory device. In particular, the present invention relates to a self repair of a semiconductor memory device that simultaneously performs repair of a defective memory cell detected through a test for detecting a defective memory cell after packaging. It relates to a repair circuit.

Typically, as the density of semiconductor memory devices increases, redundancy circuits (or repair circuits) for replacing defective memory cells with redundant memory cells (also referred to as spare memory cells in the art) are the manufacturing cost of chips. It is commonly used to save money. As described above, in order to detect and repair a defective memory (or bit) cell to a spare memory cell, a defect in the memory cell array is tested through a wafer test or a burn-in test after packaging, as is well known. (defective) The memory cell (or combined bit cell) must be detected.

Spare memory cells of most semiconductor memory devices are separated from regular memory cell arrays, and if defects or defects in the normal memory cell arrays are found by the above test, the defective memory cells are stored in a normal memory cell. It is separated from the cell array and replaced by a spare cell in the spare memory cell array. In order to replace a defective memory cell with a spare memory cell as described above, a conventional memory includes a row spare memory cell, a column spare memory cell, a low redundancy circuit for activating the low spare memory cell, and the column spare memory. It has a column redundancy circuit that activates the cell. Therefore, in the general-purpose semiconductor memory device, when a specific bit cell fails, that is, when a defect occurs, the bit memory corresponding to all given addresses operates normally by replacing it with a separate spare memory cell (bit cell). Redundancy (repair) circuits are used.

The conventional repair method used in a general semiconductor memory device performs a test on a wafer to detect a fail batcell address, and then disables the word line or column selection line of the detected defective address, and instead, the spare word line in the spare cell. Alternatively, the fault address can be programmed with a fuse to enable the spare column select line. Such a fuse programming of a defective address selectively cuts a fuse associated with an address corresponding to a bit of a defective memory cell, so that a spare word line or a spare column when an input address and an address programmed as a fuse melt coincide. Is to enable the selection line. The replacement of a defective memory cell (bit cell) with a spare word line or a spare column selection line is determined in advance in an efficient direction according to the spare row memory cell or spare column memory cell. I use it.

However, in the conventional repair method, after detecting an address of a failed bit cell through a wafer test, the fuse corresponding to the defective address is melted, so that time and equipment for fuse melting are separately required. In addition, since the fuse fusion is no longer possible after the wafer is packaged, a problem arises in that the defective memory cell generated after the patching and the defective memory cell generated at the burn-in cannot be repaired.

In order to solve the above problems, a test program and a self repair circuit are mounted on a chip of a semiconductor memory device so that the chip is powered up and a built-in self test for detecting a defective memory cell (fail bit cell). : Bist method and built-in sire repair (BISR) technique which stores the detected fail bit address in a separate memory, for example, SRAM, and operates each time a defective address is input. Has been used. Such methods such as BIST, BISR, etc. are described in the IEEE Journal of solid state circuit, VOL. 27. NO 11. November 1992, pp. 1525-1515. However, the method of BIST, BISR, etc. as described above requires a separate process because a micro program-ROM for a test program is required on a chip, and requires a separate chip area for designing a BIST and BISR circuit. There has been a problem that the area of the chip area overhead is large.

Techniques other than the redundancy described above are disclosed in US Pat. No. 4,473,895. The technique disclosed in U.S. Patent No. 4,473,895 provides for the addition of a SARM cell separately through the electrical fuse carpet after packaging to enable the removal of a failed single bit of fail after being packed while maintaining a general redundancy scheme. It is necessary to repair after coding the address of the fail bit. However, even in such a redundancy technique, the test and fuse cutting process remains on the wafer and causes a problem of an increase in a separate chip area due to bushings for SRAM cells and addresses input to each SRAM cell.

Therefore, it can be seen that as the integration of memory devices increases, a decrease in test time becomes an important problem in increasing the yield, and there is a need for a method for solving the fail bit generation problem during packaging and burn-in.

Accordingly, the present invention provides a self repair circuit in which a memory cell repairs a defective memory cell simultaneously with a memory cell test executed after the package is completed.

It is another object of the present invention to provide a redundancy circuit which automatically repairs a memory cell in a spare column upon detection of a defect of a low memory cell continuously.

It is another object of the present invention to omit the test time on the wafer and the time and equipment for repairing by performing the repair at the same time after the packaging, and the fail bit occurring during the packaging and burn-in is automatically repaired. It is to provide a repair circuit.

It is still another object of the present invention to provide a circuit for automatically programming a defect address detected in a memory test in a semiconductor memory device having a plurality of spare circuits.

It is still another object of the present invention to automatically select at least one of a plurality of spare circuits for selecting a spare memory cell in response to a defect address detected during a memory test, and automatically program the detected defect address to detect a defective memory cell. It is to provide a circuit that repairs automatically.

It is still another object of the present invention to provide a circuit in a semiconductor memory device having a plurality of spare row circuits for automatically programming a row defect address detected during a memory test to at least one spare row circuit of the plurality of spare row circuits. Is in.

It is still another object of the present invention to provide a circuit for automatically programming a column defect address detected in a memory test to at least one spare column circuit of the plurality of spare column circuits in a semiconductor memory device having a plurality of spare column circuits. Is in.

It is still another object of the present invention to provide a circuit for testing a semiconductor memory device having a spare row circuit and a spare column circuit to determine whether to repair a failed memory cell to a spare row or a spare column.

According to an aspect of the present invention, there is provided a semiconductor memory device including a plurality of normal memory cells and a plurality of spare memory cells, wherein the address signals of the normal memory cells of the semiconductor memory device are sequentially supplied to provide a defective memory cell. A plurality of defective memory cell detection means for detecting and generating detection information of a corresponding defective memory cell, and a plurality of electrically fused fuses, the plurality of fuses in response to an input of the defect detection information and an input of the defective address signal. A fault circuit is provided at the same time as a normal memory cell test by having a spare circuit for programming a fault address by melting fuses corresponding to a fault address among the fuses and selecting a spare memory cell corresponding to a corresponding fault address signal among the plurality of spare memory cells. The operation of the repair corresponding to the cell Characterized in that the row.

According to the principles of the present invention for the characteristic operation as described above, the error pulse ERR indicating an error in the memory tester when the defective memory cell is detected when testing the semiconductor memory device corresponding to the corresponding address Repair is performed by electrically fusion of one fuse. In order to ensure that the fuse is melted only when repairing, the electrically fuse is fuseable when a predetermined current flows, so that the external power voltage EVCC, which is higher than the chip operating power supply voltage IVCC, is supplied only during the test of the memory. The circuit to be provided is provided in the spare row circuit or the spare column circuit. In the self repair circuit according to the present invention, since the repair is automatically performed at the same time as the memory test, the spare word line or the spare column selection line to be repaired should be selected during the test. That is, only one of a plurality of spare word lines or spare column select lines should be selected and repaired for one defective memory cell. And a spare mode selector having a spare word line selection circuit and a spare column selection line selection circuit using a shift register to select only one of a plurality of spare word lines and a spare column selection line, and using the repair mode selector. Determine whether to replace a defective memory cell with a spare word line or a spare column select line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a self repair circuit of a semiconductor memory device according to the present invention. Referring to FIG. 1, in the semiconductor memory device 10, three signal lines for an interface are connected between the test devices 12 for testing the semiconductor memory device. The signals transmitted to each of these three signal lines are supplied from the test device 12 to the semiconductor memory device 10 to the repair enable signal RE (Repairenable) and the error pulse ERR (Error pulse) and the semiconductor memory device 10 to the test device 12. This is a repair failure signal RF (Repair failure). The repair enable signal RE is a signal indicating that repair of a defective memory cell is simultaneously performed when the semiconductor memory device 10 is tested using the test apparatus 12. If the repair enable signal RE remains low during the test, only a normal test is performed and repair of the defective memory cell is not performed. When the defective memory cell is repaired, the repair enable signal RE is high. Should be tested. When a high error pulse ERR is generated from the test apparatus 12, the word line or column selection line of the corresponding defective address is replaced with a spare word line or spare column selection line. Such operation will be clearly appreciated by understanding the following description. The repair failure signal RF is a signal generated from the semiconductor memory device 10 when all spare word lines and spare column selection lines in the memory device 10 are used for repair. The repair failure signal RF is transmitted to the test device 12 so that the repair failure signal RF becomes high. If the test of all memory cells is not completed until then, it can be seen that repair is impossible. Therefore, in the semiconductor memory device 10 according to the present invention, an input / output terminal (pin) for inputting / outputting three signals for repairing a defective memory cell in conjunction with the test apparatus 12 should be further added on a chip.

First, while the semiconductor memory device 10 and the test device 12 are connected by three in-face lines as described above, the repair mode selector 18 in the semiconductor memory device 10 outputs the spare low mode selection signal PRSEL to a logic high state. Only a number of spare row circuits (in this invention, the spare row circuit is a conventional spare row decoder) (Spare Row Circuit (hereinafter referred to as SRC)) only 16a to 16n + 1 are operable, and spare row selector 20 and spare column The selectors 22 will be described under the assumption that the spare row select signal SROWi and the spare column select signal SCOLi are activated and output in a high state in response to the activation of the initial repair enable signal RE.

Now, when the test apparatus 12 starts an operation for detecting a defect of a normal memory cell in the semiconductor memory device 10, the repair enable signal RE is activated high, and the repair enable signal RE is a plurality of SRC 14a-14n + 1. And a plurality of spare column circuits (hereinafter referred to as SCCs) 16a to 16n + 1 and a repair mode selector 18, a spare row selector 20, and a spare column selector 22.

When the test apparatus 12 detects a defect of the normal memory cell in the semiconductor memory device 10 in the above state, the error pulse ERR output therefrom is activated high. At this time, a spare low mode selection signal PRSEL output in a high state from the repair mode selector 18 among a plurality of SRCs 14a to 14n + 1 and a spare low select signal SROWi output in a high state from the spare low selector 20. For example, only SRC 14a which inputs the spare row select signal SROW1 can receive the redundancy enable signal RE and the error fill.

The ERR automatically performs fuse programming of the defective address corresponding to the defective address signal supplied from the test apparatus 12. When the fuse program is executed as described above, the low repair shift clock PRSi (where I is a natural number, 1,2,3, .. n) is supplied from the SRC 14a to the spare row selector 20. The spare row selector 20 shifts the spare row select signal SROWi in response to the input of the low repair shift clock PRSi to activate the spare row select signal SROW2 supplied to the second SRC 14b. Therefore, when the second defective memory cell is detected, it can be seen that fuse programming for the detected defective address is automatically executed in SRC 14b. When only the semiconductor memory device 10 is operated in the active mode while the fuse programming corresponding to the above address is completed, the repair enable signal RE is disabled in a low state so that the defective address signal is input to the semiconductor memory device 10. The spare row word line corresponding to the defective address is activated and repaired by the operations of the SRCs 14a to 14n + 1.

If the spare low mode selection signal PRSEL output from the repair mode selector 18 is inactive and the spare column mode selection signal PCSEL is output in the activated state, the test apparatus 12 detects a defective memory cell. The corresponding fault address is automatically programmed in SCCs 16a-16n + 1 and repaired to the spare column select line. For example, if only the spare column selection signal SCOC1 of the plurality of SCROL1 to SCOLn + 1 outputs from the spare column selector 22 is activated, only the SCC 16a is the defective address supplied from the test apparatus 12 by the redundancy enable signal RE and the error pulse ERR. Fuse programming of the defective address corresponding to the signal is automatically performed. When the fuse program as described above is performed, the column repair shift clock PCSi (where i is a natural number) is supplied from the SCC 16a to the spare column selector 22. The spare column selector 22 shifts the spare column select signal SCOLi in response to the input of the column shift clock PCSi to activate the spare column select signal SCOC1 supplied to the second SRC 14b. Thus, when the second defective memory cell is detected, it can be seen that fuse programming for the detected defective address is automatically executed in SCC 16b.

When only the semiconductor memory device 10 is operated in the active mode while the fuse programming corresponding to the above defective address is completed, the repair enable signal RE is disabled in a low state so that the defect address signal is input to the semiconductor memory device 10. The spare column select line corresponding to the corresponding defective address is activated and repaired by the operations of the SCCs 16a to 16n + 1. Each of the plurality of SRCs 14a to 14n + 1 and the plurality of SCCs 16a to 16n + 1 operated as described above is inputted by a plurality of electrical fuses melted when a predetermined amount or more of current flows, input of defective memory cell detection information, and defective address signal. Means for selectively melting only a fuse corresponding to the defective address among the plurality of electrical fuses to fuse the defective address. The configuration thereof is as follows.

2 is a circuit diagram of a spare row decoder (SRC) according to the present invention, which shows a circuit diagram configured to enable row repair of a defective memory cell at the same time as wafer testing using an electric fuse. Referring to FIG. 2, a plurality of electrical fuses in which one side node is commonly connected to the internal node N1 is connected to F1 to F4n, and a source is connected to ground voltage Vss in common, and the plurality of electrical fuses are connected to F1 to F4n. A plurality of NMOS transistors NMOS1 to NMOS4n and a plurality of NMOS transistors NMOS1 to NMOS4n for inputting the decoded row address signals DRA1, DRA1B to DRAi, and DRAiB to respective gates, respectively, having drains connected to the other nodes, respectively, and the internal power supply voltage IVcc and the above. A first PMOS transistor PMOS1 connected to an internal node n1 and precharging the internal node N1 to the internal power supply voltage IVcc in response to a low activation of the precharge control signal PPRE and defective memory cell detection information The program voltage is precharged to a predetermined level in response to the input of the signal, and the program voltage is supplied to the internal node N1 connected to the spare word line (redundant word line). Program consists of a voltage supply to. Here, the defective memory cell detection information includes a repair enable signal RE signal output from the test apparatus 12, an error-fill ERR signal, and a spare row select signal SROWi signal that specifies that only one of several spare rows is to be repaired, and a defect that is currently generated. The NAND gate 28 and the external power supply voltage EVcc for activating the spare low shift clock PRSi by a logical combination of the spare low mode selection signal PRSEL indicating whether to replace the memory cell with the spare low circuit or the spare column circuit. The second PMOS transistor PMOS2 is connected between the internal nodes N1 and supplies an external power supply voltage EVcc, that is, a program voltage, to the internal nodes N1 in response to the spare low shift clock PRSi.

The spare row circuit (or spare row decoder) configured as described above is characterized in that electrical fuses melted when a predetermined amount of current flows in a fuse for programming a defective address of a defective memory cell, and a circuit for melting the electrical fuse is added. Configuration. The plurality of electrical fuses F1 to F4n shown above are electrically fused, and have a configuration as shown in FIG. 3 below.

3 is one embodiment of the electric fuse used in the present invention, which is formed by connecting the bitline poly BLP in a bottleneck shape between the metal M and M, and the resistance of the bitline poly BLP in the bottleneck form. Since the voltage to be melted varies depending on the size, the size of the resistor must be determined according to the level of the external power supply voltage EVcc during the memory cell test. In FIG. 3, MC denotes a metal connection point.

The operation of automatically repairing the detected defective memory cell simultaneously with the test for detecting the defect of the memory cell of the semiconductor memory device will be described below.

The repair enable signal RE output from the test apparatus 12 is activated high so that the repair can be performed simultaneously during the test. When a defective memory cell is detected by the operation of the memory cell test, the error pulse ERR output from the test apparatus 12 is activated to a logic high and supplied to each block in the semiconductor memory device 10. At this time, the spare row select signal SROWi output from the spare row selector 20 to which the repair is to be performed becomes high, and when the spare row and spare column are repaired to the spare row, the spare row select signal PRSEL output from the repair mode selector 18 is performed. This is activated high. This operation of the spare row selector 20 and the operation of the repair mode selector 18 will be clearly understood by the following description.

When all the signals input to the NAND gate 28 of FIG. 2, for example, RE, ERR, and PRSEL, are input high by the above operation, the NAND gate 28 operated by the input of the external power supply voltage EVcc is low. Is supplied to the gate of the second PMOS transistor PMOS2. The low signal output from the NAND gate 28 is used as the low repair shift clock PRSi. Therefore, when all control signals input to the four-input NAND gate 28 are activated high, the second PMOS transistor PMOS2 is turned on to raise the level of the internal node N1 to the level of the external power supply voltage EVcc.

In this case, the decoded row address signals input to the gates of the plurality of NMOS transistors NMOS1 to NMOS4n + 1 are inputted with high address signals corresponding to the memory cells in which the defects occur among DRA1, DRA1B to DRAi, and DRAiB. Only enMOS transistors that input the decoded defective address signals corresponding to the gate are turned on. For example, when a memory cell is defective when row addresses RA1 to RAI are all zero, the NMOS transistor decoded address signals DRA1B, DRA2B, DRA3B, DRA4B, and DRAinB among the plurality of NMOS transistors NMOS1 to NMOS4n + 1. Only the EnMOS transistors that input to the gate are turned on.

In the above state, since the PMOS transistor PMOS2 is turned on, a current path from the external power supply voltage EVcc to the ground voltage Vss is formed through the drain-source channel of the turned-on NMOS transistors so as to correspond to a defective address. Are rugged automatically. In such a case, the high level of the precharge control signal PPRE supplied to the gate of the first PMOS transistor PMOS1 to block the current path from the external power supply voltage EVcc to the internal power supply voltage IVcc is at the level of the external power supply voltage EVcc. Should be possible. Therefore, when a memory cell test for checking whether a memory cell is defective or a defective memory cell is detected by the above operation, fuses corresponding to the defective address are automatically melted and the defective address is programmed.

As described above, when only the semiconductor memory device 10 is active and the fuses corresponding to the defective address are automatically programmed and melted, the test enabler 12 is disconnected during the active operation, so that the repair enable signal RE of the interface line is input low. Thus, the output of the NAND gate 28 is inactivated high to turn off the second PMOS transistor PMOS2. Therefore, the process of selecting the spare word line by the operation of the spare row circuit (a spare row decoder) is the same. That is, when the memory device 10 transitions to the precharge mode, the internal node N1 is precharged to the level of the internal power supply voltage IVcc by turning on the first PMOS transistor PMOS1.

In such a state, when the repaired defective address signal and another address signal, for example, an address signal for inputting a bit of a normal cell, are input, a carpet of a plurality of NMOS transistors NMOS1 to NMOS4n + 1 connected in parallel. The spare wordline driver is not enabled by turning on an NMOS transistor connected to an unused fuse and turning it into internal node N10I low. That is, the low redundant enable signal PRRE for enabling the spare word line driver (not shown) is shifted low to not select the corresponding spare word line.

However, when a defective address signal corresponding to the fused fuses among the plurality of fuses F1 to F4n + 1, for example, a defective address signal for selecting a defective memory cell, is inputted, the fuse corresponding to the input defective address. The internal node N1 maintains the high state precharged by the first differential PMOS transistor PMOS1 because all of them are fused. When the internal node N1 remains high, the low redundant enable signal PRRE goes high to disable the normal word line with the defective memory cell located on the normal memory cell array and to enable the corresponding spare word line. .

When there are a plurality of spare row circuits 14 configured as shown in FIG. 2 as shown in FIG. 1, when a defective memory cell is generated, only one of the plurality of spare row circuits is selected to fuse the fuse located in the spare row circuit to a defective address. Corresponding fuse programming should be performed. At this time, the error pulse ERR output from the test apparatus 12 is inputted as high, and after the fusion of the fuse to which the defective address corresponding to the defective memory cell, that is, the decoded row address is completed, starts a test of whether the next memory cell is defective. Another spare row circuit must be selected before. The spare row circuit, once selected and used for repair, should not be reselected until the test is complete. This selection of the spare row circuit is performed by the operation of the spare row selector 20 shown in FIG. 1, the configuration of which is shown in FIG.

4 is a detailed view of the spare row selection circuit shown in FIG. 1, which is a circuit diagram for selecting one of several spare row decoders. 4 is an example configured to generate N spare row select signals SROWi for selecting N spare row circuits by N stage shift registers in which a plurality of flip-flops 34 to 38n are connected in series. In the above, a spare row select signal SROWi that is activated high at each output node of the plurality of flip-flops 34 to 38n constituting the shift register is generated, and one spare row select signal SROWi is duplicated as a test of the test apparatus 12 proceeds. Is activated high, and the spare low circuit, which is supplied with the spare low select signal SROWi which is activated high, fuses the input of the defective address to perform the operation of the spare low repair.

5 is an operation timing diagram for explaining the operation of FIG.

Now, when the repair enable signal RE output from the test apparatus 12 is activated high as shown in FIG. 5, it is input to the reset pulse generator RPG, the flag pulse generator FPG, and the low latch pulse generator RLPG shown in FIG. Supplied.

The reset pulse generator RPG shown in FIG. 4 generates a reset pulse SRP in the high state as shown in FIG. 5 in response to the high of the repair enable signal RE to generate a plurality of NMOS transistors NMOS5 to NMOS7n. Supply to the gate. Each source of the plurality of NMOS transistors NMOS5 to NMOS7n is connected to a ground voltage Vss, and each of the drains includes a plurality of output nodes of flip-flops 34 to 38n constituting a shift register and a plurality of output nodes shown in FIG. It is connected to the lines connected between the input nodes of the spare row circuits 14a to 14n + 1, respectively. Therefore, when the reset pulse SRP such as the fifth degree is generated from the reset pulse generator RPG, a plurality of NMOS transistors NMOS5 to NMOS7n is turned on to reset the output of all flip-flops 34 to 38n low, i.e., all spare row select signals SROWi go low, leaving no spare row circuitry selected. The flagged pulse generator FPG performs the repair. In response to the high of the enable signal RE, generate a high state flag pulse SFP as shown in FIG. The flag pulse SFP is high information supplied to the delay terminal D of the first flip-flop 34 of the shift register. The flag pulse SFP is shifted one to the right every time a low repair shift clock pulse RSPi occurs. The low latch pulse generator RLPG is a low latch pulse of a high state having a period equal to the fifth degree in response to the high of the repair enable signal RE. RLPs are generated. The above three pulses originate from the rising edge of the repair enable signal RE, and the delay and pinching of the pulses will be described in more detail in FIGS.

The low latch pulse RLP generated as shown in FIG. 5 from the low latch pulse generator RLPG is provided to one input node of the NOA gate 30. Another input node of the Noah gate 30 is connected to a node of a low repair shift clock RPS (where RPS is a predetermined delayed signal by negatively multiplying rou repair shift clocks RPS1, RPS2, RPS3, and RPSNs output from a plurality of SRCemf). The output node is connected via the inverter 32 to the clock terminal CLK of the first flip-flop 34 of the shaft register. Therefore, when the repair enable signal RE is activated high as shown in FIG. 5 from the initial test apparatus 12, the first flip-flop 34 in the shift register is generated as shown in FIG. 5 to the low latch pulse RLP. It can be seen that the spare row select signal SROW1 is activated high by latching and outputting it.

As described above, when the spare row circuit 14a configured as shown in FIG. 2 is operated on the spare row select signal SROW1, the low repair shift clock PRSi generated therefrom [the low repair shift clock PRSi generated in the spare row circuit 14a is set to PRS1. This means that when the low active is generated, the flag pulse SFP outputted from the flip-flop 34 is shifted to the right, and the operation of this shift is repeated every time the low repair shift clock PRS is activated. It can be seen that SROW1 to SROWn + 1 are generated by shifting the flag pulse SFP by inputting a low repair shift clock PRS indicating that a spare low repair is in progress. Output of the last flip-flop 38n by the shift register If the change to the high, which generates the latch circuit goes low repair fail signal PRRF which transitions to a high state connected to the output node.

In the latch circuit, a transfer gate TG is connected between the flip-flop 38n and an internal node N2 latched in an initial low state, and a signal of the internal node N2 is supplied to a gate of a PMOS transistor of the transfer gate TG. At the same time, the inverter 32a is inverted and supplied to the gate of the NMOS transistor in the transfer gate TG. Accordingly, the transfer gate TG can supply the output of the initial flip-flop 38n to the internal node N2. A latch 39 consisting of two inverters is connected to the internal node N2, and an inverter 32c is connected to an output node N3 of the latch 39. Therefore, when the output of the last flip-flop 38n goes high, the low repair failure signal PRRF goes high, indicating that all spare low circuits 14a to 14n + 1 have been selected and repaired. Once the low repair failure signal PRRF is high, it is latched to maintain a high state, where all spare row select signals SROWi are all low so that there are no more repairs in the spare row circuit.

Therefore, according to the configuration of the spare row selector 20 as shown in FIG. 4, a plurality of spare row circuits 14a to 14n + 1 installed for low defects of a plurality of defective memory cells are sequentially selected to automatically program and repair a defective address. It can be seen that.

FIG. 6 is a detailed view of the shift clock generator shown in FIG. 4, which is a row repair shift clock PRSi (PRS1, PRS2,) generated from a plurality of spare row circuits 14a to 14n + 1, respectively, configured as shown in FIG. And a NAND gate 40 for outputting by multiplying PRSN) by a negative logic and a delay 42 for delaying the output of the NAND gate 40. Accordingly, it can be seen that the low shift clock can be effectively supplied to the shift register of FIG. 4 when the output of the NAND gate 28 in any spare row circuit is output low by the above configuration.

7 is a detailed view of the reset pulse generator RPG according to the present invention. This shows the activation of the repair enable signal RE, that is, the output of the delay unit 44 and the delay unit 44 for delaying the repair enable signal RE in the high state. And a NAND gate 46 for logically combining the repair enable signal RE and an inverter 48 connected in series thereto.

The reset pulse generator RPG configured as shown in FIG. 7 receives the repair enable signal RE, which is activated high as shown in FIG. 5, and the NAND gate 44 receives the signal as low as the delay time TD1 (see FIG. 5) of the delay 44. Is supplied to the inverter 46. When the enable state of the repair enable signal RE, i.e., the input of high persists over TD1, the NAND gate 44 outputs a high signal to generate the reset pulse SRP as shown in FIG. The period TD1 of the reset pulse SRP should be set so that the EnMOS transistors NMOS5 to NMOS7n + 1 can be sufficiently turned on.

8 is a detailed view of the flag pulse generator according to the present invention. Two delayers 50 and 52 which delay the repair enable signal RE are connected in series, and the output of the delay unit 52 and the output of the delay unit 52 are connected. It consists of NAND gate 54 and inverter 56 which generate a flag pulse SFP by logical combination.

The flag pulse generator FPG configured as shown in FIG. 8 has a delay time TD2 (see FIG. 5) and a delay 52 set in the delay unit 50 when a repair enable signal RE that is activated high as shown in FIGS. 5 and 9 is input. The NAND gate 54 generates a logic low signal by a period corresponding to the delay time of the delay unit 52 by the delay time TD3 set at. At this time, the output of the NAND gate 54 is inverted by the inverter to be controlled by the inverter. Generates a flag pulse SFP having a state as high as TD3 as 9 degrees, which is usefully used as a signal that is shifted by shift registers to select one of a number of spare low circuits. The delay time TD2 is set to be larger than the delay time TD1 of the delay device 44 located in FIG. 7 described above, so that a sufficient time after the reset pulse SRP is generated Please note that there is a pulse SFP occur.

FIG. 10 is a detailed view of the latch pulse generator according to the present invention, the overall configuration of which is the same as that of the flag pulse generator circuit FPG shown in FIG. 8. Only the delay time TD4 set in the delay unit 58 The low latch pulse RLP and the column latch pulse CLP are generated after a sufficient time after the flag pulse SFP is generated by being set larger than the delay time of the delay unit 50 shown in FIG.

All of the pulse generating circuits shown in FIGS. 7, 8, and 10 are operated in response to the activation of the repair enable signal RE, which will be useful in the circuit shown in FIG. Please note that there will be no further explanation.

FIG. 11 is a circuit of a spare column circuit (SCC) according to the present invention, which is a circuit diagram configured to enable repair of a column of a defective memory cell at the same time as wafer testing using an electric fuse. Referring to FIG. 11, it can be seen that a plurality of column fuse circuits (hereinafter referred to as CAF) 88 to 92n are provided. Each of the plurality of CAFs 88-92n has fuses for electrically meltable column address programs, and fuses in the CAFs 88-92n are electrically melted by a program voltage supplied from a column address program voltage supply. The column address program voltage supply unit repairs a spare column select signal SCOLi that specifies that only one of the repair enable signal RE signal, the error pulse ERR signal, and the multiple spare column select line CLSi is to be repaired. The NAND gate 66 and the external power supply voltage EVcc for activating the spare column shift clock PCSi by a logical combination of the spare column mode selection signal RCSEL indicating whether to replace the memory cell with the spare row circuit or the spare column circuit. Spare column sheep In response to the clock PCSi to include a third coat of agarose transistor PMOS3 EVcc external supply voltage that is, supplying the program voltage to each of the CAF 88~92n. The column redundancy circuit is the same as that disclosed in US Pat. No. 4,829,480 to Samsung Electronics Co., Ltd. except for a configuration in which fuses in CAF 88 to 92n are automatically melted by the operation of the column address program voltage supply unit.

FIG. 12 shows details of the CAFs 88 to 92n shown in FIG. This means that one side is connected to node C and fuses F5 and F6 corresponding to the decoded one column address CAj, CAjB (where j is a natural number), column address signal CAj (where j is a natural number) and complementary column address signal. The input node of CAjB and the second and third transfer gates TG2 and TG3 connected to the other side of the fuses F5 and F6 are configured, and the NMOS transistors of the second and third transfer gates TG2 and TG3 are shown in FIG. It is connected to the internal node B and the PMOS transistors are connected to the node A.

13 is an operation timing diagram for explaining the operation of FIG.

The operation of the spare column circuit shown in FIG. 12 will be described in detail with reference to the configuration of FIG. 12 and FIG.

Now, as shown in FIG. 13, when the repair enable signal RE, the error pulse ERR, the spare column select signal SCOLj, and the column mode select signal SCSELs output from the repair mode selector 18 are all high, the output of the NAND gate 66 is Active low. The low signal output from the NAND gate 66 is input to the gate of the third PMOS transistor PMOS3 as the column repair shift clock PCSi and is supplied to the input node of the inverter 68. Accordingly, the third PMOS transistor PMOS3 supplies the fuse program voltage, that is, the external power supply voltage EVcc to each node C of the CAFs 88 to 92n connected to the drain as shown in FIG. 13 at this time. Is supplied to the gate of the NMOS transistor 72. Therefore, with the repair mode selector 18 activating the spare column node selection signal PCSEL to the high state by the error pulse ERR output from the test apparatus 12, the test apparatus 12 When the detection information of the defective memory cell is output, the NMOS transistor 72 is turned on. When the NMOS transistor 72 is turned on, the electric fuse connected to the drain of the transistor, that is, the main fuse 70 is melted by a high current of the external power supply voltage EVcc. At this time, the main fuse 70 also has the configuration as shown in FIG. When the main fuse 70 is fused, as illustrated in FIG. 13, the internal node B becomes high and the internal node A becomes low, so that the transmission gates TG2 and TG3 of CAF 88 to 92n configured as shown in FIG. 12 are turned on.

In the above state, when the decoded column address signals CA1, CA1B, ... CAj, CAjB of the defective memory cell are inputted, the defective column addresses among the fuses F5 and F6 located in the CAFs 88 to 92n configured as shown in FIG. Corresponding fuses are fused. For example, when CA1, CA2, ... CAj are defective addresses, fuses F6 in CAFs 88 to 92n are fused. Because the complementary address signals CA1B, CA2B, ... CAjB of the defective column address signal are input at the low level, the high current of the external power supply voltage EVcc of the node C has a low level through the fuse F6 and the transmission gate TG3. This is because a current path is formed on the address signal side. Accordingly, when a memory cell test for checking whether a memory cell is defective or a column address of a defective memory cell is detected by the above operation, fuses corresponding to the defective column address are automatically melted and a defective address is programmed.

In the test, when the address signals having a complementary relationship among the column address signals CA1, CA1B, ... CAjB are high, and the level is the level of the internal power supply voltage IVcc, the current is caused by the voltage difference from the external power supply voltage EVcc supplied to the internal node C. Since the reverse flow, the level of the high level column address signal CAj, CAjB should be at the level of the external supply voltage EVcc during repair. This operation is performed by the repair column address generator shown in FIG. 14 below.

14 is a detailed view of a repair column address generator according to the present invention.

Referring to FIG. 14, it can be seen that two paths are formed in the column address buffer. In normal active operation, i.e., when the repair enable signal RE is low, transmission of the column address signal CAj or CAjB outputted from the column address buffer in the CAF 88 to 92n configured as shown in FIGS. 11 and 12 through the transfer gate TG4. It is supplied to the gates TG2 and TG. In the repair mode in which the repair enable signal RE is supplied high, the outputs of the column address signals CAj and CAjB converted by the level shifter 98 from the level of the internal power supply voltage IVcc to the level of the external supply voltage EVcc are input to the transfer gate TG5. . The transfer gate TG5 is transferred to the latch composed of inverters 104 and 106 in response to the occurrence of the error pulse ERR output from the above-described test apparatus 12 as shown in FIG. In this case, the reason for transmitting the column address signals CAj and CAjB to the latch circuit by the error pulse ERR is to prevent an invalid address from being input. The latch latches the input column address and inputs the inverted column address signal CAj or CAjB to the transfer gate TG6. The transmission gate TG6 supplies the input signals to the CAF88 to CAF92n described above when the repair enable signal RE is activated in a high state. Therefore, the spare column circuits 16a to 16n + 1 shown in FIG. 11 are generated by the circuits shown in FIGS. 12 and 14 above as shown in FIG. It is known that the fuses corresponding to the column address where the error is detected by latching the column address signals CAj and CAjB of the defective memory cell are fuse programmed to fuse the column address of the defective memory cell.

When the chip is active in the state in which the column address of the defective memory cell is programmed by the above operation, the repair enable signal RE is low and the NAND gate 66 outputs high to turn off the third PMOS transistor PMOS3. The gate of the NMOS transistor 72 connected to the output node of the inverter 68 goes low and remains turned off. In this case, when the main fuse 70 is not fused, that is, in a spare column circuit in which the column is not repaired, the node A and the node B are formed by the drain node of the NMOS transistor 72 held high by the main fuse 70. The pull-down transistors PDNs with drains connected to the NAND gate 94 are turned on by maintaining the high and low levels, respectively, so that the output of the NAND gate 94 is high, and the inverter 96 outputs a low signal, and the spare column redundancy enable signal PCRE and spare column are maintained. The signal that activates the select line remains low, so the spare column is not enabled.

However, if the main fuse 70 is melted by the above-described operation, and the address programming fuses in the CAF 88 to CAF 92n are melted in correspondence with the defective column address, the decoded spare column selection line is decoded. The drain node of the NMOS transistor 72 transitions to the low state by the reset signal RST receiving the input of the row addresses DRAi and DRAj. Thus, the internal node B becomes high and the internal node A goes low, thereby causing the column address signal CAj. Pass CAjB to the input nodes of NAND Gate 94. That is, when all the inputs of the NAND gate 94 are high, that is, when the column address coded by the fuse carpet and the input column address signal coincide, the spare column redundancy enable signal PCRE becomes high and the spare column select line is enabled. The normal column select line is disabled.

When there are a plurality of spare column circuits having the configuration of the circuits of FIGS. 11 to 14 as shown in FIG. 1, when a defective memory cell is generated, only one of the plurality of spare column circuits is selected and located in the spare column circuit. The fuse should be melted and fuse programming corresponding to the defective address should be performed. At this time, the error pulse ERR output from the test apparatus 12 is inputted high so that the defective address corresponding to the defective memory cell, that is, the decoded column address is inputted. After the carpet has been completed, another spare column circuit must be selected before starting the next memory cell failure test. The spare column circuit, once selected and used for repair, should not be reselected until the test is complete. The selection control of the spare column circuit is executed by the operation of the spare spare row selector 20 shown in FIG. 1, and the configuration thereof is shown in FIG.

15 is a detailed view of a spare column selector according to the present invention, which is a circuit diagram for selecting one of several spare column decoders. The configuration and operation of the spare column selector circuit configured as shown in FIG. 15 are substantially the same as those of the spare row selector shown in FIG. 4, and are referred to in order to avoid confusion with reference numerals of FIG. Only the sign is written differently. In FIG. 15, the CLPG is a column latch generator, which is configured as shown in FIG. The PCS is a repair column shift clock, which is generated by logically combining the clock PCSi output from the NAND gate 66 of FIG.

The operation of the circuit configured as shown in FIG. 15 is as shown in FIG. 17, and the operation thereof may be easily understood by referring to the operation description of FIG. 4 and the operation timing diagram of FIG. That is, the circuit configured as shown in FIG. 15 resets the spare column select signal SCLOi to a low state by the selected reset pulse SRP. The selected flag pulse SFP activates the spare column select signal SCOL1 by the column latch pulse signal CLP, and then the spare column select signal SCOLi, which is enabled by the repair column shift clock PCS, is shifted one by one and the final spare column select signal SCOLn +. When 1 becomes high, the column repair failure signal PCRF is activated by a latch circuit (not shown) and supplied to the NAND gate 24 of FIG.

The NAND gate 24 shown in FIG. 1 is a spare word line or spare column to be replaced if the test for all bits of the cell array is not completed until both the column repair failure signal PCRF and the low repair failure signal PRRF are high. A repair failure signal, RF, indicating that there is no selection line, is output to test device 12 to indicate that repair is not possible.

On the other hand, the present invention operated with the above configuration is a repair mode selector 18 that immediately determines whether to replace a spare word line or a spare column selection line when a failure occurs in a specific bit during a memory cell test. It has been described above that it has been provided. The repair mode selector 18 basically repairs a low line, that is, a word line, but replaces it with a spare column when two bits are consecutively failed in the column. The configuration of the repair mode selector 18 is as shown in FIG.

18 is a detailed view of the repair mode selector according to the present invention, which is an exemplary view of the mode selector shown in FIG. The shift register latches and shifts the error pulse ERR generated from the test apparatus 12 by the clock PR generated in synchronization with the row address strobe signal RASB to generate the shifted error pulse ERRF, and the generated error pulse ERR and the A spare low mode selection signal PRSEL and a spare column by logically combining a detector for detecting a consecutive defective column address by comparing the shifted error pulse ERRF, the output of the detector and the spare column repair failure signal PCRF and the spare low repair failure signal PRRF. And a mode selection signal generator for selectively generating the mode selection signal PCSEL. In FIG. 18, the configuration of the latch composed of the inverter 122, the transmission gates TG7, TG8, the inverters 126, 128, and the latch composed of the inverters 130, 132 corresponds to the seat register, the NAND gate 132 corresponds to the detector, and the NOR gate 136 and 140 and inverters 134, 138 and 142 correspond to the mode selection signal generator.

FIG. 19 is a timing diagram for describing an operation of the repair mode selector shown in FIG. 18.

Now, as shown in FIG. 19, when an error pulse ERR is generated from the test apparatus 12 in a state in which the row address is changed, the error pulse ERR is composed of inverters 126 and 128 by a clock PR synchronized with the row address strobe RASB. Stored in the latch. If the memory cells of the column address are continuously defective and error pulse ERR is continuously generated, the error pulse ERR stored in the latch configured of the inverters 126 and 128 is transferred to another latch configured of the inverters 130 and 132 through the transfer gate TG8. In this case, the output of the NAND gate 132 having an input node connected to the output nodes of the two latches is output as logic low, thereby outputting the spare column mode output from the output node of the inverter 142. The selection signal PCSEL is activated high. In other words, if two bits in a column direction are failed in succession, the spare column selection line is replaced by a spare column select line. In the circuit of the present invention, since the test should be performed in the column direction, the test pattern of the repair mode is referred to as a arch pattern.

The repair mode selector 18 configured as described above performs a column repair operation when the low memory cell repairs a defect first, but when the spare word lines are used, that is, when the low repair failure signal PRRF becomes high. That is, repair is performed by the spare column select line. If the repair low failure signal PRRF is high, there is no selected spare low circuit, and thus the low repair enable state may be high or low. On the contrary, when all spare column decoders are used, that is, when the column repair failure signal PCRF is high, the low repair enable continues to be high, so that the repair continues by the row even if the fail is caused by the column. . Accordingly, it can be seen that the repair row and repair column modes are automatically executed according to the row or column state of the memory cell detected by the memory test.

As described above, the present invention adapts to a bit defect of a memory cell detected during a burn-in test after packaging to electrically program a fuse in a spare row circuit or a spare column circuit to automatically replace a spare row of a spare memory cell. By immediately repairing in spare color, the operation of redundancy can be accelerated and the yield can be improved, and the efficiency of redundancy can be increased by automatically moving the repair mode to the spare row or the spare column.

Claims (17)

A semiconductor memory device comprising a plurality of normal memory cells and a plurality of spare memory cells, Defective memory cell detection means for supplying address signals of normal memory cells of the semiconductor memory device sequentially to detect defective memory cells and generating corresponding defect detection information and defective address signals, and a plurality of electrically fused fuses. And program means for automatically programming a defect address by melting the fuses corresponding to the defect address among the plurality of fuses in response to the input of the defect detection information and the input of the defect address signal. Self repair circuit of a semiconductor memory device. The method of claim 1, wherein the program means comprises: a first node precharged to a predetermined level, a plurality of electrically stable fuses connected at one side to the first node, a programming voltage and the first node; A program voltage supply means connected to the first node and supplying a programming voltage to the first node in response to the defect detection information of the memory cell, and connected to the other side of the plurality of fuses and to a power supply voltage lower than the programming voltage. And a program current passing means for melting fuses corresponding to the defective address in response to an input of a signal. The self repair of a semiconductor memory device as claimed in claim 1, wherein the plurality of fuses are electrical fuses formed of a bottleneck bit line poly and fused by a high current flow between one side and the other side. Circuit. A semiconductor memory device having a plurality of normal memory cells and a plurality of spare memory cells, comprising: sequentially supplying an address signal of a normal memory cell of the semiconductor memory device to detect a defective memory cell and corresponding defect detection information and defects A defective memory cell detecting means for generating an address signal, and a plurality of electrically fused fuses, the fuse corresponding to a defective address among the plurality of fuses in response to an input of the defect detection information and an input of the defective address signal; Spare decoding to automatically program a defect address and select a spare line connected to the spare memory cell corresponding to the defective address among the plurality of spare memory cells when the defect address is input after the defect detection information is blocked. Including means A self repair circuit of a semiconductor memory device, wherein the repair operation corresponding to the defective memory cell is performed simultaneously with the normal memory cell test of the semiconductor memory device. 5. The apparatus of claim 4, wherein the spare decoding means comprises: a first node precharged to a predetermined level, a plurality of fuses electrically connected to one side of the first node, a programmable voltage and the first voltage; A program voltage supply means connected between one node and supplying a programming voltage to the first node in response to defect detection information of the memory cell, and a power supply voltage other than that of the plurality of fuses and the programming voltage. And a program current passing means connected to and fused fuses corresponding to the defective address in response to an input of a defective address signal. The self repair of a semiconductor memory device as claimed in claim 4 or 5, wherein the plurality of fuses are electrical fuses formed of a bottleneck bit line poly and fused by a high current flow between one side and the other side. Circuit. A semiconductor memory device having a plurality of normal memory cells and a plurality of spare memory cells, the semiconductor memory device comprising: outputting a repair enable signal in response to a repair mode and simultaneously receiving an address signal of a normal memory cell of the semiconductor memory device; A defective memory cell detecting means for sequentially supplying the defective memory cells to detect defective memory cells and generating defect detection information corresponding thereto, and generating a repair control pulse in response to the defect detection information and the spare selection signal, and generating a repair control pulse. A plurality of spare decoding means for fuse-fusing the detected defective address by melting the fuses corresponding to the defective address among the plurality of fuses which are electrically melted in response; and the plurality of spare decoding means in response to the defect detection information. At least one of the spare decoding means And a selection means for generating a spare selection signal for selecting me and shifting the generated spare selection signal sequentially in response to activation of at least one of the repair control pulses respectively output from the plurality of spare decoding means. A self repair circuit of a semiconductor memory device. 8. The apparatus of claim 7, wherein each of the plurality of spare decoding means comprises: a first node precharged to a predetermined level, a plurality of electrically stable fuses having one side connected to the first node, and Pulse generation means for generating a repair control pulse in response to the defect detection information and the spare selection signal of the memory cell, and connected between a programming voltage and the first node to the first node in response to the generated repair control pulse. A program voltage supply means for supplying a programming voltage, and a program current connected to the other side of the plurality of fuses and a power supply voltage that is less than the programming voltage and fused fuses corresponding to the fault address in response to input of a fault address signal. A self repair circuit of a semiconductor memory device, characterized by comprising passing means. The self-repairing device of claim 7 or 8, wherein the plurality of fuses are electrical fuses formed of a bottleneck bit line poly and fused by a high current flow between one side and the other side. Circuit. 9. The self repair circuit of claim 8, wherein the first nodes of each of the plurality of spare decoding means are connected to a spare memory cell select line for activating the spare memory cell. 8. The apparatus of claim 7, wherein the selecting means comprises: a shift register for each output node connected to each input node of the plurality of spare decoding means and for shifting a flag pulse input in response to an input of a latch pulse and a repair control pulse; And pulse generating means for generating the flag pulse and generating a latch pulse in response to the defect detection information. 12. The self repair of a semiconductor memory device according to claim 11, further comprising an alarm signal generating means for generating a non-repairable alarm signal in response to activation of a spare selection signal output from the last output node of the shift register. Circuit. 13. The self repair circuit according to claim 11 or 12, further comprising reset pulse generating means for resetting all outputs of the shift register in response to the defect detection information. A semiconductor memory device having a plurality of normal memory cells and a plurality of spare memory cells, comprising: sequentially supplying an address signal for accessing a normal memory cell located in the semiconductor memory device to detect a defective memory cell and A spare column mode selection for outputting a spare row mode selection signal in response to only at least two consecutive consecutive times by detecting a continuity of generation of the defect detection information and a defect memory cell detecting means for generating defect detection information and a defect address signal; A repair mode selection means for signal transition, a repair low control pulse in response to the defect detection information, a spare row selection signal, and a spare low mode selection signal, and a plurality of fuses electrically electrically fused in response to the repair column control pulse Corresponds to the defective address A plurality of spare row decoders that fuse the fuses to automatically program the detected defect address, and select a spare word line corresponding to the defect address upon input after the blocking of the defect detection information; The repair column control pulse is generated in response to the spare column selection signal and the spare column mode selection signal, and the fuse corresponding to the defective address is fused among the plurality of fuses electrically electrically fused in response to the repair column control pulse. A plurality of spare column decoders for automatically programming a defective address and selecting a spare word line corresponding to the defective address upon input after the blocking of the defect detection information, and the plurality of spares in response to the defect detection information. At least one of the low decoders A spare row decoder for generating a spare row select signal for selecting me and shifting the generated spare row select signal sequentially in response to activation of at least one of the repair row control pulses respectively output from the plurality of spare row decoders; At least one of a repair column control pulse generated by a selection means and a spare column selection signal for selecting at least one of the plurality of spare column decoders in response to the defect detection information, and output from the plurality of spare column decoders, respectively; And a spare column decoder selecting means for shifting the generated spare column selection signal and sequentially activating the generated spare column selection signal in response to the activation of the self repair circuit. 15. The apparatus of claim 14, wherein the repair mode selecting means comprises: a shift register for generating shifted error pulses by latching and sheeting the generated defect detection information by a control clock generated in synchronization with a row address strobe signal; A detection means for detecting a successive defect column address by comparing the detected defect detection pulse with the shifted error pulse, and a logical combination of an output of the detection means and a final output of the spare row decoder selection means and the spare column decoder selection means. A self repair circuit of a semiconductor memory device for selectively generating a low mode selection signal and a spare column mode selection signal. 15. The memory device of claim 14, wherein each of the plurality of spare row decoders comprises: a first node precharged to a predetermined level; a plurality of electrically stable fuses having one side connected to the first node; Pulse generating means for generating a repair low control pulse in response to defect detection information of the cell, the spare selection signal, and the spare low mode selection signal, and connected between a programming voltage and the first node and responding to the generated repair control pulse. Program voltage supply means connected between the first node and supplying a programming voltage to the first node in response to the generated repair control pulse, and a power supply that is more familiar than the other side of the plurality of fuses and the programming voltage. A fuse that is connected to a voltage and that fuses fuses corresponding to the defective address in response to input of the defective address signal. A semiconductor memory device, characterized in that the configuration program to the current passing circuit means for the self-repair. 17. The self-repairing semiconductor memory device of claim 15 or 16, wherein the plurality of fuses are electrical fuses formed of a bottleneck bit line poly and high current flows between one side and the other side. Circuit.