KR100527591B1 - Semi-conductor memory device - Google Patents

Abstract

The present invention relates to Rambus DRAM, Synclink DRAM and D.D. The present invention relates to a semiconductor memory device which performs a high-speed test operation, and more particularly, wherein the number of data input / output pads that are activated by participating in a read operation in the DA mode in which only core cells are tested and defective cells are repaired. By reducing the use in half, the present invention relates to a semiconductor memory device that realizes a high speed test operation and a reduction in test cost by doubling the maximum number of dies that can be tested by input / output channels of a fixed test system.

Description

Semi-conductor memory device

The present invention relates to semiconductor memory devices such as Rambus DRAM, Synchlink DRAM, and D.D. (Double Data Rate). The present invention relates to a semiconductor memory device that realizes high-speed test operation and reduced test cost by doubling the test capacity by halving the number of data inputs and outputs.

In general, the DA mode is used for the purpose of testing only core cells for Rambus DRAMs operating at 400 to 800 MHz and repairing failed cells.

The maximum test parameters (test parameter_max :) can be tested at the same time by the prober and burn-in test equipment having 144 channels of input / output channels when testing Rambus DRAM having an input / output pad number of 18. The number of input and output channels of the system, calculated by the number of inputs and outputs of the die, is limited to eight dies.

As can be seen from the above calculation of the test parameter value (the number of input and output channels of the system ÷ the number of inputs and outputs of the die), the maximum number of inputs and outputs of the die should be reduced for the fixed number of system input and output channels. The parameter value is increased.

The conventional semiconductor memory device reduces the number of input / output dies used during the test operation by controlling the read data to be transferred directly from the output driver to the data input / output pad (DQ PAD) during the read operation. There was a limit.

FIG. 1 is a block diagram showing a read data path in a conventional semiconductor memory device. Each of the corresponding data signals RDi <7: 0> and RDj <7 read from the memory cell by the operation control signals test_DSTB and bias_DTM is shown in FIG. (0>) are loaded into the respective data shifter registers 10 and 12, and the read data signals eReadi / oReadi and eReadj / oReadj loaded into the respective data shifter registers 10 and 12 are control clock signals. As the (test_clkR) toggles, it is configured to pass directly to the data input / output pads DQi PAD and DQj PAD via the respective output drivers 20 and 22.

At this time, the operation control signal (bias_DTM: bias drive test mode) is a bias signal applied to the pipe input of the first shifting part of each of the data shift registers 10 and 12 and a ground potential for operation control in the normal mode. It is fixed to be applied.

FIG. 2 is a block diagram of the data shift registers 10 and 12 shown in FIG. 1, and receives read data signals corresponding to odd and even addresses, respectively, and outputs the output signal of the previous stage to each pipe input. Consists of a plurality of shifting units that perform a right-shfting operation by the operation control signal test_DSTB and the clock control signal test_clkR, and correspond to odd and even addresses, respectively, for operation control in the normal mode. As a pipe input signal of the first shifting part receiving the read data signal, a bias control signal bias_DTM having a ground potential is applied.

Thus, valid read data is transmitted to the data output pad during the time when the four test control clock signals are applied, and then the logic low signal is transmitted thereafter.

FIG. 3 is a timing diagram of an operation during a read test of the semiconductor memory device having the configuration shown in FIG. 1, and is shown in (a) and (b) of FIG. Since the data read operation as described above occurs at the same time, the maximum number of dies testable by one test operation is limited to eight as it is.

As described above, in the semiconductor memory device according to the related art, the test cost and the test time become large due to the maximum number of dies limited during the test operation, resulting in a problem of low efficiency.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use an input / output pad that is used during a read operation in a DA mode (an operation mode in which only core cells are tested and repaired for defective cells). It is possible to provide a semiconductor memory device that maximizes efficiency by reducing the required test time and cost by half by doubling the number of dies that can be tested with a fixed system input / output channel by halving the number of times.

In order to achieve the above object, the semiconductor memory device according to the present invention receives the first and second data signals read from the memory cells, respectively, and shifts the first and second data shifts by shifting them according to the toggle of the control clock signal. Registers,

First and second output drivers driven under the control of the control clock signal to transfer respective read data signals received from the first and second data shift registers to first and second output pads, respectively;

The first output driver is connected between the first output pad and the first output pad and is always turned on regardless of whether or not it enters a mode (DA mode) for testing only core cells and performing a repair operation on a defective cell. First switching means for transferring one read data to a first output pad;

A second device connected between the second output driver and the second output pad to prevent the second read data from being transferred to the second output pad when the DA mode entry determination signal is applied in an activated state. 2 switching means;

The first data shift register receives a second read data signal generated from the second data shift register as a first pipe input terminal when the first data shift register enters the DA mode, and sequentially shifts the first read data signal after the first read data signal is transferred. It is done.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a read data path in the semiconductor memory device according to the present invention, wherein the first and second read data signals RDi <7: 0> and RDj <7 respectively read from memory cells (not shown). : 0>) under the control of the first and second data shift registers 14 and 16, which are shifted according to the toggling of the clock control signal test_clkR, and the clock control signal test_clkR. Each of the read data signals RDi <7: 0> and RDj <7: 0>, which are driven and transferred from the first and second data shift registers 14 and 16, may be configured to receive the first and second output pads DQi PAD. And between the first and second output drivers 24 and 26, which respectively transmit to DQj PAD, between the first output driver 24 and the first output pad DQi PAD, and test only core cells. Regardless of whether or not it enters the mode for performing the repair operation on the defective cell (hereinafter referred to as 'DA mode') First switching means 30 which is turned on to transfer the first read data RDi <7: 0> to a first output pad DQi PAD, the second output driver 26 and the second It is connected between the output pads DQj PAD, and when the DA mode entrance determination signal DAmode is applied to the active state (logic high), the second read data RDj <7: 0> is turned off. And second switching means 32 to prevent delivery to the second output pad DQj PAD.

Here, the first data shift register 14 receives the second read data signal RDj <7: 0> generated from the second data shift register 16 to the first pipe input terminal when entering the DA mode. After receiving the first read data signal (RDi <7: 0>) is configured to be shifted in order to transfer.

The first switching means 30 includes an NMOS transistor to which a power supply voltage is applied to the gate terminal, and a transfer gate MT1 including a PMOS transistor connected to the ground terminal.

The second switching means 32 is a PMOS transistor to which the DA mode entrance determination signal DAmode is applied to the gate terminal and an NMOS transistor to which an inversion signal of the DA mode entrance determination signal DAmode is applied to the gate terminal. It is composed of a transfer gate MT2.

FIG. 5 is a block diagram of the first data shift register 14 shown in FIG. 4. The clock control is performed by receiving read data signals RD <0> to RD <7> corresponding to respective addresses. A plurality of shifting parts 40 to 47 which transmit to a pipe input end of the rear end according to the toggling of the signal test_clkR; The DA mode entry determination signal DAmode and the normal mode control bias signal bias_DTM are inputted and a combination of these signals causes the second read data signal RDj received from the second data shift register 16 to enter the DA mode. <7: 0>) is output to the pipe input terminal of the first shifting unit (in the drawing, 46 and 47), and the normal mode control bias signal (bias DTM) in the normal mode. The control unit 50 for outputting the ground potential of the first shifting unit 46, 47 to the pipe input terminal is configured.

The control unit 50 receives the inverted signal of the DA mode entrance determination signal DAmode and the normal mode control bias signal bias_DTM and inputs and combines the first logic element AND1 and the DA mode entry determination signal ( A second logic element AND2 for receiving and combining DAmode and the second read data signal RDj <7: 0>, and an output signal of the first and second logic elements AND1 and AND2. It consists of the 3rd logic element OR1 which receives and combines.

Hereinafter, the read operation in the DA mode in the present invention having the above configuration will be described in detail with reference to the accompanying drawings.

First, the read data signal output from the adjacent second data shift register 16 is not fixed to the pipe input terminals of the first shifting sections 46 and 47 of the first data shift register 14 to ground potential. The read data signal RDj <7: 0> to be output to the second output pad DQj PAD in the normal mode by toggling the clock control signal test_clkR four more periods than the conventional case by receiving (eReadj, oReadj). The output is bypassed to the first output pad DQi PAD. Therefore, it is possible to reduce the number of required input and output pads in half, and accordingly, it is a key principle of the present invention to make it possible to test a product having a length of 18 data with a product having a length of 9 data.

Referring to FIG. 5, when entering into the DA mode (ie, when DAmode = 'H' is applied), the controller 50 is adjacent to a pipe input terminal of each of the first shifting units 46 and 47. 'EReadj' and 'oReadj', which are output signals of the second data shift register, are transferred.

Thereafter, the 'eReadj' and 'oReadj' signals are output to the first output pad DQi PAD while being shifted to the right as the clock control signal test_clkR is toggled. Therefore, the first read data signal RDi <7: 0> is output to the first output pad DQi PAD during the first four cycle clocks, and the second read data signal RDj <7: 0> during the next four cycle clocks. ) Is output to the first output pad DQi PAD so that the number of input / output pads used for the read test in the DA mode can be reduced to 1/2.

On the other hand, in the normal mode (when DAmode = 'L' is applied), the output signal of the controller 50 becomes the normal mode control bias signal bias_DTM, so that the pipes of the first shifting parts 46 and 47 are piped. ) Ground potential is transmitted to the input terminal to perform the same operation as the existing case.

In addition, the first transfer gate MT1 constituting the first switching means 30 is always turned on regardless of the mode, in order to satisfy the specification of the input capacitance change amount ΔCi of the package pin. The second transfer gate MT2 constituting the means 32 performs an operation of completely preventing transmission of the read data signal RDj <7: 0> to the second output pad DQj PAD when entering the DA mode.

FIG. 6 is a timing diagram of an operation during a read test of a semiconductor memory device according to an exemplary embodiment of the present invention. As shown in (b), a single output pad DQi PAD according to toggling of a clock control signal shown in (a) is shown. In this figure, two read data signals RDi <7: 0> and RDj <7: 0> are sequentially shifted and output.

In the present invention, no additional control signal is required, and only the clock control signal test_clkR may be increased by 4 cycles from 6 cycles to 10 cycles when the read data signal is output.

As described above, the same read test operation is performed by reducing the number of data input / output pads from x18 to x9.

As described above, according to the semiconductor memory device of the present invention, the number of output dies used in the DA mode read operation is reduced by half, so that the maximum number of dies that can be tested with the input and output channels of the fixed test system is reduced. It is possible to increase the doubling, resulting in a very excellent effect of reducing the test cost and test time accordingly.

In addition, an output pad that is not used during the data read operation can be used for other purposes during that time, thereby increasing the efficiency of the device.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, changes, etc. fall within the scope of the claims Should be seen.

1 is a block diagram showing a read data path in a conventional semiconductor memory device.

FIG. 2 is a block diagram of the data shift register shown in FIG.

3 is an operation timing diagram of a read test of the semiconductor memory device having the configuration shown in FIG. 1;

4 is a block diagram showing a read data path in the semiconductor memory device according to the present invention.

5 is a block diagram illustrating the configuration of the first data shift register shown in FIG.

6 is an operation timing diagram during a read test of a semiconductor memory device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 12, 14, 16: Data Shift Registers 20, 22, 24, 26: Output Driver

30, 32: switching means 40 to 47: shifting part

50: control unit

Claims (5)

First and second data shift registers receiving first and second read data signals respectively read from the memory cells and shifting the shifted data according to the toggle of the clock control signal; First and second output drivers driven under the control of the clock control signal to transfer respective read data signals received from the first and second data shift registers to first and second output pads, respectively; The first output driver is connected between the first output pad and the first output pad and is always turned on regardless of whether or not it enters a mode (DA mode) for testing only core cells and performing a repair operation on a defective cell. First switching means for transferring one read data to a first output pad; A second device connected between the second output driver and the second output pad to prevent the second read data from being transferred to the second output pad when the DA mode entry determination signal is applied in an activated state. 2 switching means; The first data shift register receives a second read data signal generated from the second data shift register as a first pipe input terminal when the first data shift register enters the DA mode, and sequentially shifts the first read data signal after the first read data signal is transferred. A semiconductor memory device. The method of claim 1, The first data shift register includes: a plurality of shifting units configured to receive read data signals corresponding to respective addresses and transfer the read data signals to a pipe input terminal at a later stage according to a toggle of a clock control signal; When the DA mode entry determination signal and the normal mode control bias signal are inputted, these signals are combined to output the second read data signal received from the second data shift register to the pipe input terminal of the first shifting unit when the DA mode enters. And a control unit for outputting the ground potential of the normal mode control bias signal to the pipe input terminal of the first shifting unit in the mode. The method of claim 2, The control unit may include: a first logic element configured to receive and combine the inverted signal of the DA mode entrance determination signal and the normal mode control bias signal; A second logic element receiving and DA-combining the DA mode entry determination signal and the second read data signal; And a third logic element configured to receive and output the output signals of the first and second logic elements. The method of claim 1, And the first switching means uses a transfer gate comprising an NMOS transistor to which a power supply voltage is applied to a gate terminal and a PMOS transistor connected to a ground terminal. The method of claim 1, And the second switching means uses a transfer gate comprising a PMOS transistor to which the DA mode entry determination signal is applied to the gate end and an NMOS transistor to which an inverted signal of the DA mode entry determination signal is applied to the gate end. Memory device.