KR100535048B1 - Semi-conductor memory device - Google Patents

Abstract

The present invention relates to Rambus DRAM, Synclink DRAM and D.D. The present invention relates to a semiconductor memory device which performs a high-speed test operation, and more particularly, wherein the number of data input / output pads that are activated by participating in a read operation in the DA mode in which only core cells are tested and defective cells are repaired. By reducing the use in half, the present invention relates to a semiconductor memory device that realizes a high speed test operation and a reduction in test cost by doubling the maximum number of dies that can be tested by input / output channels of a fixed test system.

Description

Semi-conductor memory device

The present invention relates to semiconductor memory devices such as Rambus DRAM, Synchlink DRAM, and D.D. (Double Data Rate). The present invention relates to a semiconductor memory device that realizes high-speed test operation and reduced test cost by doubling the test amount by halving the number of data inputs and outputs.

In general, the DA mode is used for the purpose of testing only core cells for Rambus DRAMs operating at 400 to 800 MHz and repairing failed cells.

The maximum test parameters (test parameter_max) that can be tested by the prober and burn-in test equipment having 144 channels of input and output channels when testing Rambus DRAM having an input / output number of × 18. The number of dies is calculated by the number of input and output channels of the system ÷ the number of inputs and outputs of the die).

As can be seen from the above calculation of the test parameter value (the number of input and output channels of the system ÷ the number of inputs and outputs of the die), the maximum number of inputs and outputs of the die should be reduced for the fixed number of system input and output channels. The parameter value is increased.

The conventional semiconductor memory device reduces the number of input / output dies used during the test operation by controlling the read data to be transferred directly from the output driver to the data input / output pad (DQ PAD) during the read operation. There was a limit.

FIG. 1 is a block diagram showing a read data path in a conventional semiconductor memory device, in which respective data signals RDi <7: 0> and RDj <7: 0, which are read from a memory cell by an operation control signal test_DSTB, are shown in FIG. &Quot; ) Is configured to be passed directly to the data input / output pads DQi PAD and DQj PAD via the respective output drivers 20 and 22.

FIG. 2 is a timing diagram of an operation during a read test of the semiconductor memory device having the configuration shown in FIG. 1. As shown in FIGS. 1A and 2B, the data read operation has 18 data of the Rambus DRAM. Since the same occurs at the same time in both the input and output pads, the maximum number of dies that can be tested by one test operation is limited to eight as it is.

As described above, the semiconductor memory device according to the related art has a problem in that the efficiency decreases due to the increase in test cost and test time due to the limited maximum number of dies.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use an input / output pad that is used during a read operation in a DA mode (an operation mode in which only core cells are tested and repaired for defective cells). It is possible to provide a semiconductor memory device that maximizes efficiency by reducing the required test time and cost by half by doubling the number of dies that can be tested with a fixed system input / output channel by halving the number of times.

In order to achieve the above object, the semiconductor memory device according to the present invention receives the first and second data signals read from the memory cells, respectively, and shifts the first and second data signals by the respective control clock signals to the output driver. A data shift register;

The operation mode (DA mode) determination signal, which is connected to the output driver and tests only core cells and performs repair on defective cells, is switched when the signal is inactivated to transfer a corresponding data signal to each output pad. 1 switching means;

Second switching means connected to the output driver in parallel with a first switching means and switched when the DA mode determination signal is applied in an activated state;

Selecting means for selecting the first and second data signals transmitted through the second switching means by a selection control signal applied from the outside and transferring only one signal to a corresponding output pad;

And an activation control means for generating a respective control clock signal for controlling whether the first and second data shift registers are activated by combining an external clock signal, the DA mode determination signal, and the selection control signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a read data path in a semiconductor memory device according to an embodiment of the present invention, in which respective data signals RDi <7: 0> and RDj <7: 0> read from a memory cell are inputted to control the respective data signals. First and second data shift registers 10 and 12 that are shifted by clock signals tclk1 and tclk2 and transferred to respective output drivers 20 and 22; The operation mode (hereinafter referred to as 'DA mode') determination signal DAmode, which is connected to each of the output drivers 20 and 22 and tests only core cells and performs repair on defective cells, is deactivated (logic). Low: The first switching means 30 is switched when applied to 'L' to transfer the corresponding data signal (RDi <7: 0> or RDj <7: 0>) to each output pad (DQi PAD, DQj PAD) )and; A second switch connected to each of the output drivers 20 and 22 in parallel with the first switching means 30 and switched when the DA mode determination signal DAmode is applied to an active state (logic high: 'H'). Switching means 32; A selection control signal (select) for receiving the first and second data signals RDi <7: 0> or RDj <7: 0> received through the second switching means 32 from the outside through an extra package pin. Selecting means (40) for selecting and transmitting only one signal to a corresponding output pad; Each control clock signal for controlling whether the first and second data shift registers 10 and 12 are activated by combining an external clock signal test_clkR, the DA mode determination signal DAmode, and the selection control signal select. and activation control means 50, 52 for generating (tclk1, tclk2).

The first and second switching means 30 and 32 are switched in accordance with the DA mode discrimination signal DAmode to respectively output the first and second data signals RDi <7: 0> or RDj <7: 0>. The first switching elements MT1 and MT3 and the second switching elements MT2 and MT4 are provided to each other, and the switching elements MT1 to MT4 are all composed of a transmission gate.

In the figure, the selecting means 40 is constituted by a multiplexer.

The activation control means (50, 52) includes a first logic operation unit (50) for generating a clock control signal (tclk1) for controlling whether the first data shift register (10) is activated; And a second logic operation unit 52 for generating a clock control signal tlklk2 for controlling whether the second data shift register 12 is activated.

In this case, the first logic operation unit 50 includes: a first logic element AND1 for receiving and combining the inverted signal of the DA mode determination signal DAmode and the external clock signal test_clkR; A second logic element AND2 for receiving and inverting the inversion signal of the selection control signal select and the DA mode determination signal DAmode; And a third logic element OR1 that receives and outputs the output signals of the first and second logic elements AND1 and AND2.

On the other hand, the second logic operator 52 has the same configuration as the first logic operator 50, and applies the inverted signal instead of the select control signal (select) that is an input signal of one side of the AND gate, which is the second logic element. There is a difference in configuration.

Hereinafter, the read operation in the DA mode in the present invention having the above configuration will be described in detail with reference to the accompanying drawings.

First, since the determination signal DAmode is applied at logic high 'H' in the DA mode, the two transfer gates MT1 and MT2 constituting the first switching means 30 are turned off, and the second Only two transfer gates MT3 and MT4 constituting the switching means 32 are turned on.

Accordingly, the data signals RDi <7: 0> and RDj <7: 0> output from the respective output drivers 20 and 22 are passed to the corresponding data output pad DQi PAD via the multiplexer as the selection means 40. In this case, the select control signal (select) applied to the multiplexer is a signal applied from the outside through an extra unused package pin. If the signal (select) is 'logic low', the data signal RDi <7 : 0> is transmitted to the DQi PAD. On the contrary, if the select control signal is 'logic high', another data signal RDj <7: 0> is transmitted to the DQi PAD.

If the selection control signal (select) is applied as 'logic low' and the data signal (RDi <7: 0>) is selected and transferred to the DQi PAD, the valid data signal flows to the remaining output pad DQj PAD. As a result, the output pad DQj PAD can be used for other purposes such as an address input pin during this time.

On the other hand, when the external clock signal test_clkR toggles, the first and second data shift registers 10 and 12 shift the loaded data to transfer them to the data output pads. A circuit for controlling the clock signal is required so that this operation is performed by the activation control means (50, 52).

That is, when the selection control signal (select) is applied as 'logic low', the control clock signals generated from the activation control means (50, 52) are respectively tclk1 = 'logic high', tclk2 = 'logic low' Only the first data shift register 10 is activated and operated, and the second data shift register 12 is not activated.

On the other hand, when the selection control signal (select) is applied as 'logic high', the control clock signals generated from the activation control means (50, 52) become tclk1 = 'logic low' and tclk2 = 'logic high', respectively. Only the second data shift register 12 is activated and operated. In this case, the first data shift register 10 is not activated and does not operate.

FIG. 4 is a timing diagram of an operation during a read test of the semiconductor memory device having the configuration shown in FIG. 3. The read data signal RDi <7: 0>, RDj <7: 0> is loaded into each of the data shift registers 10 and 12, and then read data signals RDi <7: 0> and RDj <7 in response to toggling of the external clock control signal test_clkR. : 0>) is transferred to the data output pad, and only one of the two data shift registers 10 and 12 is activated by the two clock control signals tclk1 and tclk2 generated by being controlled according to the selection control signal select. In the 'T1' section in which the selection control signal select is logic low, the first read data signal RDi <7: 0> and the 'T2' section in which the selection control signal select is logic high. The second read data signal RDj <7: 0> is connected to (a) through the same output pad DQi PAD. A it is output as.

Therefore, ten clock signal toggles are required in one read operation, and the third to sixth clocks are used to transfer the first read data signal RDi <7: 0> to the data output pad DQi PAD. The seventh to tenth clocks are used to transfer the second read data signal RDj <7: 0> to the data output pad DQi PAD.

As described above, the same read test operation is performed by reducing the number of data input / output pads from x18 to x9.

As described above, according to the semiconductor memory device of the present invention, the number of output dies used in the DA mode read operation is reduced by half, so that the maximum number of dies that can be tested with the input and output channels of the fixed test system is reduced. It is possible to increase the doubling, resulting in a very excellent effect of reducing the test cost and test time accordingly.

In addition, an output pad that is not used during the data read operation can be used for other purposes during that time, thereby increasing the efficiency of the device.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications, changes, etc. fall within the scope of the claims Should be seen.

1 is a block diagram showing a read data path in a conventional semiconductor memory device.

FIG. 2 is an operation timing diagram during a read test of the semiconductor memory device having the configuration shown in FIG. 1. FIG.

3 is a block diagram showing a read data path in the semiconductor memory device according to the present invention.

4 is an operation timing diagram of a read test of the semiconductor memory device having the configuration shown in FIG.

<Description of the symbols for the main parts of the drawings>

10, 12: data shift register 20, 22: output driver

30, 32: switching means 40: selection means

50, 52: activation control means

Claims (7)

First and second data shift registers receiving first and second data signals respectively read from the memory cells, shifted by the respective control clock signals, and transferred to the output driver; The operation mode (DA mode) determination signal, which is connected to the output driver and tests only core cells and performs repair on defective cells, is switched when the signal is inactivated to transfer a corresponding data signal to each output pad. 1 switching means; Second switching means connected to the output driver in parallel with a first switching means and switched when the DA mode determination signal is applied in an activated state; Selecting means for selecting the first and second data signals transmitted through the second switching means by a selection control signal applied from the outside and transferring only one signal to a corresponding output pad; And an activation control means for generating a respective control clock signal for controlling whether the first and second data shift registers are activated by combining an external clock signal, the DA mode determination signal, and the selection control signal. Memory device. The method of claim 1, And the first and second switching means include first and second switching elements which are switched in accordance with the DA mode determination signal to transfer first and second data signals, respectively. The method of claim 2, And the first and second switching elements comprise transfer gates. The method of claim 1, And said selecting means comprises a multiplexer. The method of claim 1, The activation control means includes a first logic operation unit for generating a clock control signal for controlling whether the first data shift register is activated;  And a second logic calculator configured to generate a clock control signal for controlling whether the second data shift register is activated. The method of claim 5, The first logic operation unit comprises: a first logic element for receiving and combining an inverted signal of the DA mode determination signal and an external clock signal; A second logic element which receives and inverts the inversion signal of the selection control signal and the DA mode determination signal; And a third logic element for receiving and outputting the output signals of the first and second logic elements. The method of claim 5, The second logic unit comprises: a first logic element for receiving and combining the inverted signal of the DA mode determination signal and an external clock signal; A second logic element which receives and selects the selection control signal and the DA mode determination signal; And a third logic element for receiving and outputting the output signals of the first and second logic elements.