KR100238223B1 - Race control circuit for semiconductor memory device - Google Patents

Abstract

The present invention provides a race control circuit of a semiconductor memory device. The race control circuit according to the present invention includes a master signal generator for generating a master signal in response to a high voltage signal input through an input pin, a control signal generator for generating a control signal in response to predetermined signals; And a race control clock generator for receiving a plurality of input signals input through the plurality of input pins in response to the master signal and the control signal and generating a plurality of race control clocks, and a plurality of transfer paths. And a race controller for transmitting an internal signal through a transfer path selected from among the plurality of transfer paths in response to a plurality of race control clocks. Therefore, when the race control circuit according to the present invention is employed in a semiconductor memory device, particularly when the race control circuit is applied to the main internal signals that have a decisive influence on the internal operation of a sensing related signal lamp, the predetermined signals are applied through an input pin in a package state. The race of the internal signals can be adjusted. Accordingly, it is possible to effectively screen the defects related to the race during the package test, and ultimately improve the characteristics and reliability of the product.

Description

Race control circuit for semiconductor memory device

The present invention relates to a race control circuit of a semiconductor memory device.

The present invention relates to a race control circuit of a semiconductor memory device capable of adjusting a race of major internal signals having a decisive effect on internal operation by applying predetermined signals through an input pin in a package state.

In recent years, semiconductor devices have been diversified in function in order to accommodate various demands of system developers, and the operation speed has been increased. In particular, the semiconductor memory device has a faster acceptance rate for such a high performance demand, and the operating speed is faster, while the chip size is decreasing. Accordingly, the problem of race control of internal operation signals has a great effect on the operation of the semiconductor device. Its importance is increasing day by day. In particular, the normal sensing operation of the memory cell data is determined by the internal signal controlling the sensing time and the capacity of the cell determined through the manufacturing process. Therefore, in relation to such a race, in the case of a specific memory cell, a failure does not occur in normal operation under normal conditions, but a failure may occur depending on an external environment connected to a semiconductor memory device, data conditions of a peripheral memory cell, and the like. Therefore, in order to eliminate such defects, it would be desirable to test all conditions within the product specification by strengthening race operating conditions of important signals in wafer state and package state before the semiconductor memory device product is provided to the user. However, in the conventional semiconductor memory device, a delay circuit composed of a resistor and a capacitor and a predetermined fuse are used to control the race of an internal signal, and the use of the delay circuit is determined according to whether the fuse is cut off, or a predetermined pad. There is a method of delaying a specific internal signal by applying an external signal through the signal, but there is a limitation that they are possible only in a wafer state.

Accordingly, it is an object of the present invention to provide a race control circuit of a semiconductor memory device that can control a race of major internal signals that have a decisive influence on internal operation even in a package state.

1 is a block diagram of a race control circuit according to the present invention;

FIG. 2 is a circuit diagram of a master signal generating means of the race control circuit shown in FIG.

3 is a circuit diagram of a control signal generating means of the race adjustment circuit shown in FIG.

4 is a circuit diagram of a race control clock generating means of the race adjustment circuit shown in FIG.

5 is a circuit diagram of a race control means of the race adjustment circuit shown in FIG.

6 is an operation timing diagram of the race adjustment circuit shown in FIG.

7 is a truth table showing the operation of the race control clock generating means shown in FIG.

The race control circuit according to the present invention for achieving the above object, the master signal generating means for generating a master signal in response to a high voltage signal input through an input pin, and predetermined first, second, and third signals Control signal generation means for generating a control signal in response to the race, and a race control clock for generating a plurality of race control clocks in response to the master signal and input signals input through another plurality of input pins in response to the control signal. Means and a race control means including a plurality of transfer paths and transferring an internal signal through a transfer path selected from the plurality of transfer paths in response to the plurality of race control clocks.

The high voltage signal is preferably a signal of 7V or more. The predetermined first signal is externally input Signal generated by a (low address strobe) signal, and the predetermined second signal Signal generated by a (column address strobe) signal, and the third signal This signal is generated by the (light enable) signal. Any one of the plurality of transmission paths of the race control means may transmit the internal signal without delay, and the remaining transmission paths may delay and transmit the internal signal by a predetermined time different from each other.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a race control circuit according to the present invention.

Referring to FIG. 1, the race control circuit according to the present invention includes a master signal generating means 1, a control signal generating means 3, a race control clock generating means 5, and a race control means 7. It is provided. The master signal generating means 1 generates a master signal PSVA0 in the internal signal race adjustment mode in response to a high voltage signal IN0 of 7V or higher input through an input pin such as an address pin. The control signal generating means 3 is input from the outside of the semiconductor memory device. The first signal PR generated by the (low address strobe) signal, The second signal PC generated by the (column address strobe) signal, and The control signal PFTE is generated in response to the third signal PW generated by the (light enable) signal. The race control clock generating means 5 receives signals IN1 and IN2 input through another two input pins such as an address pin in response to the master signal PSVA0 and the control signal PFTE. Generate two race control clocks (PRCC0, PRCC1, PRCC2, PRCC3). In addition, the race control means 7 includes a plurality of transfer paths, and in the chip through a transfer path selected from among the plurality of transfer paths in response to the plurality of race control clocks PRCC0, PRCC1, PRCC2, PRCC3. It carries a signal PSE. The race control circuit can be effectively applied to a sensing related circuit stage in which a race problem of a signal is important. That is, the internal signal PSE may be a bit line sensing enable signal, a column select line (CSL) signal, an input / output line sensing signal, or the like.

Hereinafter, each component of the race control circuit according to the present invention will be described in detail.

FIG. 2 is a circuit diagram of the master signal generating means of the race control circuit shown in FIG.

Referring to FIG. 2, the master signal generating means is provided with a high voltage signal IN0 of 7 V or more input through an input pin to a source, a ground voltage VSS is applied to a gate, and the source is connected to a bulk and drained. PMOS transistor MP1 connected to output node N1 for outputting the master signal PSVA0, and PMOS transistor having a source connected to the output node N1 and bulk, and having a gate and a drain connected in common. MP2) and NMOS transistor MN1 having a drain connected to the drain of PMOS transistor MP2, a power supply voltage VCC applied to a gate, and a ground voltage VSS applied to a source.

3 is a circuit diagram of the control signal generating means of the race adjustment circuit shown in FIG.

Referring to FIG. 3, the control signal generating means generates a pre control signal PWMC in response to the first signal PR, the second signal PC, and the third signal PW. A pre-control signal generating means 3a, and a delay means 3b for delaying the pre-control signal PWMW and outputting the delayed control signal PFTE.

The pre-control signal generating means 3a includes a latch 3a1 for inputting the first signal PR and the second signal PC, and the first signal PR and the third signal PW. NAND means (ND4) for receiving and performing an AND operation, an AND means (3a2) for performing an AND operation, a signal output through the output node (N2) of the latch (3a1), and an output signal of the AND means (3a2). ), The latch 3a3 for inputting the output signal of the NAND means ND4 and the first signal PR, and the signal output through the output node N3 of the latch 3a3 are inverted. Inverter means I2 for outputting the pre-control signal PWMW. The latch 3a1 is composed of two NAND means ND1 and ND2, and the NAND means ND1 receives a NAND operation by inputting the first signal PR and an output signal of the NAND means ND2. And output to the output node N2, wherein the NAND means ND2 inputs the second signal PC and the output signal of the NAND means ND1. The latch 3a3 is composed of two NAND means ND5 and ND6. The NAND means ND5 inputs an output signal of the NAND means ND4 and an output signal of the NAND means ND6. The NAND means ND6 inputs the first signal PR and an output signal of the NAND means ND5 to perform an NAND operation, and outputs the result to the output node N3.

The delay means 3b includes inverting means I3 for inverting the pre-control signal PWCBR, and noah means NR1 for receiving a fourth signal PROR and a fifth signal PCBR to perform a noah operation. And a latch 3b1 for inputting the output signal of the inverting means I3 and the output signal of the noah means NR1, and a signal output through the output node N4 of the latch 3b1. Inverting means I4 and inverting means I5 for inverting the output signal of the inverting means I4 to output the delayed control signal PFTE.

The pre-control signal PWCBR is enabled by a WCBR (Write CAS BEFORE RAS) timing pattern input from the outside of the semiconductor memory device and is disabled by the first signal PR. In addition, the control signal PFTE, in which the pre-control signal PWCBR is delayed by a predetermined time, is logically "low" by the fourth signal PROR or the fifth signal PCBR, and the control signal ( When PFTE) is disabled with a logic "low", it exits the race control mode.

4 is a circuit diagram of a race control clock generating means of the race adjustment circuit shown in FIG.

Referring to FIG. 4, the race control clock generating means includes NAND means ND9 and ND10 for inverting signals IN1 and IN2 respectively inputted through two input pins in response to the master signal PSVA0. Transmission gates TM1 and TM2 are transmission means for transmitting the output signals of the respective NAND means ND9 and ND10 in response to the control signal PFTE, and the transmission gates TM1 and TM2 are transmitted. The latches 5a and 5b for latching the received signals, and the output signals L1 and L2 and the inverted output signals L1B and L2B of the latches 5a and 5b in response to the control signal PFTE. Combination means 5c for outputting the first to fourth race control clocks PRCC0, PRCC1, PRCC2, and PRCC3 in combination. Here, the latch 5a includes inverting means I7 for inverting the signal transmitted through the transmission gate TM1 and outputting the inverted output signal L1B, and an output node of the inverting means I7. An inverting means I8 to which an input node is connected and an output node is connected to an input node of the inverting means I7, and an inverting means I9 for inverting the inverted output signal L1B and outputting the output signal L1. It is composed of The latch 5b has the same configuration as that of the latch 5a, inverting means I10 for inverting the signal transmitted through the transmission gate TM2 to output the inverted output signal L2B, and the inversion. An inverting means (I11) in which an input node is connected to an output node of the means (I10) and an output node is connected to an input node of the inversion means (I10), and the inverted output signal (L2B) is inverted to output the output signal (L2). ) Is inverted means (I12) for outputting. In addition, the decoding unit 5c performs an NAND operation to receive the output signal L1 of the latch 5a, the inverted output signal L2B of the latch 5b, and the control signal PFTE. A NAND means ND11 for outputting the two-race control clock PRCC1, an inverted output signal L1B of the latch 5a, an output signal L2 of the latch 5b, and the control signal PFTE. NAND means ND12 for performing the NAND operation to output the third race control clock PRCC2, an output signal L1 of the latch 5a, an output signal L2 of the latch 5b, and NAND means ND13 for receiving the control signal PFTE and outputting the first race control clock PRCC0, an inverted output signal L1B of the latch 5a, and the latch 5b. NAND means ND14 for receiving the inverted output signal L2B and the control signal PFTE to output the fourth race control clock PRCC3. For reference, FIG. 7 shows a truth table indicating the number of cases of the race control clocks PRCC0, PRCC1, PRCC2, and PRCC3 generated when the input signals IN1 and IN2 are input by the race control clock generating means.

5 is a circuit diagram of a race control means of the race adjustment circuit shown in FIG.

Referring to Figure 5, the race control means, three transmission paths (Pas 1, Path 2, Path 3) to which a predetermined internal signal (PSE) can be transmitted is shown, more than that, if necessary You can configure paths.

Referring to FIG. 5, the path 1 transmits a predetermined internal signal PSE without delay and outputs the internal signal PS in response to the first race control clock PRCC0, that is, a transmission gate ( TM3). The path 2 includes a delay means 7a for delaying the internal signal PSE by a predetermined time, for example, T, and the NAND means ND15 for the first and second race control clocks PRCC0 and PRCC1. The transmission gate TM4 transmits the output signal of the delay means 7a and outputs the internal signal PS in response to the result of the operation. In addition, the path 3 includes a delay unit 7b for delaying the internal signal PSE by a predetermined time, for example, 2T, and an output signal of the delay unit 7b in response to the second race control clock PRCC1. And a transmission gate TM5 outputting the internal signal PS.

Herein, the internal signal PSE is transmitted through one path selected from the three transmission paths and output as the internal signal PS according to the states of the first and second race control clocks PRCC0 and PRCC1. do. That is, when the first and second race control clocks PRCC0 and PRCC1 are logic "low" and logic "high", the transmission gate TM3 is turned on and the transmission gates TM4 and TM5 are turned off. The transfer path of the internal signal PSE becomes path1. When the first and second race control clocks PRCC0 and PRCC1 are logic "high" and logic "low", the transmission gate TM5 is turned on and the transmission gates TM3 and TM4 are turned off to thereby The transfer path of the internal signal PSE becomes path 3. In addition, when the first and second race control clocks PRCC0 and PRCC1 are all logic " high ", the transmission gates TM4 are turned on and the transmission gates TM3 and TM5 are turned off. The delivery path of PSE) becomes path 2.

6 is an operation timing diagram of a race control circuit according to the present invention shown in FIG.

Referring to the operation timing diagram of FIG. 6, a schematic operation of the race adjustment circuit shown in FIG. 1 and each component shown in FIGS. 2 to 5 will be described below.

First, when a high voltage signal IN0 of 7 V or more is applied to a predetermined input pin designated to set the race adjustment mode, the master signal PSVA0 of the race adjustment mode is logiced by the voltage distribution action in the master signal generating means shown in FIG. Enabled "high". At this time, as shown in the timing diagram of FIG. signal, Signal, and If the signals are all logic " high ", their inverted signals PR, PC and PW are all logic " low " in FIG. PWCBR maintains a logic " low " state, and control signal PFTE, which is an output signal of delay means 3b, also maintains a logic " low " state. At this time, since the transmission gates TM1 and TM2 are turned on in the race control clock generating means shown in FIG. 4, the input signals IN1 and IN2 input through the other two input pins are latched to the latches 5a and 5b. do.

Next, as shown in the timing diagram of FIG. signal, Signal, and When the signals are all logic " low ", their inverted signals PR, PC, and PW are all logic " high " The control signal PWCBR is enabled at a logic " high ", and the control signal PFTE is enabled at a logic " high " Accordingly, the input signals IN1 and IN2 latched by the latches 5a and 5b are decoded by the decoding means 5c to generate first to fourth race control clocks PRCC0, PRCC1, PRCC2, and PRCC3.

As described above, in the race control means of FIG. 5, the internal signal PSE is transmitted through any one path selected from three transfer paths according to the states of the first and second race control clocks PRCC0 and PRCC1. It is output as a signal PS.

In more detail, for example, when the input signals IN1 and IN2 are (0,0), the output signal of the latch 5a and the inverting signals L1 and L1B thereof shown in FIG. 4 are (1,0). ) And the output signal of the latch 5b and its inverted signals L2 and L2B become (1,0). Accordingly, the output signals of the decoding means 5c, that is, the first to fourth race control clocks PRCC0, PRCC1, PRCC2, and PRCC3 become (0, 1, 1, 1). Therefore, in FIG. 5, only the transmission gate TM3 is turned on and the transmission gates TM4 and TM5 are turned off, so that the path 1 is selected. That is, the internal signal PSE is output as the internal signal PS without delay through the path 1.

In addition, when the input signals IN1 and IN2 are (0,1), the output signal of the latch 5a and the inverting signals L1 and L1B thereof shown in FIG. 4 become (1,0) and the latch The output signal of (5b) and its inverted signals L2 and L2B become (0,1). Accordingly, the output signals of the decoding means 5c, that is, the first to fourth race control clocks PRCC0, PRCC1, PRCC2, and PRCC3 become (1, 0, 1, 1). Therefore, in FIG. 5, only the transmission gate TM5 is turned on and the transmission gates TM3 and TM4 are turned off, so that the path 3 is selected. That is, the internal signal PSE is delayed by the delay time of the delay means 7b through the path 3, for example, 2T, and output as the internal signal PS.

In addition, when the input signals IN1 and IN2 are (1,0), the output signal of the latch 5a and its inverted signals L1 and L1B shown in FIG. 4 become (0,1) and the latch The output signal of (5b) and its inverted signals L2 and L2B become (1,0). Accordingly, the output signals of the decoding means 5c, that is, the first to fourth race control clocks PRCC0, PRCC1, PRCC2, and PRCC3 become (1, 1, 0, 1). Therefore, in FIG. 5, only the transmission gate TM4 is turned on and the transmission gates TM3 and TM5 are turned off, so that the path 2 is selected. That is, the internal signal PSE is delayed by the delay time of the delay means 7a, for example, T, through the path 2 and output as the internal signal PS.

In addition, when the input signals IN1 and IN2 are (1,1), the first to fourth race control clocks PRCC0, PRCC1, PRCC2, and PRCC3 become (1,1,1,0). Even in this case, since only the transmission gate TM4 is turned on and the transmission gates TM3 and TM5 are turned off in FIG. 5, the path 2 is selected.

In other words, the race of the internal signal PSE may be controlled by entering the race control mode in the package state of the semiconductor memory device and changing the input signals IN1 and IN2. That is, the delay time of the internal signal PSE may be adjusted. In FIG. 5, the paths 1, 2, 3 are configured to be selected by the first and second race control clocks PRCC0 and PRCC1, but it is obvious that various modifications are possible.

In addition, as shown in the timing diagram of FIG. The signal is logical "low" With the signal logic "high" Toggling the signal to logic " low " causes the signal PROR or PCBR shown in FIG. 3 to be logic " high ", thereby disabling the control signal PFTE to logic " low " You exit the mode.

As described above, the present invention has been limited to one embodiment, but not limited thereto, and it is obvious that various modifications to the present invention can be made by those skilled in the art within the scope of the spirit of the present invention. .

Therefore, when the race control circuit according to the present invention is employed in a semiconductor memory device, in particular, when the race control circuit is applied to main internal signals that have a decisive influence on the internal operation of a sensing-related signal lamp, predetermined input signals IN1 in the package state are inputted through the input pins. By applying IN2), the race of the main internal signals can be easily adjusted. Accordingly, during the package test, all the conditions within the specification can be easily tested while adjusting the race of the main internal signals, and the defects related to the race can be effectively screened.

Claims (12)

Master signal generating means for generating a master signal in response to a high voltage signal input through an input pin; Control signal generating means for generating a control signal in response to the predetermined first, second, and third signals; Race control clock generating means for receiving input signals input through another plurality of input pins in response to the master signal and the control signal and generating a plurality of race control clocks; Comprising a plurality of transfer paths, in response to the plurality of race control clock race control means for transmitting an internal signal through a transfer path selected from the plurality of transfer paths, characterized in that the race control of the semiconductor memory device Circuit. 2. The race control circuit of claim 1, wherein the high voltage signal is a signal of 7V or more. The method of claim 1, wherein the predetermined first signal is externally input Signal generated by a (low address strobe) signal, and the predetermined second signal Signal generated by a (column address strobe) signal, and the third signal And a signal generated by a (write enable) signal. The master signal generating unit of claim 1, wherein the master signal generating unit is configured to apply the high voltage signal input through the input pin to a source, apply a ground voltage to a gate, connect the source to a bulk, and output a drain from the master signal. A first PMOS transistor connected to an output node, a second PMOS transistor whose source is connected to the output node and the bulk, and a gate and a drain are commonly connected, and a drain is connected to the drain of the second PMOS transistor and the gate And an NMOS transistor having a power supply voltage applied thereto and a ground voltage applied to the source. 2. The apparatus of claim 1, wherein the control signal generating means comprises: pre-control signal generating means for generating a pre-control signal in response to the predetermined first, second, and third signals; And delay means for outputting the delayed control signal. The method of claim 5, wherein the predetermined first signal is externally input Signal generated by a (low address strobe) signal, and the predetermined second signal Signal generated by a (column address strobe) signal, and the third signal And a signal generated by a (write enable) signal. 6. The apparatus of claim 5, wherein the pre-control signal generating means comprises: a first latch for inputting the first signal and the second signal, an end means for receiving the first signal and the third signal and performing an end operation; NAND means for performing a NAND operation to receive a signal output through the output node of the first latch and the output signal of the end means, a second latch for inputting the output signal and the first signal of the NAND means; And inverting means for inverting the signal output through the output node of the second latch and outputting the pre-control signal. 8. The method of claim 7, wherein the first latch comprises first and second NAND means, and the first NAND means performs a NAND operation by inputting the first signal and an output signal of the second NAND means. And outputting to the output node, wherein the second NAND means inputs the second signal and the output signal of the first NAND means. 8. The method of claim 7, wherein the second latch comprises first and second NAND means, and the first NAND means receives an output signal of the NAND means and an output signal of the second NAND means. And the second NAND means outputs the output signal to the output node by performing a NAND operation by inputting the first signal and the output signal of the first NAND means. 6. The apparatus of claim 5, wherein the delay means comprises: a first inverting means for inverting the pre-control signal, a noah means for receiving a predetermined fourth signal and a fifth signal, and performing a noah operation; A latch for inputting an output signal and an output signal of the noah means, second inverting means for inverting a signal output through the output node of the latch, and the control signal delayed by inverting the output signal of the second inverting means. And a third inverting means for outputting the race control circuit of the semiconductor memory device. 2. The apparatus of claim 1, wherein the race control clock generating means comprises: a plurality of NAND means for inverting signals input through the plurality of other input pins in response to the master signal, and each of the race control clock generating means in response to the control signal; A plurality of transfer means for respectively transmitting output signals of the NAND means, a plurality of latches for latching signals transmitted through the respective transfer means, and output signals and inverted output signals of each latch in response to the control signal. And decoding means for decoding and outputting the plurality of race control clocks. The method of claim 1, wherein any one of the plurality of transmission paths of the race control means transmits the internal signal without delay, and the remaining transmission paths transmit the internal signal by delaying each of the internal signals by a predetermined time. A race control circuit of a semiconductor memory device.