KR100412135B1 - Rambus dram - Google Patents

Abstract

The present invention relates to Rambus DRAM, which enables users to select x8 / x9 bit memory even after package using anti-fuse even without a separate mask, thereby lowering the cost of the memory device. In addition, when a 1-bit fail occurs after the package, the repair efficiency can be increased by repairing using cells connected to an unused deq (dq) pin. The Rambus DRAM according to the present invention selects bits according to a logical combination of a test mode signal that is enabled when switching to a Y-bit memory and a Y-bit memory enable signal that is enabled when the Y-bit memory is used when the X-bit memory is set to X-bit memory. A bit selection generator for generating a signal A and outputting the bit selection signal A to a memory cell block according to a control signal, and receiving the bit selection signal A and performing a repair enable signal REn. The repair determination unit generated by the repair address enable signal RAEn and the repair address signal received by the repair enable signal RAEN are transmitted to the memory cell block to replace unused memory cells with redundancy cells. It is characterized by comprising a repair address transmission unit.

Description

Rambus DRAM

The present invention relates to Rambus DRAM. In particular, a user can select an x8 / x9 bit memory even after package by using an anti-fuse even without a separate mask, thereby reducing the cost of the memory device. In addition, the present invention relates to a Rambus DRAM that increases repair efficiency by repairing cells that are connected to an unused deq (dq) pin when a 1-bit fail occurs after the package.

1 shows an x8 / x9 configuration of a Rambus DRAM according to the prior art.

In the case of Rambus DRAM, there is a control register similar to the mode register setting like the general synchronous DRAM, and the logic part of the RAM bus DRAM memory device is set by an externally applied value.

2A-2C show a conventional x8 / x9 logic configuration.

First, FIG. 2A illustrates a conventional bit selector for selecting an x8 / x9 bit memory byte. The x8 / x9 bit memory byte is selected by the metal option M1 or M2 by a mask. At this time, the mask must be replaced to make the metal option. Rambus DRAM is used as a 9-bit memory byte when switch M1 is turned on with the metal option of the mask, and as 8-bit memory byte when switch M2 is turned on.

FIG. 2B shows one dequeue (dq) pin and a memory cell connected thereto when Rambus DRAM is used as an 8-bit memory byte.

FIG. 2C is a diagram for explaining a specification of Rambus DRAM. FIG.

If the control register (CNFGB) address is 024 ₁₆ in the control register, if the last 0th bit is '1', it means a Rambus DRAM that reads and writes to the 9-bit memory byte. If the bit is '0', it is decided to use read and write with 8-bit memory byte.

When the RAMB DRAM device is made of 9-bit memory mainly using the prior art, a setting method implemented by the prior art may use only 8 deques (dq) out of the total 9 bits as shown in FIGS. 1 and 2B when the user wants to use the 8-bit memory byte. It is necessary and the other deq dq is not needed. As a result, the cells bound to the unused 1-bit deque (dq) were rendered useless.

In addition, the conventional circuit has a problem in that a bit selection part can be processed only with a metal option to inform the core from the Rambus DRAM logic part as shown in FIG.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to allow an x8 / x9 bit memory selection only with a conventional mask change. The use of anti fuses enables x8 / x9-bit memory selection even after package, thereby providing Rambus DRAMs that reduce the cost of memory devices.

In addition, another object of the present invention is to repair by replacing by replacing the cells connected to the unused deq (dq) pin with redundancy cells when a one-bit failure occurs after the package, To provide Rambus DRAM with increased efficiency.

1 is a view showing the x8 / x9 configuration of the Rambus DRAM according to the prior art

2A to 2C are diagrams illustrating a conventional x8 / x9 logic configuration.

2A is a diagram illustrating a conventional bit selector for selecting an x8 / x9 bit memory byte,

FIG. 2B shows one deq (dq) pin and a memory cell connected thereto when Rambus DRAM is used as an 8-bit memory byte.

FIG. 2C is a diagram for explaining a specification of Rambus DRAM. FIG.

3 is a block diagram of a Rambus DRAM according to the present invention

FIG. 4 is a circuit diagram of a bit select generator shown in FIG. 3. FIG.

5 is a configuration diagram of a repair address transfer unit illustrated in FIG. 3.

6 is a circuit diagram of the anti-fuse cell stage shown in FIG.

Explanation of symbols on the main parts of the drawings

10: bit selection generator 20: repair determination unit

30: repair address transfer unit 40: memory cell block unit

In order to achieve the above object, the Rambus DRAM according to the present invention is a test mode signal that is enabled when switching to a Y-bit memory in the state set as an X-bit memory and a Y-bit memory enable signal that is enabled when the Y-bit memory is used. A bit select signal generation unit (A) which generates a bit select signal (A) by a logical combination of the output signal, and outputs the bit select signal (A) to a memory cell block by a control signal, and receives and repairs the bit select signal (A) The repair determination unit generated by the repair signal enable signal RAEn by the enable signal REn and the repair address signal received by the repair address enable signal RAEn are not transmitted to the memory cell block. And a repair address transfer unit for replacing the memory cells with the redundancy cells.

The bit selection generation unit has two inputs of the test mode signal DAM and the Y bit memory enable signal, and when the test mode signal DAM and the Y bit memory enable signal both have high, And an N-MOS transistor for outputting a 'N' transistor, and when the output signal of the AND gate is 'high', the N-MOS transistor is turned on to supply a power supply voltage Vcc to the first node to make the potential of the first node high. And an antifuse connected between the first node and a ground voltage Vss and accumulating a 'high' voltage of the first node. Connected between the first node and a power supply voltage Vcc and the node Nd1. A resistor for supplying a raw power supply voltage (Vcc) at all times, and a transfer gate for outputting the signal of the first node to the memory cell block by a control signal.

The transfer gate is characterized in that the PMOS and NMOS transistor.

The repair determination unit may be configured as a clock inverter.

The repair address transfer unit includes a plurality of row address transfer units for generating a row address received by the repair address enable signal RAEn as a low address programming signal, and a column received by the repair address enable signal RAEn. Characterized in that the address is composed of a plurality of column address transfer unit for generating a column address programming signal.

The row address transfer unit may receive a repair enable signal and transmit a first inverter generating an inverted signal and a power supply voltage Vcc connected to a source terminal by an output signal of the first inverter to a drain terminal. A PMOS transistor, an NMOS transistor for transmitting the power supply voltage Vcc transmitted to the drain terminal of the PMOS transistor by the row address signal to a first node, and between the first node and the ground voltage Vss. And an anti-fuse connected to the first fuse, a resistor connected between the first node and the power supply voltage Vcc, and a second inverter configured to receive a signal of the first node and generate a low repair signal.

The column address transfer unit transfers a first inverter that receives the repair address enable signal and generates an inverted signal, and a power supply voltage Vcc connected to a source terminal by an output signal of the first inverter to a drain terminal. A PMOS transistor, an NMOS transistor for transmitting the power supply voltage Vcc transmitted to the drain terminal of the PMOS transistor by the row address signal to a first node, and between the first node and the ground voltage Vss. And an anti-fuse connected to the first fuse, a resistor connected between the first node and the power supply voltage Vcc, and a second inverter receiving the signal of the first node and generating a column repair signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

FIG. 3 is a block diagram illustrating a Rambus DRAM according to the present invention, wherein a bit selection generator 10 for determining bit selection (x8 / x9 bits) and x8 is selected by the bit selection generator 10 and then repaired. A memory including a repair decision unit 20 for determining whether a comparison is performed, a repair address transmission unit 30 for recognizing a repair necessity by the repair decision unit 20 and informing the address thereof, and a plurality of memory cells The cell block part 40 is provided.

The bit selection generator 10 is set to x9 bit memory and is switched to x8 bit memory. The test mode signal DAM is enabled as 'high' and the x8 bit memory is enabled when the x8 bit memory is used. The bit selection (x8 / x9 bits) signal A is generated by the logical combination of the enable signal x8MEn and the bit selection (x8 / x9 bits) generated by the control signal Sel and the control bar signal BSel. The signal A is output to the meriscell block unit 40.

The repair determination unit 20 receives the output signal A of the bit selection generation unit 10 and generates the repair address enable signal RAEn by the repair enable signal REn.

The repair address transmitter 30 transmits the repair address signal received by the repair enable signal RAEn to the memory cell block to replace unused memory cells with a redundancy cell.

FIG. 4 shows a circuit of the bit select generator 10 shown in FIG. The bit select generator 10 includes an AND gate G1, an NMOS transistor N1, an antifuse AF1, a resistor R1, and a transfer gate P1 / N1.

The AND gate G1 has two inputs of the test mode signal DAM and the x8-bit memory enable signal x8MEn, and the test mode signal DAM and the x8-bit memory enable signal x8MEn are both ' When it has high, it prints high.

The N-MOS transistor N1 is turned on when the output signal of the AND gate G1 is 'high' to supply a power supply voltage Vcc to the node Nd1 to bring the potential of the node Nd1 to 'high'. Make.

The antifuse AF1 is connected between the node Nd1 and the ground voltage Vss and accumulates a 'high' voltage of the node Nd1.

The resistor R1 is connected between the node Nd1 and the power supply voltage Vcc and always supplies the power supply voltage Vcc to the node Nd1.

The transfer gate P1 / N2 includes a PMOS transistor P1 and an NMOS transistor N2, and the node when the control signal Sel is high and the control bar signal BSel is low. The signal of Nd1 is output to the memory cell block 40.

The operation of the bit selection generator 10 of the present invention by the above configuration is as follows.

First, a bit selection circuit that can only process mask change option, which is a conventional technique for x8 and x9 selection, is configured like the bit selection generating circuit of FIG.

The memory element of the present invention is normally set to x9 bits as a default, and then enters the DA mode (test mode setting) when the user wants to switch to x8 bit memory.

At this time, the test mode signal DAM, which is the DA mode entry signal of FIG. 4, becomes 'high' level. Once in the DA mode, one of the DA modes is set to generate an x8 bit memory enable signal (x8MEn).

As a result, a circuit for generating an x8 bit memory enable signal (x8MEn), which is a signal that is held at a 'high' level only when the x8 bit memory is set when entering the DA mode, is configured.

This means that the user wants to replace an x9 bit memory device with an x8 bit memory device. By the above setting, all of the input signals of the AND gate G1 of FIG. 4 are 'high', and their output values are 'high'. Therefore, the NMOS transistor N1 operated by the output signal of the AND gate G1 is turned on. In this case, a voltage that is likely to be ruptured is applied across the anti-fuse. As shown in FIG. 4, the anti-fuse rupture causes the current path to be 'low' so that the level of the node Nd1 becomes 'low'. In this circuit operation, as shown in FIG. 2, the register setting signal Y is outputted from the logic part as 'low' to disable cells bound to any one bit (dq8 in FIG. 2) in the core part. It is the same as the existing operation to make it.

On the contrary, if the user wants to use the x9 bit memory, even if the test mode signal (DAM) of FIG. 4 indicating that the DA mode has been entered is 'high', the x8 bit memory enable signal (a signal for the user to use the x8 bit memory) ( The output of the AND gate G1 of FIG. 4 is 'low' unless any program operation to generate x8MEn) is 'high'. This output value does not turn on the NMOS transistor N1, so that no voltage is generated to rupture the anti-fuse AF1, and thus serves as a capacitor. In this case, the path 'A' of FIG. 4 has a constant voltage applied to the node Nd1 as 'high' by the voltage division principle between the resistor R1 and the anti-fuse.

This is because the signal A of FIG. 4 is caught at the 'high' level, and the logic part of the memory device notifies the core part of the operation of the x9 mode memory by setting the BYT B value in the Rambus specification description of FIG. 2C to '1'. It is like the role of. First of all, according to the above two cases, the user can proactively cope with x9, x8 selection according to the market demand in package state instead of the conventional mask change scheme.

5 illustrates the configuration of the repair address transfer unit 30 shown in FIG. 3. The repair address transfer unit 30 is a row address received by the repair address enable signal RAEn, as shown. The row address transfer unit 32 generating AddX as the row address programming signal ARPX and the column address AddY received by the repair address enable signal RAEn as the column address programming signal ARPY. It consists of the column address transfer part 34 which generate | occur | produces. The repair bit address signal RBAdd is generated by the row address programming signal ARPX and the column address programming signal ARPY.

FIG. 6 is a circuit diagram showing each unit row and column address transfer unit Xn (Yn) of the row and column address transfer unit 32 and 34 shown in FIG. As shown in the drawing, the row and column address transfer units Xn and Yn each include one P-MOS transistor P11, one N-MOS transistor N11, an anti-fuse AF11, and a resistor R11. It consists of two inverters G11 and G12.

The inverter G11 receives the repair address enable signal RAEn and outputs an inverted signal. The PMOS transistor P11 is connected to a source terminal when the output signal of the inverter G11 is 'low'. The connected power supply voltage Vcc is transferred to the drain terminal.

The N-MOS transistor N11 is turned on when the row address signal (or column address signal) is 'high', and the node N11 receives the power supply voltage Vcc transferred to the drain terminal of the P-MOS transistor P11. To send.

The antifuse AF11 is connected between the node Nd11 and the ground voltage Vss, and accumulates a 'high' voltage of the node Nd11.

The resistor R11 is connected between the node Nd11 and the power supply voltage Vcc, and supplies the power supply voltage Vcc to the node Nd11 at all times.

The inverter G12 receives and inverts the signal of the node Nd11 and generates the low repair programming signal (or column repair programming signal) ARP #.

The operation of the repair address transfer unit 30 having the above configuration is as follows.

First, when one-bit failure occurs when testing a package selected as x8 or x9, the conventional method has no way of repairing the memory device. However, in the case of the present invention, once a 1-bit fail occurs, the cells suspended in the unused dq stage (dq1 not used among nine) described above are used as redundancy cells.

Since the memory device needs to be informed that a repair is needed, the repair address enable signal (RAEn) and the repair address (AddX, AddY), which are signals indicating that a repair is necessary after entering the DA mode, such as the previous x9 and x8 bit memory selection, are required. Applied from outside. In this case, as shown in FIG. 5, each repair address transfer unit (Xn) (Yn) generates a repair bit address and transmits the repair bit address to a core part as in a conventional normal fuse scheme.

As shown in FIG. 5, the repair address enable signal RAEn becomes 'high', which is the first condition for generating a current path for breaking the anti-fuse AF11 of FIG. 6. For example, if the row address is an address to be repaired by 100, the addresses are input in the order of x0, x1, and x2 which are repair address transfer units as shown in FIG. When the most significant bit '1' is input, as shown in FIG. 6, the repair address enable signal RAEn is 'high' and the address signal Add # is also 'high' so that the PMOS transistor P11 and the NMOS transistor ( N11) are all turned on. Therefore, a voltage that can be ruptured is generated in the anti-fuse AF11. Once the anti-fuse AF11 is ruptured, a current path such as the path 'I' of FIG. 6 is generated and the level of the node Nd11 is 'low'. This value outputs an anti repair program (ARP #) as 'high' via the inverter G12.

When the next bit '0' is input, as shown in FIG. 6, the repair address enable signal RAEn is 'high' and the address signal Add # is 'low' such that the PMOS transistor P11 is turned on. Is turned on and the NMOS transistor N11 is turned off. In this case, there is no current path that can be ruptured in the anti-fuse. Instead, a constant level is applied to the node Nd11 by the voltage division principle between the resistor R11 and the anti-fuse AF11. The Anti Repair Program (ARP #) value is then zero. As shown in these two examples, the user can program the address to be repaired after the package so that repair address comparison can be made any number of times.

As shown in FIG. 3, the repair enable signal REn indicating the need for repair is not generated from the outside, and the repair determination unit 20 generates a repair address enable signal RAEn in a low state to repair the repair address. In 30, the repair bit address can be disabled.

This operation allows the user to select x8 and x9 bits of memory after the package without making a mask, and repairs a 1-bit fail that may occur after the package.

As described above, the Rambus DRAM of the present invention can reduce the cost of the memory device by not requiring a user to rewrite the x8 and x9 bit memory after the package, and also actively package the product family required by the customer after the package. Coping with the market can increase competitiveness. In addition, by using the cells unused by the conventional method for the 1-bit fail generated after the package, it is possible to increase the repair efficiency, thereby improving the yield.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (7)

For Rambus DRAM, The bit selection signal A is generated by a logical combination of a test mode signal enabled when the switch to the Y bit memory and the Y bit memory enable signal enabled when the Y bit memory is used when the X bit memory is set. A bit selection generator for outputting the bit selection signal A to a memory cell block by a control signal; A repair determination unit which receives the bit selection signal A and generates a repair address enable signal RAEn by the repair enable signal REn; And a repair address transfer unit which transmits a repair address signal received by the repair enable signal RAEN to the memory cell block and replaces unused memory cells with a redundancy cell. The method of claim 1, wherein the bit selection generation unit, AND for outputting high when the test mode signal DAM and the Y bit memory enable signal are two inputs, and the test mode signal DAM and the Y bit memory enable signal both have high. With the gate, An N-MOS transistor that is turned on when the output signal of the AND gate is 'high' and supplies a power supply voltage Vcc to the first node to make the potential of the first node 'high'; An antifuse connected between the first node and a ground voltage Vss and accumulating a 'high' voltage of the first node. A resistor connected between the first node and a power supply voltage Vcc and supplying a power supply voltage Vcc to the node Nd1 at all times; And a transfer gate configured to output a signal of the first node to the memory cell block by a control signal. The method of claim 2, The transfer gate is Rambus DRAM, characterized in that consisting of the P-MOS and N-MOS transistor. The method of claim 1, The repair determination unit Rambus DRAM, characterized in that configured as a clock inverter. The method of claim 1, wherein the repair address transfer unit, A plurality of row address transfer units generating a row address received by the repair enable signal RAEn as a row address programming signal; Rambus DRAM comprising a plurality of column address transfer unit for generating a column address received by the repair address enable signal (RAEn) as a column address programming signal. The method of claim 5, wherein the row address transfer unit, A first inverter receiving the repair address enable signal and generating an inverted signal; A P-MOS transistor for transferring a power supply voltage Vcc connected to a source terminal to a drain terminal by an output signal of the first inverter; An N-MOS transistor for transmitting the power supply voltage Vcc transmitted to the drain terminal of the P-MOS transistor by the row address signal to a first node; An anti-fuse connected between the first node and a ground voltage Vss; A resistor connected between the first node and a power supply voltage Vcc; Rambus DRAM comprising a second inverter for receiving a signal of the first node to generate a low repair signal. The method of claim 5, wherein the column address transfer unit, A first inverter receiving the repair address enable signal and generating an inverted signal; A P-MOS transistor for transferring a power supply voltage Vcc connected to a source terminal to a drain terminal by an output signal of the first inverter; An N-MOS transistor for transmitting the power supply voltage Vcc transmitted to the drain terminal of the P-MOS transistor by the row address signal to a first node; An anti-fuse connected between the first node and a ground voltage Vss; A resistor connected between the first node and a power supply voltage Vcc; And a second inverter configured to receive the signal of the first node and generate a column repair signal.