JP2002076076A - Probe card and test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a probe card which can test characteristics of a TEG by the test equipment for an electronic circuit of a semiconductor chip, and a test method using the same. SOLUTION: This probe card is used for electrically connecting an object to be measured on which one electronic circuit at least and one test element 10 at least are formed with test equipment, and comprises first probes (Q1, Q2) to test electronic characteristics of the electronic circuit connecting with above electronic circuit and second probes (P1 to 4) to test electronic characteristics of the test element 10 connecting with above test element 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe card and a test method, and more particularly to a probe card used for testing electrical characteristics of a semiconductor chip and a test element using a measuring device, and a test method using the same. About.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing process, for example, in a process of inspecting a semiconductor wafer such as silicon, an electrode of a semiconductor chip formed on the wafer and a semiconductor device test device (LSI tester) are electrically connected by a probe card. The electrical characteristics of the semiconductor chip are tested.

Here, generally, a semiconductor wafer has a T
An EG (Test Element Group) is formed. TEG
In order to evaluate a single element such as a transistor and a contact constituting an electronic circuit of a semiconductor chip, such a single element is provided separately from the electronic circuit of the semiconductor chip when forming the semiconductor chip. It is a thing.

FIG. 4 is a plan view of a part of a semiconductor wafer. In the semiconductor wafer shown in FIG.
For example, 0 is formed on a scribe line which is a boundary where the semiconductor chips C are separated from each other at the time of assembling a semiconductor device between the semiconductor chips C. In the semiconductor wafer shown in FIG. TEG10
Are formed inside the semiconductor chip C.

The above-mentioned TEG 10 is not used for shipping as a product, but is used, for example, for collecting management data in a mass production line. Specifically, the TEG 10 is fed back to each semiconductor process to execute the process. Used when optimizing. It is also used for new technology development. For example, when a new device structure is to be developed, a TEG including a pattern combining various structures and dimensions may be formed for the purpose of design optimization.

[0006] The test of the semiconductor wafer on which the TEG is formed as described above usually includes two steps. In the first step, as shown in FIG. 5A, for example, a TEG formed on a scribe line between semiconductor chips C is used to test the electrical characteristics of a single element such as a transistor.
The probe needle (P) connected to the probe card substrate for the characteristic test of the TEG 10 is applied to each electrode (M1 to M4)
1 to P4), and test the electrical characteristics of the TEG via a tester. Alternatively, as shown in FIG. 5B, for example, the TEG formed inside the semiconductor chip C
Probe electrodes (P1, P2) connected to a probe card substrate for TEG characteristic test
2) Contact and test the electrical properties of the TEG via a tester. The test of the electrical characteristics of the TEG 10 is mainly a direct current (DC) characteristic test. The DC characteristics test includes, for example, a high-level and low-level input voltage of each input pin, an input current, This test is for measuring the static characteristics such as the output voltage and output current of the output pins, and the DC characteristics of the semiconductor element such as the operating current consumption and the quiescent current consumption.

After performing the above-described electrical property test of the TEG, the electrical property of the semiconductor chip C is tested as a second step. In the second step, as shown in FIG. 6, among the electrodes (N1 to N6) connected to the electronic circuit of the semiconductor chip C, for example, the probe (N1, N2) is connected to a probe card for testing the characteristics of the semiconductor chip C. The probe needles (Q1, Q2) connected to the substrate are brought into contact with each other to test the electrical characteristics of the semiconductor chip via a tester. For example, as a test of the electrical characteristics of the semiconductor chip, there are a function test and an alternating current (AC) characteristic test. The function test checks the logical operation function of the LSI. The AC characteristic test is for testing switching characteristics such as a delay time of a logic circuit and rise and fall times of an output.

In the conventional process of testing a semiconductor wafer, as described above, when testing the electrical characteristics of the TEG and the semiconductor chip, there are separate test processes, and a probe card used in each test process is also provided. As shown in FIGS. 5 and 6, a probe card composed of separate substrates and probe needles is used. Also, the tester used must be a large tester for performing complex tests such as a function test and an AC characteristic test as a tester for testing the electrical characteristics of a semiconductor chip. As a tester for testing the characteristic, a simple tester is used because only a DC characteristic test is required. Thus, TE
A test facility environment such as a tester and a probe card used differs between the characteristic test of G and the characteristic test of the semiconductor chip.

Therefore, in order to perform the characteristic test of the TEG and the characteristic test of the electronic circuit of the semiconductor chip,
The tester for the characteristic test of G aligns the probe needle of the probe card with the wafer W to measure the electrical characteristics of the TEG. Then, the tester for the characteristic test of the semiconductor chip separates the wafer W into another wafer. It was necessary to test the electrical characteristics of the electronic circuit of the semiconductor chip by aligning the probe needles of the probe card.

Here, the electrical characteristic test of the TEG is carried out by testing a single element wafer W constituting an electronic circuit of a semiconductor chip.
Although it is an important test to see the electrical characteristics in the plane,
As shown in FIG. 7A, only the TEGs (J1 to J5) mounted on the semiconductor wafer W are tested at several places (J1 to J5) for reasons such as productivity and TEGs are not shipped as products. I have.

Therefore, in the characteristic test of the semiconductor chip after the characteristic test of the TEG, a defective semiconductor chip exists at a specific portion or the like in the surface of the semiconductor wafer W, and FIG.
As shown in (1), when the defective portion K1 is a region where the TEG characteristic test is performed, the correlation between the abnormal parameters is determined based on the TEG characteristic test result and the characteristic test result of the electronic circuit of the semiconductor chip. By calculating, it is possible to grasp the cause of the defect of the semiconductor chip.

[0012]

However, FIG.
As shown in (c), the defective portion (K2,
If K3) is an area where the TEG characteristic test has not been performed, it is necessary to return to the TEG test process, perform the test again under a dedicated equipment environment, and acquire data.

In this case, in order to obtain the correlation between the characteristics of the semiconductor chip and the characteristics of the TEG, it is necessary to measure the TEG corresponding to the defective portion of the semiconductor chip. If the test equipment environment is different, checking the TEG corresponding to the defective portion of the semiconductor chip, which is about 200 to 300 in the semiconductor wafer, and performing the test under the different equipment environment requires a lot of time and labor. It will cost.

The present invention has been made in view of the above problems, and accordingly, the present invention provides a probe capable of performing a TEG characteristic test in a facility environment for testing characteristics of an electronic circuit of a semiconductor chip. An object of the present invention is to provide a card and a test method using the card.

[0015]

In order to achieve the above object, a probe card according to the present invention comprises an object to be measured on which at least one electronic circuit and at least one test element are formed, and a measuring device. An electrically connected probe card, comprising: a first probe connected to the electronic circuit for testing electrical characteristics of the electronic circuit; and a first probe connected to the test element, the A second probe for testing electrical characteristics.

Preferably, the probe card tests the electrical characteristics of the electronic circuit and the test element in parallel through the first and second probes.

According to the probe card of the present invention described above,
A first probe connected to an electronic circuit for measuring electrical characteristics of the electronic circuit, and a second probe connected to a test device for measuring electrical characteristics of the test device The use of a probe card having the following makes it possible to measure the electrical characteristics of the electronic circuit and the test element with the same probe card.

In order to achieve the above object, a test method according to the present invention is a method for testing an object to be measured on which at least one electronic circuit and at least one test element are formed. The first probe of the probe card having the probe and the second probe is connected to the electronic circuit, and the second probe is connected to the test element to measure the measurement device and the object to be measured. Electrically testing, testing the electrical characteristics of the electronic circuit through the first probe, and testing the electrical characteristics of the test element through the second probe. Having.

Preferably, electrical characteristics of the electronic circuit and the test element are tested in parallel through the first and second probes.

According to the above-described test method of the present invention, by connecting the first probe to the electronic circuit and connecting the second probe to the test element, the electronic circuit can be connected to the electronic circuit through the first probe. The electrical characteristics of the test element are tested through the second probe, and the electrical characteristics of the electronic circuit and the test element can be measured with the same probe card. .

Further, in order to achieve the above object, a test method according to the present invention is a test method for an object to be measured having two or more semiconductor chips on which at least one electronic circuit and at least one test element are formed. Oh, the first
The first probe of the probe card having the first probe and the second probe is connected to the electronic circuit of the semiconductor chip, and the second probe is connected to the test element of the semiconductor chip, and the measurement is performed. Electrically connecting the device and the object to be measured; testing the electrical characteristics of the test element through the second probe; and electrically connecting the electronic circuit through the first probe. Testing the electrical characteristics of the electronic circuit. The step of testing the electrical characteristics of the electronic circuit is performed only when the electrical characteristics of the test element are normal.

According to the test method of the present invention, in the step of testing the electrical characteristics of the electronic circuit and the test element, the step of testing the electrical characteristics of the electronic circuit includes the step of testing the electrical characteristics of the test element. Only do it if. This is because the electrical characteristics of the electronic circuit of the semiconductor chip having the defective test element have a high probability of being defective, whereby the test of the electrical characteristics of the electronic circuit of the semiconductor chip having the defective test element is performed. Can be omitted,
The test time of the semiconductor chip can be reduced.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a probe card of the present invention and a test method using the same will be described with reference to the drawings.

First Embodiment FIG. 1 is a schematic configuration diagram of a probe card according to the present embodiment. The probe card 101 shown in FIG. 1 has a substrate 102 and a plurality of probe needles (probes) 105 held on the substrate 102.
Is an LSI by a cable 109 via the substrate 102.
It is electrically connected to the tester 201. Here, the probe needle 105 has a probe needle Q for testing the characteristics of the semiconductor chip and a probe needle P for testing the characteristics of the TEG. Therefore, a probe needle P for testing the characteristics of the TEG and a probe needle Q for testing the characteristics of the semiconductor chip C
Are connected to the same substrate 102 and the substrate 10
2 is also connected to the same LSI tester 201.

The test method of the present invention using the probe card 101 will be described. FIG. 2 is a cross-sectional view showing a state in which the probe card 101 is positioned with respect to the wafer W and is in contact with a semiconductor chip on the wafer and an electrode connected to the TEG. As shown in FIG. 2, the test of the electrical characteristics of the semiconductor chip C and the TEG is performed by positioning the probe card 101 with respect to the wafer W and connecting the electrode N to the electronic circuit of the semiconductor chip C on the wafer W.
An electrode M for contacting a probe needle Q with the substrate and connecting to a TEG formed between the semiconductor chips C on the wafer W, for example.
Is performed by bringing the probe needle P into contact with.

As shown in FIG. 2, the probe card 101
First, the electrical characteristics of the semiconductor chip C are tested in a state where the probe needles (P, Q) are in contact with the electrode N of the semiconductor chip formed on the wafer W and the electrode M of the TEG.

As shown in FIG. 3A, for example, the probe needles (P1 to P4) are brought into contact with the respective electrodes (M1 to M4) of the TEG 10 formed on the scribe lines between the semiconductor chips C, and Among the electrodes (N1 to N6) connected to the electronic circuit of the chip C, for example, the electrodes (N1, N
2) Contact the probe needles (Q1, Q2) with LS
The electrical characteristics of the semiconductor chip C are tested via the I tester 201. Alternatively, as shown in FIG.
For example, the probe needles (P1, P2) are brought into contact with the respective electrodes (M1, M2) of the TEG 10 formed inside the semiconductor chip C, and the respective electrodes (N1 to N6) connected to the electronic circuit of the semiconductor chip C are connected. Of which, for example, electrodes (N1, N2)
Then, the probe needles (Q1, Q2) are brought into contact with each other to test the electrical characteristics of the semiconductor chip C via the LSI tester 201.

For example, as a test of the electrical characteristics of the semiconductor chip C, a function test or an alternating current (A
C) There are characteristic tests. The function test is
This is to check the logical operation function of the LSI.
The AC characteristic test is for testing switching characteristics such as a delay time of a logic circuit and rise and fall times of an output.

During the characteristic test of the semiconductor chip C,
Alternatively, immediately after the characteristic test, when a defect in the electrical characteristics of the semiconductor chip C is found, the characteristic test of the TEG 10 in the defective portion is performed. The test of the electrical characteristics of the TEG 10 is mainly a direct current (DC) characteristics test. The DC characteristics test includes, for example, a high level and a low level input voltage of each input pin, an input current, and a test of each output pin. This test is for measuring the static characteristics such as the output voltage and the output current, and the DC characteristics of the semiconductor single device such as the operating current consumption and the quiescent current consumption.

Next, the cause of the failure of the semiconductor chip C can be grasped by obtaining the correlation between the abnormal parameters from the result of the characteristic test of the TEG 10 and the result of the characteristic test of the electronic circuit of the semiconductor chip C. . Thereafter, the result is fed back to each process of the semiconductor, so that the process can be optimized.

According to the probe card and the test method using the same according to the present embodiment, the defective portion of the semiconductor chip C in the surface of the semiconductor wafer W obtained from the characteristic test result of the semiconductor chip C is Under the equipment environment of the characteristic test, it is possible to see the characteristics of the TEG 10 at the abnormal point in a short time without any trouble, to grasp the cause of the abnormality, and to take prompt measures and measures.

Second Embodiment In this embodiment, a probe card to be used is substantially the same as that of the first embodiment, but a test method using the probe card is different. The test method according to the present embodiment will be described.

For example, as shown in FIG.
In the semiconductor wafer W in which 0 is present inside the semiconductor chip C, if an abnormality out of the standard is observed in the characteristics of the TEG 10, it is expected that an abnormality is observed in the characteristics of many semiconductor chips C, and as a semiconductor device, It is possible that the function cannot be fulfilled. This is because, if there is an abnormality in the characteristics of the TEG 10, the electronic circuit of the semiconductor chip C having a single element substantially similar to the TEG 10 has a high probability of failure.

In such a case, as a test program stored in the storage device of the LSI tester 201, TEG1
0 is added before the characteristic test program of the semiconductor chip C, and if the characteristic test of the TEG 10 is out of specification, the characteristic test program of the semiconductor chip C having the TEG 10 is performed without performing the characteristic test of the semiconductor chip C. Is programmed to be determined to be defective.

Then, as shown in FIG. 2, the probe needles (P, Q) of the probe card 101 are brought into contact with the electrodes N of the semiconductor chips formed on the wafer W and the electrodes M of the TEG. Test characteristics. The T
The content of the test of the electrical characteristics of the EG is the same as that described in the first embodiment.

According to the characteristic test of TEG10, TEG1
If there is no problem with the characteristic of 0, the electrical characteristics of the semiconductor chip C having the TEG 10 are tested next. The content of the test of the electrical characteristics of the semiconductor chip C is the same as that described in the first embodiment. Here, TEG10
According to the characteristic test described above, if the characteristic of the TEG 10 is out of the standard, the characteristic test of the semiconductor chip C having the TEG 10 is not performed, and the TE
The process proceeds to the characteristic test of G10 and the characteristic test of the semiconductor chip C. In this way, the characteristic test of the semiconductor chip C and the TEG 10 formed one after another in the surface of the wafer W is performed.

According to the present embodiment, the nonstandard TEG10
By determining that all of the semiconductor chips C containing the defective products are defective, it is possible to avoid the defective products from flowing out to a later process or a market. In the characteristic test of the TEG 10, the semiconductor chip C having the TEG 10 determined to be out of the standard is determined to be defective without performing the characteristic test of the semiconductor chip C. The characteristic test time can be reduced.

The probe card and test method of the present invention are not limited to the above description. For example, in the present invention,
The probe card of the horizontal (cantilever type) needle in which the needle-like terminal (probe) is inclined obliquely from the substrate has been described. However, the present invention is not limited to this. For example, a needle-like terminal (probe)
The present invention is also applicable to a probe card having a vertical (vertical) type needle in which a probe is vertically set on a substrate, and a probe card having a membrane type probe terminal in which a bump is formed on an insulating film. In addition, the number of probe needles for testing the characteristics of the TEG and the number of probe needles for testing the characteristics of the semiconductor chip mounted on the probe card is not limited to the number described in the present embodiment, and as many probe needles as possible are mounted. It is also possible. In addition, various changes can be made without departing from the gist of the present invention.

[0039]

According to the present invention, it is possible to measure the electrical characteristics of an electronic circuit and a test element with the same probe card, and the correlation between the electrical characteristics of the electronic circuit and the electrical characteristics of the test element. Can be obtained in a short time.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a probe card according to the present embodiment.

FIG. 2 is a cross-sectional view showing a state in which the probe card of the present embodiment is positioned with respect to a wafer and is in contact with a semiconductor chip on the wafer and an electrode connected to a TEG.

FIG. 3 is a perspective view of a main part for describing a test method using the probe card of the present embodiment;
(A) shows a case where a TEG is formed in a scribe line between semiconductor chips, and (b) shows a case where a TEG is formed inside the semiconductor chip.

FIG. 4 is a plan view of a part of a semiconductor wafer, and FIG. 4 (a) shows a wafer in which a TEG is formed in a scribe line between semiconductor chips;
(B) shows a wafer in which a TEG is formed inside a semiconductor chip.

FIG. 5 is a perspective view of a main part for describing a TEG test method in a wafer test process according to a conventional example, and FIG. 5 (a) shows a TE line in a scribe line between semiconductor chips.
FIG. 4B shows a case where a G is formed, and FIG. 5B shows a case where a TEG is formed inside a semiconductor chip.

FIG. 6 is a perspective view of an essential part for describing a method of testing a semiconductor chip in a wafer test process according to a conventional example.

FIG. 7 is a diagram for explaining a relationship between a portion where a characteristic test of a TEG formed in a wafer surface is performed and an abnormal portion of a semiconductor chip;

[Description of References] 10 TEG, 101 probe card, 102 board, 109 cable, 105 probe needle, J1, J
2, J3, J4, J5 ... TEG characteristic test location, K
1, K2, K3: defective semiconductor chip, M1, M2,
M3, M4 ... electrodes connected to TEG, N1, N2, N
3, N4, N5, N6 ... electrodes connected to the electronic circuit of the semiconductor chip, P1, P2, P3, P4 ... probe needles for TEG characteristic test, Q1, Q2 ... probe needles for semiconductor chip characteristic test, C ... semiconductor Chip, W: wafer.

Claims (5)

[Claims] An object under test on which at least one electronic circuit and at least one test element are formed;
A probe card electrically connected to a measurement device, wherein the probe card is connected to the electronic circuit, and a first probe for testing an electrical characteristic of the electronic circuit, and connected to the test element, A probe card having a second probe for testing electrical characteristics of the test element. 2. The probe card according to claim 1, wherein electrical characteristics of said electronic circuit and said test element are tested in parallel through said first and second probes. 3. A method for testing an object to be measured on which at least one electronic circuit and at least one test element are formed, wherein the first and second probes are provided in a probe card having a first probe and a second probe. Connecting the first probe to the electronic circuit, and connecting the second probe to the test element to electrically connect the measuring device and the object to be measured; and the first probe A test method comprising: testing the electrical characteristics of the electronic circuit through the second probe; and testing the electrical characteristics of the test element through the second probe. 4. The test method according to claim 3, wherein the electrical characteristics of the electronic circuit and the test element are tested in parallel through the first and second probes. 5. A semiconductor chip on which at least one electronic circuit and at least one test element are formed.
A method for testing an object to be measured having the above, wherein the first probe of a probe card having a first probe and a second probe is connected to an electronic circuit of a semiconductor chip,
Connecting the second probe to the test element of the semiconductor chip to electrically connect the measuring device and the object to be measured; and electrically connecting the test element to the test element through the second probe. Testing the electrical characteristics of the electronic circuit through the first probe; testing the electrical characteristics of the electronic circuit; A test method performed only when the characteristics are normal.