JPH10199943A - Method of testing semiconductor integrated circuit and probe card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove defective semiconductor chips on a semiconductor wafer, when the en-bloc burn-in in the form of a wafer. SOLUTION: Integrated circuit chips 2 on a semiconductor wafer 1 are tested and burnt-in in the form of a wafer, using a probe card having power voltage feed lines 4 and ground lines 5 divided per row and column and disposed mutually crosswise. For defective chips found, the voltages on corresponding power voltage feed lines 4 and ground lines 5 are replaced to feed negative power voltages, conductors 17 between electrodes 14 for feeding the power voltages and internal circuits are cut off to stop feeding the power voltages to the internal circuits, while the power voltages feed to the internal circuits of other good chips are kept.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of inspecting a semiconductor integrated circuit device formed on a semiconductor wafer and simultaneously performing burn-in in a wafer state, and a probe used for the inspection. It's about cards.

[0002]

2. Description of the Related Art In recent years, there has been remarkable progress in miniaturization and price reduction of electronic devices equipped with semiconductor integrated circuit devices, and there is a strong demand for semiconductor integrated circuit devices to be reduced in size and cost. Usually, a semiconductor integrated circuit device is electrically connected to a lead frame by a wire bonding method and mounted on a circuit board in a form sealed with resin or ceramics. A state in which the device is cut out from a semiconductor wafer (hereinafter, "bare chip"
Therefore, a method of mounting directly on a circuit board has been developed, and it is desired to provide a bare chip with a guaranteed quality at a low price.

[0003] However, the burn-in using the bare chip is very complicated to handle and cannot meet the demand for cost reduction. In addition, it is very difficult to perform burn-in screening by dividing a large number of semiconductor integrated circuit devices (hereinafter, sometimes referred to as “integrated circuit chips” in some cases) simultaneously formed on the same substrate one by one or several. It takes time and is not realistic in terms of time and cost.

Therefore, it is important to perform burn-in screening on all integrated circuit chips simultaneously in a wafer state. In order to perform batch burn-in in a wafer state, it is necessary to apply a power supply voltage or an input signal to a plurality of integrated circuit chips formed on the same semiconductor wafer at the same time to operate. For this purpose, it is necessary to prepare a probe card having a very large number (usually several thousand or more) of probe terminals, and the conventional needle type probe card cannot cope with the number of pins and the cost. Therefore, it is conceivable to adopt a thin-film probe card in which bump electrodes are provided on a flexible substrate (Nitto Technical Report Vo)
l. 28, No. 2 Oct. 1990pp. 57-6
2).

Hereinafter, a burn-in screening using a thin-film probe card using a flexible substrate with bumps will be described with reference to FIGS. 4 and 5. 4 and 5 show a state in which a thin film probe card a (not shown in FIG. 4) is connected to an integrated circuit chip c on a semiconductor wafer b. The semiconductor wafer b is placed on the upper surface of the vacuum chuck d during burn-in, and is fixed so as not to move by being evacuated from a plurality of pores (not shown) formed on the upper surface of the vacuum chuck d. I have.
The vacuum chuck d is equipped with a heater and a temperature sensing device (both are not shown) so that the temperature of the semiconductor wafer b mounted on the upper surface of the vacuum chuck d can be controlled.

[0006] The thin-film probe card a includes a polyimide substrate e as a flexible substrate, and a wiring f is formed on the polyimide substrate e. The wiring f is connected to a bump electrode i inserted into a through hole h. It is connected to the. On the other hand, each integrated circuit chip c of the semiconductor wafer b
Is formed with a pad electrode j serving as a power supply, a ground, and an input / output terminal of the integrated circuit. At the time of burn-in, the bump electrode i of the thin-film probe card a is connected to the pad electrode of all the integrated circuit chips c on the semiconductor wafer b. j, so that all the pad electrodes j of the plurality of integrated circuit chips c and all the bump electrodes i of the thin-film probe card a are connected at one time.

The surface of each of the integrated circuit chips c other than the pad electrodes j is covered with an electrically insulating passivation film k for protecting the integrated circuit. In order to prevent the surface of the package from peeling off from the package resin, the package is covered with an electrically insulating polyimide film m.

The procedure for performing burn-in screening using the thin-film probe card a is as follows. The thin-film probe card a is pressed against a semiconductor wafer b fixed to a vacuum chuck d, and all pads of a plurality of integrated circuit chips c are formed. The electrode j and all the bump electrodes i of the thin-film probe card a are connected at one time. In this state, a power supply voltage and an input signal are applied via the wiring f of the thin-film probe card a, and an electrical measurement is performed in this state for inspection. When performing measurement at high temperature during burn-in, use the vacuum chuck d
To heat the vacuum chuck d and the semiconductor wafer b fixed on the upper surface thereof.

[0009]

However, when performing the batch burn-in in the wafer state using the above-described thin film type probe card a, if there is a defective chip, the batch burn-in in the wafer state may not be possible. is there. The causes include a power supply voltage and an input signal, which will be described below.

First, the power supply voltage will be described. In order to reduce the amount of wiring on the thin-film probe card a and to reduce the number of power supplies of the tester, the wiring f is usually shared on the thin-film probe card a. . At this time, if a short circuit occurs between the power supply wiring in the defective chip and another wiring, a large current flows through the defective chip, and not only the voltage of the power supply terminal of the defective chip drops, but also the power supply terminal of another good chip. , The normal burn-in or inspection becomes impossible.

On the other hand, when the power supply wiring is not shared on the thin-film probe card a, the amount of wiring on the thin-film probe card a is extremely increased, which is not practical. In any case, a large amount of current flows through the defective chip and the wiring connected to the defective chip to generate heat, and the temperature rises. This leads to a rise in the temperature of nearby good chips,
Obstruction of normal burn-in or inspection.

Next, input signals will be described. In order to reduce the amount of wiring on the thin film probe card a in the same manner as in the case of power supply wiring, and to reduce the number of input signal sources of the tester, the thin film probe card is used. It is desirable to share the wiring f on a. At this time, if a short circuit occurs between the input signal wiring in the defective chip and another wiring, an input signal on the input signal wiring becomes an abnormal signal completely different from a normal signal. Therefore, the thin-film probe card a
Abnormal input signals are supplied to other non-defective chips sharing the same input signal wiring, and normal burn-in or inspection becomes impossible.

In order to avoid this, the input signal wiring and the input signal source for each semiconductor chip may be made independent. However, in this method, the amount of wiring on the thin-film probe card a is increased and the input signal source of the tester is increased. However, this method is not practical because the number of devices increases and the cost of the inspection apparatus increases significantly. The above-described failure of the power supply wiring or the input signal wiring is not only present before the burn-in, but may also occur during the burn-in. If the defective chip is removed by any method before the burn-in, the defective chip during the burn-in may be removed. Not all can be removed.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems, and to prevent an abnormal electric potential of a power supply wiring or an input signal wiring due to a defective chip, or to prevent a temperature rise due to heat generation of a defective chip. In addition, the amount of power supply wiring and input signal wiring on the thin-film probe card and the number of tester power supplies and input signal sources are prevented from increasing, and low-cost inspection equipment allows semiconductors to be burned in batch at the wafer state. The purpose is to eliminate the effects of defective chips on the wafer.

[0015]

In order to achieve the above-mentioned object, the present invention provides a method of performing a batch burn-in process in a wafer state, in which an input range between a power supply pad and a ground pad of each integrated circuit chip on a semiconductor wafer is out of an allowable range. Is supplied, the conductive line connecting the power supply and the internal circuit is disconnected in the chip thereafter.

More specifically, a method for inspecting a semiconductor integrated circuit device according to claim 1 is a method for inspecting a semiconductor integrated circuit device formed in a matrix on a semiconductor wafer. A power supply voltage is supplied to each power supply electrode of each semiconductor integrated circuit device arranged in one direction in a row direction or a column direction through a common wiring, and the power supply voltage is supplied to the other direction in the row direction or the column direction in each semiconductor integrated circuit device. A step of determining the quality of each semiconductor integrated circuit device by grounding each ground electrode of each of the lined semiconductor integrated circuit devices via a common wiring; Apply voltage or current to the power supply electrode and ground electrode of the circuit device through the common wiring, so that the voltage or current between the power supply electrode and ground electrode is outside the allowable input range. The Rukoto, and a step of cutting the conductive wire for connecting the power source electrode or the ground electrode and the internal circuit of the failure judged semiconductor integrated circuit device.

According to the above configuration, not only a defective chip existing before burn-in but also a defective chip generated during burn-in can be removed from the burn-in. In other words, a voltage outside the input allowable range is supplied to the defective chip between the power supply electrode and the ground electrode at the time of burn-in from the row direction and the column direction, and the conductive line between the power supply electrode or the ground electrode and the internal circuit inside the defective chip. Breaks. As a result, the defective chip can be electrically separated from the wiring on the inspection device (probe card), so that a large amount of current flows through the defective chip, thereby lowering the voltage of the power supply wiring shared on the probe card. The temperature rise due to heat generation and heat generation does not affect the burn-in or inspection of other good chips.

According to a second aspect of the present invention, there is provided a method for inspecting a semiconductor integrated circuit device according to the first aspect, wherein the power supply electrode or the ground electrode of the semiconductor integrated circuit device determined to be defective has a common wiring. On the other hand, when a voltage or current between the power supply electrode and the ground electrode of the semiconductor integrated circuit device determined to be defective is out of the allowable input range, the power supply electrode and the ground electrode of the good semiconductor integrated circuit device are applied. The connection between the power supply electrode and the ground electrode and the internal circuit is maintained by applying a voltage and a current within the allowable range of the input.

As described above, when a voltage or current is applied such that the voltage or current between the power supply electrode and the ground electrode of the integrated circuit chip determined to be defective is outside the allowable input range,
By applying a voltage and a current within the allowable range of input between the power supply electrode and the ground electrode of a good integrated circuit chip, a good wiring having a common wiring with the power supply electrode or the ground electrode of the integrated circuit chip determined to be defective. Since the connection between the power supply electrode and the ground electrode of the integrated circuit chip and the internal circuit is maintained, the connection between the power supply electrode and the ground electrode and the internal circuit can be cut off only for the integrated circuit chip determined to be defective.

According to a third aspect of the present invention, the conductive line connecting the power supply electrode or the ground electrode of the semiconductor integrated circuit device determined to be defective to the internal circuit and the internal circuit is cut off. In this case, the input terminal is electrically floated. The wiring between the power supply and the internal circuit is disconnected inside the defective chip, and power is not supplied to the internal circuit, so that the input signal terminal that has short-circuited with other wiring inside the chip is floated by a pre-designed function. be able to. As a result, the input signal wiring in the chip can be electrically separated from the common input signal wiring on the inspection device (probe card), so that the input signal on the input signal wiring shared on the probe card becomes abnormal. Can be avoided, and the burn-in and inspection of other good chips are not affected. For this reason, it is possible to perform low-cost, normal burn-in or inspection of non-defective chips at the time of probe inspection using a thin-film probe card with common power supply wiring and input signal wiring. Become.

According to a fourth aspect of the present invention, there is provided an inspection method for a semiconductor integrated circuit device according to the first aspect, wherein an input between the power supply electrode and the ground electrode applied to the power supply electrode and the ground electrode of the semiconductor integrated circuit device determined to be defective is allowed. The voltage or the current outside the range is a voltage or a current at which the power electrode becomes a negative voltage with respect to the ground electrode. In this way, by applying a voltage or current to the power supply electrode which is a negative voltage with respect to the ground electrode to the defective chip, the conductive line connecting the power supply electrode or the ground electrode of the defective chip to the internal circuit is cut. Then, the power supply to the internal circuit is stopped. In this case, for example, a negative power supply voltage can be supplied by exchanging the voltages of the power supply voltage supply wiring and the grounding wiring, and when the power supply electrode has a negative voltage with respect to the ground electrode, By providing a PN junction through which a current flows in an internal circuit between the power supply electrode and the ground electrode, a large current flows and the conductive line can be cut.

According to a fifth aspect of the present invention, the probe card extends in one direction in the row direction or the column direction and is provided in parallel in the other direction in the row direction or the column direction, and each row or each column in one direction in the row direction or the column direction. A first wiring group including a plurality of wiring layers for supplying a power supply voltage to a power supply electrode of the semiconductor integrated circuit device;
The power supply circuit extends in the other direction in the row or column direction and is provided in parallel in one direction in the row or column direction to ground the ground electrode of the semiconductor integrated circuit device in each row or column in the other direction in the row or column direction. A second wiring group including a plurality of wiring layers.

A probe card in which wiring is shared by the first wiring group and the second wiring group as described above.
It is possible to carry out batch burn-in or inspection in a wafer state for non-defective chips at the time of probe inspection at low cost without any problem.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. A probe card used for applying a power supply voltage between a power supply pad and a ground pad of an integrated circuit chip will be described. FIG. 1 is an explanatory diagram of a configuration of a probe card according to the present invention. In FIG. 1, 1 is a semiconductor wafer, 2 is an integrated circuit chip formed in a matrix on the semiconductor wafer 1, 3 is a bump electrode on a probe card (not shown), and 4 is a first tester.
5 is a wiring on the probe card connected to a power supply (not shown) of the tester, 5 is a wiring on the probe card connected to a second power supply (not shown) of the tester, and 6 is a first input signal source of the tester. Wiring on the probe card (not shown),
7 is a wiring on the probe card connected to a second input signal source (not shown) of the tester.

In this configuration, the wiring to each bump electrode 3 on the probe card, and the wiring 4 connected to the first power supply of the tester are wired horizontally one row at a time to form a first wiring group VDD1. , VDD2, VDD3, VDD4, VDD
5, and the wirings 5 connected to the second power supply of the tester are wired independently in a vertical column to form a second wiring group VSS.
1, VSS2, VSS3, VSS4 and VSS5. A power supply pad (power supply electrode) on each integrated circuit chip 1 is independently connected to a single common wiring 4 extending in the lateral direction connected to a first power supply of the tester, and a ground pad (ground electrode) is It is independently connected to one common wiring 5 extending in the vertical direction connected to the second power supply of the tester. Wiring 6, connected to the input signal source of the tester
7 is common to all the integrated circuit chips 1.

FIG. 2 shows an integrated circuit chip according to an embodiment of the present invention. In FIG. 2, reference numeral 2 denotes an integrated circuit chip. On the integrated circuit chip 2, a ground electrode 12 serving as a pad electrode, an Al wiring 13 connected to an internal circuit (not shown), and a pad electrode are provided. Al wiring 1 connected to a certain power supply voltage supply electrode 14 and an internal circuit (not shown)
5 are provided. The Al wiring 15 connects an Al fuse (conductive line) 16 and an Al wiring 17 in series, and is connected to the electrode 14 for supplying power supply voltage. Here, the width of the Al wirings 15 and 17 is, for example, 20 μm, the width of the fuse 16 is, for example, 2 μm, and the width of the fuse 16 is the Al wiring 1.
It is formed narrower than the width of 5,17.

When a normal integrated circuit chip 2 is used, a power supply voltage during normal use within an allowable input range, for example, 3.3 V, is supplied between the power supply voltage supply electrode 14 and the ground electrode 12. Is done. At this time, the power supply voltage is
6 and an Al wiring 15 connected to the internal circuit. At this time, the current flowing through the fuse 16 is not large enough to blow the fuse 16, and therefore, the configuration of the power supply wiring does not hinder the normal use of the integrated circuit chip 2.

When performing burn-in, a power supply voltage at the time of burn-in, for example, 6.0 V is supplied between the power supply voltage supply electrode 14 and the ground electrode 12. At this time, the power supply voltage is the fuse 16 and the Al wiring 1 connected to the internal circuit.
5 to the internal circuit. At this time, fuse 1
The current flowing through 6 is not large enough to blow fuse 16, so that the configuration of the power supply circuit does not hinder burn-in of integrated circuit chip 2.

During the burn-in, the integrated circuit chip 2 is periodically inspected. The power supply voltage at this time is made equal to that during normal use. The voltage state during normal use described above is realized. At this time, an output signal from the integrated circuit chip 2 to be inspected is detected using a tester (not shown) connected to an output pad (not shown). When the output signal is determined to be normal based on a predetermined reference, the integrated circuit chip 2 is determined to be non-defective, and the burn-in voltage is again applied between the power supply voltage supply electrode 14 and the ground electrode 12. Apply. If it is determined that the output signal is not normal based on a predetermined criterion, the integrated circuit chip 2 is determined to be defective. At this time, a voltage outside the input allowable range, particularly a negative voltage, for example, -6.0 V, is applied between the power supply voltage supply electrode 14 and the ground electrode 12 of the defective chip.

FIG. 3 shows a CMO as a typical internal circuit when a high negative voltage is applied between the two power supply voltage supply electrodes 14 and the ground electrode 12 of the integrated circuit chip 2.
FIG. 4 is an explanatory diagram of a current path in an S inverter. In FIG. 3, 21 is a P well, 22 is a gate electrode of an NMOSFET formed on the P well 21, and 23 is an NMOSFET.
Gate oxide film, 24 is the source of the NMOSFET, 25
Is a drain of an NMOSFET, 26 is an N well, 27 is a gate electrode of a PMOSFET formed on the N well 26, 28 is a gate oxide film of the PMOSFET, 29 is PM
The drain of the OSFET, 30 is the source of the PMOSFET, 31 is the wiring to be the input of the inverter, 32 is the wiring to be the output of the inverter, 33 is the power supply wiring, 34 is the wiring for applying the substrate voltage, and 35 is the wiring connected to the ground. is there.

The wiring 34 for applying the substrate voltage and the wiring 35 connected to the ground are separate in the DRAM, and the substrate voltage Vbb is connected to the substrate voltage generating circuit through the wiring 34. A negative voltage slightly lower than the ground, for example, -1.5 V is maintained by the generating circuit. In a CMOS circuit other than a DRAM, a wiring 34 for applying a substrate voltage and a wiring 35 connected to the ground are connected, and the substrate voltage Vbb is kept at the same potential as the ground. The power supply wiring 33 is connected to the N well 26 together with the source 30 of the PMOSFET.
The power supply voltage Vcc is applied to the power supply voltage supply electrode 14, and the substrate voltage Vbb is supplied from the grounding electrode 12
In the case of AM, the voltage is directly applied to the P well 21 through the substrate voltage generation circuit and in the case of a CMOS circuit other than the DRAM.

When power supply voltage Vcc is a negative voltage having an absolute value larger than substrate voltage Vbb, P well 21 and N well 2
The PN junction between 6 is forward and current flows. This current is represented by I (-) in FIG. 3, and flows from the wiring 34 for applying the substrate voltage to the power supply wiring 33 through the P well 21 and the N well 26. When the power supply voltage Vcc is a negative voltage, for example, about -6.0 V, the resistance of the PN junction between the forward P-well 21 and the N-well 26 becomes very small, and the voltage of this PN junction becomes N-well. 26 is fixed at about −0.6 V with respect to the P well 21. Therefore, when the substrate voltage Vbb is -1.5 V, the voltage of the Al wiring 15 connected to the internal circuit is fixed at about -2.1 V. Therefore, a difference of 3.9 V between the power supply voltage of −6.0 V and the voltage of −2.1 V of the wiring 15 connected to the internal circuit is applied to the fuse 16. As a result, a large current is applied to fuse 1 in FIG.
The fuse 16 is blown by the heat generated by the electric resistance. As a result, the electrical connection between the internal circuit of the defective chip and the power supply wiring on the probe card can be cut off.

On the other hand, due to the configuration of the common power supply wiring on the probe card, 0V is applied to the power supply voltage supply electrode 14 and the grounding electrode 12
Of the power supply voltage supply electrode 14 with respect to the ground electrode 12, the negative voltage −6.0 is applied.
When V is applied, a non-defective chip is applied with 0 V or 6.0 V to the ground electrode 12 when a voltage of 6.0 V is applied to the power supply electrode 14, and When 0 V is applied to the power supply electrode 14, 0 V is applied to the ground electrode 12, so that the power supply electrode 14 is 6.0 V higher than the ground electrode 12. Alternatively, a voltage of 0 V is applied.

When the electrode 14 for supplying the power supply voltage is applied with 0 V to the electrode 12 for grounding, the PN junction between the P-well 21 and the N-well 26 in FIG. Does not flow. Therefore, the electrical connection between the internal circuit of the good chip and the power supply wiring on the probe card is maintained without blowing the fuse 16 of FIG. When the power supply voltage supply electrode 14 is applied with 6.0 V to the grounding electrode 12, the power supply voltage is within the same input allowable voltage range as the power supply voltage at the time of burn-in, so that the current flowing through the fuse 16 is set. As a result, the internal connection of the non-defective chip and the electrical connection between the power supply wiring on the probe card are maintained.

As described above, due to the configuration of the common power supply wiring and ground wiring on the probe card, a negative voltage − between the power supply voltage supply electrode 14 and the ground electrode 12 is applied to the defective chip. When 6.0 V is applied, a voltage of 6.0 V or 0 V within an allowable input range is applied between the power supply voltage supply electrode 14 and the ground electrode 12 for a good chip. Thus, the internal circuit of the good chip and the power supply wiring on the probe card are retained, and the electrical connection between the internal circuit and the power supply wiring on the probe card can be cut off only for the defective chip.

Further, by designing in advance that the input terminal is in an electrically floating state when power is not supplied to the internal circuit, the input signal wiring in the integrated circuit chip 2 and the input signal wiring on the probe card are provided. Can be disconnected from the electrical connection. Next, the procedure of the inspection will be described.

First, after the probe test, the integrated circuit chip 2 on the semiconductor wafer 1 is formed by the method described in the background art.
The bump electrode 3 of the probe card is connected to the ground electrode 12 and the power supply electrode 14. Thereby, the wiring 4 connected to the first power supply of the tester is connected to the power supply voltage supply electrode 14 of the integrated circuit chip 2, and the second power supply of the tester is connected to the grounding electrode 12 of the integrated circuit chip 2. Wiring 5 connected to the input signal source is connected to the input terminal.
And 7, the wiring connected to the output signal detector of the tester is connected to the output terminal through the bump electrode 3.

Thereafter, the semiconductor wafer 1 is heated to a voltage for burn-in, that is, 6.0 V is applied to the wiring 4 connected to the first power supply of the tester extending in the lateral direction on the probe card and the voltage on the probe card. A power supply voltage of 6.0 V is applied by applying 0 V to the wiring 5 connected to the second power supply of the tester extending in the vertical direction. . At this time, for a defective chip found at the time of the probe test, 0 V is applied to the wiring 4 connected to the first power supply of the tester extending in the horizontal direction on the probe card, and the second tester extending in the vertical direction on the probe card is applied. 6.0V to the wiring 5 connected to the power supply
To apply a power supply voltage of -6.0V. The power supply voltage of the other integrated circuit chips is fixed to 6.0 V or 0 V.

As a result, the defective chip is blown by applying a large current to the fuse 16 between the power supply voltage supply electrode 14 and the internal circuit shown in FIG. Disconnect the electrical connection. This makes it possible to remove a defective chip existing before burn-in from the burn-in. By blowing the fuse 16, the defective chip does not electrically affect the burn-in or inspection of another integrated circuit chip 2 through the shared power supply wiring. In addition, since power is not supplied to the defective chip, the current does not generate heat in the defective chip or the power supply wiring on the probe card, and the rise in temperature due to the heat does not affect the burn-in or test of another integrated circuit chip 2. . For this reason, it is possible to carry out batch burn-in or inspection in a wafer state for a non-defective chip at the time of probe inspection at low cost and without problems using a probe card having a common power supply.

Further, the input terminal of the defective chip is electrically floated by the function designed in advance, so that the input signal wiring inside the integrated circuit chip 2 and the common input signal wiring on the probe card are electrically connected. Connection is disconnected. Thus, it is possible to prevent the signal of the shared input signal wiring on the probe card from becoming abnormal due to a short circuit between the input signal wiring in the defective chip and another wiring. As a result, a normal input signal is supplied to another non-defective chip having a common input signal wiring on the probe card, and normal burn-in or inspection can be performed.

At this time, the voltage of the power supply voltage supply electrode 14 with respect to the ground electrode 12 is fixed to 6.0 V or 0 V within the allowable input range for the good chip which has been in the same horizontal and vertical directions as the defective chip. Is done. As mentioned earlier,
In this case, the value of the current flowing through the fuse 16 between the power supply voltage supply electrode 14 in the integrated circuit chip 2 and the internal circuit is small, and the fuse 16 does not blow. Therefore, the operation of blowing the fuse 16 inside the defective chip is
The connection between the non-defective chip and the power supply wiring is not disconnected.

Defective chips generated during burn-in are found by performing periodic inspections during burn-in. For bad chips found during burn-in,
As in the case of a defective chip found during the probe test, 0 V is applied to the wiring 4 connected to the first power supply of the tester.
A voltage of 6.0 V is applied to the wiring 5 connected to the second power supply, and the other wiring is fixed at the voltage at the time of burn-in. This disconnects the electrical connection between the defective chip generated during the burn-in and the power supply wiring, and removes the defective chip generated during the burn-in. In this way, the batch burn-in of the good chip in the wafer state can be normally executed.

[0043]

According to the method for inspecting a semiconductor integrated circuit device according to the first aspect of the present invention, the defective chip is located between the power supply electrode and the ground electrode at the time of burn-in and out of the allowable input range in the row and column directions. Is supplied, and the conductive line between the power supply electrode or the ground electrode and the internal circuit is broken inside the defective chip. As a result, the defective chip can be electrically separated from the wiring on the inspection device (probe card), so that a large amount of current flows through the defective chip, thereby lowering the voltage of the power supply wiring shared on the probe card. The temperature rise due to heat generation and heat generation does not affect the burn-in or inspection of other good chips. Therefore, when batch burn-in is performed on an integrated circuit chip formed on a semiconductor wafer in a wafer state, defective chips found during inspection or burn-in are both removed and normal burn-in is performed only on good chips. It is possible to do. At this time, there is no increase in inspection cost due to an increase in the amount of wiring of the probe card or an increase in the number of power supplies and input signal sources of the tester. Therefore, it is possible to improve the reliability of the product in the market at low cost.

According to the present invention, when a voltage or current between the power supply electrode and the ground electrode of the integrated circuit chip determined to be defective is out of the allowable input range, a good power supply of the integrated circuit chip is applied. By applying a voltage and current within the input allowable range between the electrode and the ground electrode, a power supply electrode of a good integrated circuit chip having a common wiring with a power supply electrode or a ground electrode of the integrated circuit chip determined to be defective and Since the connection between the ground electrode and the internal circuit is maintained,
The connection between the power supply electrode and the ground electrode and the internal circuit can be cut off only for the integrated circuit chip determined to be defective.

According to a third aspect of the present invention, when a conductive line connecting a power supply electrode or a ground electrode of a defective chip to an internal circuit is cut off, an input terminal is electrically floated to thereby provide an input signal wiring in the chip. Can be electrically separated from the common input signal wiring on the inspection device (probe card), so that the input signal on the common input signal wiring on the probe card can be prevented from becoming abnormal. It does not affect the burn-in and inspection of good chips. For this reason, it is possible to perform low-cost, normal burn-in or inspection of non-defective chips at the time of probe inspection using a thin-film probe card with common power supply wiring and input signal wiring. Become.

According to a fourth aspect of the present invention, a voltage or current is applied to the defective chip so that the power supply electrode has a negative voltage with respect to the ground electrode, thereby connecting the power supply electrode or the ground electrode of the defective chip to the internal circuit. Disconnect the line and stop supplying power to the internal circuit. In this case, for example, a negative power supply voltage can be supplied by exchanging the voltages of the power supply voltage supply wiring and the grounding wiring, and when the power supply electrode has a negative voltage with respect to the ground electrode, By providing a PN junction through which a current flows in an internal circuit between the power supply electrode and the ground electrode, a large current flows and the conductive line can be cut.

According to the probe card of the fifth aspect of the present invention, the probe card extends in one direction in the row direction or the column direction and is provided in parallel in the other direction in the row direction or the column direction. A first wiring group consisting of a plurality of wiring layers for supplying a power supply voltage to a power supply electrode of a semiconductor integrated circuit device in each row or each column in one direction, and a first wiring group extending in another direction in the row direction or the column direction; A second wiring group, which is provided in parallel in one direction in the direction of the column or the column and comprises a plurality of wiring layers for grounding the ground electrode of the semiconductor integrated circuit device in each row or the column in the other direction of the row or the column By using the probe card having the above features for the inspections of claims 1 to 4, it is possible to carry out batch burn-in or inspection in a wafer state for non-defective chips at the time of probe inspection at low cost without any problem. Become.

[Brief description of the drawings]

FIG. 1 is a plan view of a thin-film probe card used for testing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram of power supply wiring of the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of a current path in an internal circuit when a negative voltage is applied to a power supply electrode and a ground electrode in the embodiment of the present invention.

FIG. 4 is a perspective view showing a conventional method for testing a semiconductor integrated circuit device.

FIG. 5 is a cross-sectional view showing a connection state between a conventional semiconductor integrated circuit device and a thin-film probe card.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor wafer 2 integrated circuit chip 3 bump electrode 4 one wiring of first wiring group 5 one wiring of second wiring group 6, 7 wiring group for input signal 12 electrode for grounding 14 power supply Electrode 15 wiring 16 fuse (branch line) 17 Al wiring VDD1, VDD2, VDD3, VDD4, VDD5
First wiring group VSS1, VSS2, VSS3, VSS4, VSS5
Second wiring group

Claims (5)

[Claims] 1. A method for inspecting a semiconductor integrated circuit device formed in a matrix on a semiconductor wafer, wherein each of the semiconductor integrated circuit devices is arranged in one of a row direction and a column direction. A power supply voltage is supplied to each power supply electrode via a common wiring, and a common wiring is connected to each ground electrode of each semiconductor integrated circuit device arranged in the other direction in the row direction or the column direction among the semiconductor integrated circuit devices. Determining the acceptability of each semiconductor integrated circuit device by performing grounding through the semiconductor device; and providing a common power supply electrode and a ground electrode to the power supply electrode and the ground electrode of the semiconductor integrated circuit device determined to be defective among the semiconductor integrated circuit devices. The voltage or current between the power supply electrode and the ground electrode is out of the allowable input range through the wiring of the semiconductor device. A method of inspecting a semiconductor integrated circuit device including a step of cutting the conductive wire for connecting the power source electrode or the ground electrode and the internal circuitry of the integrated circuit device. 2. A power supply electrode and a ground of a semiconductor integrated circuit device determined to be defective are compared with a good semiconductor integrated circuit device having a common wiring with a power supply electrode or a ground electrode of the semiconductor integrated circuit device determined to be defective. When a voltage or current between the electrodes that is out of the input allowable range is applied, a voltage or current within the input allowable range is applied between the power supply electrode and the ground electrode of the good semiconductor integrated circuit device. 2. The method for testing a semiconductor integrated circuit device according to claim 1, wherein the connection between the power electrode and the ground electrode and an internal circuit is maintained. 3. An input terminal is electrically floated when a conductive line connecting a power supply electrode or a ground electrode of a semiconductor integrated circuit device determined to be defective and an internal circuit is disconnected. A method for inspecting a semiconductor integrated circuit device according to claim 1. 4. A voltage or current applied to a power supply electrode and a ground electrode of a semiconductor integrated circuit device determined to be defective and out of an allowable input range between the power supply electrode and the ground electrode is negative with respect to the ground electrode. 2. The method for testing a semiconductor integrated circuit device according to claim 1, wherein the voltage or the current is a voltage or current. 5. A probe card formed in a matrix on a semiconductor wafer for inspecting a plurality of semiconductor integrated circuit devices for pass / fail, extending in one direction in a row direction or a column direction, and A plurality of wiring layers that are provided in parallel in the other direction in the direction of the column or in the column direction and that supply a power supply voltage to the power supply electrode of the semiconductor integrated circuit device in each row or each column in the one direction of the row direction or the column direction. A plurality of wiring groups extending in the other direction in the row direction or the column direction and provided in parallel in one direction in the row direction or the column direction, and semiconductor integrated circuits in each row or each column in the other direction in the row direction or the column direction A second wiring group including a plurality of wiring layers for grounding a ground electrode of the circuit device.