JP3456782B2 - Semiconductor device inspection method and probe card - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention
Inspect and burn semiconductor chips simultaneously in semiconductor wafer state
Inspection methods for semiconductor devices intended to
Especially for semiconductor device electrodes and probe card probes
It relates to a method of confirming connection with a terminal. 2. Description of the Related Art In recent years, electronic devices equipped with semiconductor integrated circuit devices have been developed.
The progress of miniaturization and price reduction of slave devices is remarkable, and semiconductors
Strong demands for downsizing and price reduction of integrated circuit devices
It has become to. Usually, a semiconductor integrated circuit device uses a wire.
It is electrically connected to the lead frame by bonding or the like.
Supplied in the form of resin or ceramic
It is mounted on the printed circuit board of the slave device. However, due to the demand for downsizing of electronic devices,
Body integrated circuit device as cut from semiconductor wafer
Circuit of electronic equipment directly in the state (hereinafter referred to as bare chip state)
As the method of mounting on the board is developed, quality assurance
It is desired that bare chips be supplied at a low price. For a semiconductor integrated circuit device in a bare chip state,
In order to perform quality assurance by
Burn-in must be performed in a bare chip state. I
However, burn-in in bare chip state is handled
Is very complicated and cannot meet the demand for price reduction. Ma
In addition, a large number of semiconductor devices formed simultaneously on a semiconductor wafer
(Hereinafter referred to as semiconductor chips) one by one or several
Performing burn-in over and over again takes a lot of time
However, it is not practical in terms of time and cost. So, half
At the same time, all the semiconductor chips in a conductor wafer state
Burning in is becoming important. [0005] Batch burn-in is performed in a semiconductor wafer state.
In this method, a plurality of semiconductor chips formed on a semiconductor wafer are
The power supply voltage and input signal must be applied to the
It is necessary. This requires a large number of probe terminals (through
It is necessary to prepare a probe card with
is there. However, conventional needle-type probe cards
Neither the number nor the price can be met. So flexible
Thin-film probe car with bumps on the shiver substrate
(Nitto Technique Vol. 28, No. 2).
2 Oct. 1990 pp. 57-62). Hereinafter, a thin film type probe will be described with reference to the drawings.
About burn-in of semiconductor chips by
Will be explained. Figure 5 shows the probe card bumps and semiconductor chips.
FIG. 5 is a cross-sectional view showing a state where the pad is in contact with the pad.
You. In FIG. 5, 28 is a probe card, 3
1 is a bump made of Ni, 32 is electrically connected to the bump 31
The connected wiring layer 33 is a polyimide film.
The flexible substrate 34 connects the bump 31 and the wiring layer 32 to each other.
This is a contact for pneumatic connection. Also, 30
These are pads formed on the semiconductor chip 29. When performing an inspection, as shown in FIG.
The bump 31 of the lobe card 28 and the path of the semiconductor chip 29
Probe card 28 so that it is connected to
Press against body chip 29. And in this state the wiring layer
Bump by supplying power supply voltage and input signal to 32
The power supply voltage is applied to the pad 30 of the semiconductor chip 29 via
And an input signal is applied to perform the inspection. Next, the probe card and the semiconductor wafer
The alignment method will be described. Figure 6 shows the probe
Alignment that aligns semiconductor chips with semiconductor wafers
FIG. In FIG. 6, 2 is a semiconductor wafer, and 1 is a half.
Vacuum chuck for fixing the conductor wafer 2, 10 is a probe
Card, 36 is a semiconductor wafer stage, 35 is a semiconductor wafer stage.
Turtle for detecting probe card position on wafer stage 36
37, bumps on the probe card 10, 37 on the probe
Probe card stage to which the
And 38 are attached to the probe card stage 39.
Semiconductor wafer alignment camera, 40 is X
X-axis control motor for controlling the position in the axial direction, 41 is the Y-axis
Y-axis control motor for controlling the position in the direction, 42 is the θ direction
Control motor 43 for controlling the position of
A Z-axis control mechanism 44 for controlling the
The heater is turned off. First, the semiconductor wafer 2 is placed on the vacuum chuck 1.
And a plurality of holes provided on the upper surface of the vacuum chuck 1.
Vacuuming the semiconductor wafer 2 into a vacuum chuck.
Fix to 1. The vacuum chuck 1 has a heater 44 inside.
A temperature sensing device (not shown) is
Control the temperature of the semiconductor wafer 2 fixed on the workpiece 1
Can be used. Next, a probe card position detecting camera 35
To detect the position of the probe card 10 and
The bump 37 of the slave card 10 is caught. Also semiconductor
The semiconductor wafer 2 is adjusted by the wafer alignment camera 38.
Of the semiconductor wafer 2 (not shown)
Without). At this time, the probe card 10
If not parallel to chuck 1, make it parallel
Adjust automatically. Next, the semiconductor wafer 2 is moved in the X-axis direction and the Y-axis direction.
The X-axis control motor 40 and the Y-axis control motor
Alignment by the motor 41 and the θ control motor 42
While moving directly below the probe card 10
When C moves right below the probe card 10, Z
The vacuum chuck 1 is raised by the shaft control mechanism 43 and semiconductive.
Pads of the body wafer 2 and bumps 37 of the probe card 10
And is connected. Normally, electrical measurement is performed in this state.
Measurement at high temperature during burn-in of conductor wafer 2
In this case, the heater 44 of the vacuum chuck 1 is energized to
And heat the semiconductor wafer 2 fixed thereon.
You. SUMMARY OF THE INVENTION
In the conventional case, the pad and the
The electrical connection with the bump of the probe card cannot be confirmed. This
Semiconductor with poor electrical connection between pads and bumps
Chips are generated, and a bar
So-called burn-in S
Cape may occur. As a result, the semiconductor wafer
Burn-in in c
There is a problem that the reliability of the product is reduced. There are two causes for poor electrical connection:
You. The first cause is that the semiconductor chip on the semiconductor wafer
Misalignment between the pad of the probe and the bump of the probe card
Electrical connection failure. This is because a semiconductor wafer and a probe card
When the semiconductor wafer itself and the
The lobe card itself blocks the field of view, and the semiconductor wafer and
Since the contact surface of the probe card cannot be observed with a camera,
Positions of semiconductor wafer pads and probe card bumps
This is because detection becomes impossible. For this reason, as shown in the conventional method,
Before aligning the wafer and the probe card,
Conductor wafer and probe card position, pads and bumps
Even if the position of the
Of the semiconductor wafer to connect the bumps
During horizontal or vertical movement, the semiconductor wafer
Error in the relative position between the pad and the probe card bump
I will. Therefore, the gap between the semiconductor wafer and the probe card
Electricity due to misalignment between pad and bump during alignment
May result in poor connection. Further, the semiconductor wafer and the probe card are connected to each other.
After alignment, use the semiconductor to perform measurements at high temperatures.
When heating the body wafer and the probe card and after
Cool and measure the conductor wafer and probe card again
The thermal expansion coefficient of the semiconductor wafer and the thermal expansion of the probe card
Difference from expansion coefficient, or each part constituting probe card
Difference in thermal expansion coefficient, and also the semiconductor wafer stage,
Peripheral parts such as vacuum chuck and probe card stage
Formed on a semiconductor wafer due to the difference in the coefficient of thermal expansion of
Phase of semiconductor chip pad and probe card bump
The position of the pair fluctuates, and the power is
Poor air connection may also occur. In these cases, the power
Check for poor air connection, correct misalignment, and
Securing the electrical connection with the bump is a conventional method
It was impossible. The second cause of the defect is that the semiconductor wafer
Between the pads of each semiconductor chip and the bumps of the probe card
Electrical connection failure due to insulating foreign matter between
There is good. Each pad of a semiconductor chip is usually made of aluminum.
The surface of this pad is exposed to air.
Alumina which is electrically insulating by being oxidized by
Covered with a film. The bump makes mechanical contact with the pad
In order to connect both electrically,
It is necessary to break the alumina film on the pad surface. However, the shape of the bump is usually hemispherical.
Therefore, the conditions when mechanically contacting the bump with the pad,
For example, the pressure to press the bump against the pad is inappropriate
And the alumina film on the pad surface remains without tearing,
Failure may occur in the electrical connection between the bumps and the bumps. Further, the probe card is connected to a plurality of semiconductor wafers.
Repeated use of probe card
Alumina gradually adheres to the bump surface, and aluminum on the bump surface
The pad and the bump are interposed between the pad and the bump.
Failure may occur in the electrical connection with the pump. In addition to these cases, for some reason,
Marginal foreign matter gets into the inspection device and the pad and bump
Intermediary may cause poor electrical connection
Conceivable. Electricity generated by these insulating foreign substances
Detects the occurrence of poor air connection and detects the connection between the pad and bump.
Take measures such as changing the contact conditions and removing foreign matter
This was not possible with conventional methods. The present invention has been made in view of the above points, and has been made in consideration of the problems described above with respect to pads and bumps.
When a failure occurs in the electrical connection with the
Can be found and responded to, ensuring that pads and bumps
Electrical connection between pads and bumps to achieve
An object is to provide a method for confirming a pneumatic connection. [0027] In order to achieve the above object,
According to the first aspect of the present invention, each operating power of a plurality of semiconductor chips is provided.
The difference between the total current and the total operating current of the
If the operating current is smaller than the minimum value,
All electrodes are connected to all probe terminals of the probe card.
It is considered to be continued. [0028] Means for solving the problems specifically taken by the invention of claim 1
Is a semiconductor device inspection method formed on a semiconductor wafer.
Of actually measuring each operating current value of multiple semiconductor chips
Calculating the sum of the respective operating current values by calculation
And electrodes of the plurality of semiconductor chips and a probe card.
Connecting a probe terminal to the plurality of semiconductor chips;
The step of actually measuring the total operating current value of the
Find the difference between the sum of the values and the total operating current value by calculation
And the sum of the operating current values and the total operating current value.
Is smaller than the minimum value of each of the operating current values,
All electrodes of the plurality of semiconductor chips and the probe
Assumes that all probe terminals are connected
And a process. According to the first aspect of the present invention, a plurality of semiconductor chips are provided.
Sum of each operating current and total operating current of multiple semiconductor chips
If the difference is less than the minimum of each operating current,
All electrodes on the conductor chip and all the probes on the probe card
Check that the cable is securely connected to the
Wear. A method for testing a semiconductor device according to the present invention will now be described.
And the probe card will be described with reference to the drawings.
You. FIG. 1 shows the inspection of the semiconductor device according to the first embodiment.
FIG. 4 is an explanatory diagram showing a state of measuring an operating current in the method.
You. In FIG. 1, 1 is a vacuum chuck and 2 is a semiconductor wafer.
C, 2a is a semiconductor chip, 3 is a probe needle, 4 is a need
Probe probe card, 5 is a needle probe card 4
, 6 is a power supply, 7 is a ground, and 8 is an input signal.
Source 9 is an ammeter. Before the burn-in of the semiconductor wafer 2, the semiconductor
Each semiconductor chip 2a on the wafer 2 is determined to be a good product or a defective product.
A probe test is performed to determine. Probe inspection
At this time, a plurality of semiconductors formed on the semiconductor wafer 2
To inspect the chip 2a in a semiconductor wafer state, it is usually full.
Use an auto prober. Semiconductor wafer 2
Provided on the upper surface of the vacuum chuck 1 inside the probe prober.
Vacuum chuck 1 by vacuuming from multiple holes
Fixed to. Next, for example, made of tungsten or the like
A probe card 4 having probe needles 3 is mounted on a semiconductor wafer.
2 and the semiconductor chip 2a on the semiconductor wafer 2
Connect the probe needle 3 to each pad (not shown),
Via the wiring layer 5 on the lobe card 4, the semiconductor chip 2
a, the power supply pad is connected to the ammeter 9 and the power supply 6;
The ground pad of the conductive chip 2a is connected to the ground 7.
Then, the pad for the input signal of the semiconductor chip 2a is connected to the tester.
Connect to input signal source 8 (not shown) to detect output signal
Inspection of the semiconductor chip 2a is performed one chip at a time
Do. At this time, the semiconductor chip under inspection by the ammeter 9 is used.
The operation current of the tip 2a is actually measured. After that,
The semiconductor to be inspected next by the alignment function of the rover
Connect each probe needle 3 to each pad of the body chip 2a,
In the same manner as described above, the operating current of the semiconductor chip 2a under inspection and inspection is
Measure the flow. Repeat this procedure for the semiconductor wafer
Measurement of operating current for all semiconductor chips 2a
I do. Each of the semiconductor chips 2 thus obtained
The minimum value is obtained from the measured values of the operating current a, and
Operating current of all semiconductor chips 2a on semiconductor wafer 2
Is obtained by calculation. FIG. 2 shows the inspection of the semiconductor device according to the first embodiment.
FIG. 7 is an explanatory diagram showing a state of measuring a total operating current in the method.
is there. In FIG. 2, 1 is a vacuum chuck and 2 is a semiconductor wafer.
2a is a semiconductor chip, 10 is a thin film probe car
And 11 are professionals connected to the power supply of a tester (not shown).
The first wiring layer 12 on the probe card 10 is
Wiring on the probe card 10 connected to the
Layer, 13 is an ammeter, 14 is a tester power supply, 15 is a tester
It is the ground of. Sum of operating currents of all semiconductor chips 2a
Wafer burn is applied to the semiconductor wafer 2 for which the calculated value of
When performing the semiconductor chip 2
The pad a is connected to the bump of the probe card 10.
Alignment of semiconductor wafer 2 with probe card 10
On the vacuum chuck 1 of the device,
Vacuum from multiple holes
Fix it to the jack 1. This vacuum chuck 1 is
The semiconductor wafer 2 moves to just below the
When the semiconductor wafer 2 is directly below the card 10, the semiconductor wafer 2 is lifted.
To the pads of the semiconductor chips 2a on the semiconductor wafer 2.
The bumps on the lobe card 10 are connected. And semiconductor
The power supply pad of each semiconductor chip 2a on the wafer 2 is
Power supply of the tester through the first wiring layer 11 and the ammeter 13
14. Similarly, connect the ground pad to the second
It is connected to the ground 15 of the tester via the wire layer 12.
Then, connect the input signal pad to the input signal source (Fig.
(Not shown). After that, the same as the probe inspection performed earlier
All semiconductor chips 2a under voltage, input signal and temperature conditions
Operate simultaneously. At this time, the power supply 14 of the tester
Connected to the power supply pads of all the semiconductor chips 2a.
By means of the ammeter 13 between the first wiring layer 11 and all
Measure the total operating current of the body chip. And I asked earlier
The sum of the operating current of each semiconductor chip 2a is used to calculate the total operating current.
The measured value is subtracted and the difference is calculated for each semiconductor chip.
Smaller than the minimum value of the operating current, for example, 10% of the minimum value
Make sure it is smaller than For example, the operating current of one semiconductor chip 2a
Assuming that the actual measured value is 10 mA, in FIG.
Since the number of semiconductor chips 2a on wafer 2 is twenty,
The sum of the operating currents at the time of the probe test is 200 mA. That
Later, in FIG. 2, all motions measured collectively in the wafer state
If the actual value of the operating current is 200 mA, the sum of the operating current
Subtract all operating current from
Pad of conductor chip 2a and bump of probe card 10
Can be confirmed to be electrically connected. But,
A semiconductor chip 2a that is not connected to at least one bump
Of the total operating current measured collectively in the wafer state
The measured value is 190 mA or less, and the total
The value obtained by subtracting the operating current is 10 mA or more,
It can be seen that there is a poor connection. In this example,
10% of the minimum operating current of the semiconductor chip 2a is allowed.
The range was set by the operating current of each semiconductor chip 2a.
And a measurement error of the total operating current. this
In this case, the actual measurement value of the operating current of one semiconductor chip 2a is 10
mA, the allowable range is 1 mA. Confirmation of connection between pad and bump in the first embodiment
The difference between the sum of the operating currents and the total operating current is
Is smaller than the minimum value of the operating current of the body chip 2a.
If approved, the semiconductor wafer 2 and the probe card 1
0, all packages of the semiconductor wafer 2 are aligned.
The probe and all bumps on the probe card are electrically normal
Is determined to be connected, and wafer burn-in is performed. If the difference between the sum of the operating currents and the total operating current
Is smaller than the minimum value of the operating current of each semiconductor chip 2a.
If this cannot be confirmed, the semiconductor
A power supply pad and a ground pad of the body chip 2a;
Alternatively, pads and bumps in the input signal
It is determined that there is a semiconductor chip 2a having a poor electrical connection.
I do. In this case, after taking appropriate measures,
Alignment of the blank 10 with the semiconductor wafer 2
cure. In the first embodiment, the contact between the pad and the bump is
The subsequent temperature must be the same as during the probe test.
However, the gap between the semiconductor wafer 2 and the probe card 10
When performing wafer burn-in after alignment,
It is necessary to raise the temperature of the wafer 2. At this time, the semiconductor wafer
C2 thermally expands and the relative position between the pad and the bump shifts
there is a possibility. Check the connection between the pad and the bump at this time.
In order to confirm that each semiconductor chip 2a is
The operating current of each semiconductor chip 2a.
Are measured one by one using a full auto prober, and the measurement is performed.
Confirm the connection between the pad and the bump by the above method using the fixed value.
You have to admit. FIG. 3 shows the inspection of the semiconductor device according to the second embodiment.
Of an input protection circuit formed on a semiconductor chip in a method
Explanatory diagram showing how a threshold voltage of a semiconductor element is measured
It is. In FIG. 3, 10 is a thin-film probe card,
16 is a bump of the probe card 10, and 17 is a probe card.
A wiring layer on the chip 10, a pad 18 of the semiconductor chip,
9 is an input protection circuit in the semiconductor chip, and 20 is an input protection circuit.
N-channel MOS transistor in the path 19, 21
The resistance in the power protection circuit 19 and 22 are internal circuits of the semiconductor chip.
The path, 23 is an ammeter, and 24 is a voltage source. First, according to the method described in the background art,
The bump 16 of the lobe card 10 is connected to a semiconductor wafer (not shown).
)) Is connected to the pad 18 of the upper semiconductor chip. Soshi
The bump 16 and the wiring layer 1 are
7, the ammeter 23 and the voltage source 24 of the tester are connected.
You. The bump 1 connected to the input signal pad 18
6 The absolute value increases with time from 0 V by the voltage source 24.
A negative voltage is applied. At that time, pass through the bump 16
The current flowing immediately is measured by the ammeter 23. The internal circuit 2 is provided at the input stage of the semiconductor chip 2a.
2 to protect it from damage caused by high voltage input such as electrostatic breakdown.
An input protection circuit 19 is provided. Its input protection circuit
N-channel type MOS transistor used in 19
N-type diffusion layer at the drain of the transistor 20 and a P-type substrate or P-type substrate.
By applying a negative voltage, the PN junction between the wells
A voltage is applied. During this measurement, the characteristics of the PN junction
When the voltage is near 0 V, almost no current flows, but the forward direction
When the voltage exceeds a certain voltage, a current starts to flow rapidly.
The current flows through the resistor 21 of the input protection circuit 19, the pad 18,
The current flows through the bump 16 and the wiring layer 17 and is
Measured. Here, the voltage of the resistor 21 is reduced by the current.
And an excessive voltage is applied in the forward direction of the PN junction.
To prevent The current value is a constant value, in this example -10 μm
The voltage that becomes A is the threshold voltage of the PN junction. this
The threshold voltage is a standard prepared in advance, for example,-
Confirm that it is within the range of 0.5V to -0.7V
You. At this time, the threshold voltage is set in advance by the resistance of the resistor 21.
Since the resistance value is known, the applied voltage of -10 μA is
It can be measured and calculated. The connection between the pad 18 and the bump 16 of the second embodiment
In the connection confirmation method, half of all non-defective products on the semiconductor wafer 2 are
All of the input signal pads 18 are provided with respect to the conductor chip 2a.
Alternatively, the N-channel MOS transistor in some of the input protection circuits 19
The threshold voltage of the transistor 20 is determined, and the threshold voltage is determined.
Pressure is within the range of the prepared standard
If confirmed, the semiconductor wafer 2 and the probe card 1
Alignment of all the halves on the semiconductor wafer 2
All pads 18 of the conductor chip 2a are the probe card 1
It is determined that all the bumps 16 of 0 have been electrically connected normally.
And perform wafer burn-in. If the N-channel type in the input protection circuit 19
The threshold voltage of the MOS transistor 20 is
If there is a semiconductor chip 2a that does not fall within the prepared standard
In this case, the pad 18 for the input signal and other pads
It is determined that there is an electrical connection failure between the pad 18 and the bump 16
I do. In this case, after taking appropriate measures,
Redo alignment between wafer 2 and probe card 10
You. In this method, the contact between the pad 18 and the bump 16 is
Not only when the temperature is normal, but also when
It can be applied to the case of the temperature at the time of in. This and
The threshold voltage specification at the temperature at the time of connection confirmation.
It should just be set to a sharp value. FIG. 4 shows an inspection of a semiconductor device according to the third embodiment.
A first wiring group and a first wiring group in each of the rows and columns in the method.
Each semiconductor chip using a probe card having two wiring groups.
FIG. 4 is an explanatory diagram showing a state of scanning a tip. In FIG.
2 is a semiconductor wafer, 2a is a semiconductor chip, 16 is
The probe card bumps, 25, are connected to the power supply of the tester.
The first wiring group on the probe card, 26, is
The second wiring group 27 on the connected probe card is
On the probe card connected to the output signal detector of the
This is a third wiring group. The first wiring group 25 on the probe card is horizontal.
Independently arranged row by row, the second on the probe card
The wiring group 26 and the third wiring group 27 are independent of each other in a vertical line.
Place. Also, the wiring connected to the tester ground
Layer (not shown) is common to all semiconductor chips 2a
And First, the alignment described in the prior art
The device allows the semiconductor chip 2a on the semiconductor wafer 2 to be
Bump (not shown) of the probe card 10
Connecting. Thereby, the power supply package of the semiconductor chip 2a is formed.
The first wiring group 25 is connected to the ground (not shown).
Pad (not shown) connected to tester ground
Wiring layers (not shown) are connected to pads (not shown) for input signals.
), A second wiring group 26 is provided with output pads (not shown).
3), the third wiring group 27 is connected via the bumps 16.
You. Next, one of the first wiring groups 25 is selected.
Power supply voltage to only one selected wiring layer
The other wiring layers are set to 0V. At the same time the second wiring
One of the groups 26 is selected, and only this one wiring layer
Supply the input signal. The power supply voltage of the semiconductor chip 2a is zero.
So that the output is in a floating state in the case of V
Design in advance. As a result, of the selected first wiring group,
One wiring layer and one wiring layer of the second wiring group
Is selected at the intersection of
Normal power supply voltage and input to only one semiconductor chip 2a
When a signal is supplied and this semiconductor chip 2a is a good product,
Normal operation, normal output signal output, tester output
Detected by force signal detector. And a half to choose
The power supply voltage and the input signal are scanned to the conductive chip 2a.
Output signals of all the semiconductor chips 2a
Can be detected. The pad 18 and the bump 16 of the third embodiment
In the connection confirmation method, all non-defective chips on the semiconductor wafer 2 are checked.
Power supply voltage and input signal to the
Signal, and this output signal is
If it is confirmed that the standards are met,
The alignment between wafer 2 and probe card 10 is half
All packages of all the semiconductor chips 2a on the conductor wafer 2
Is connected to all bumps 16 of the probe card 10
Connection is determined to be normal, and wafer burn-in is performed.
Now. If the power supply voltage and the input signal are supplied,
Output signal satisfies the predefined criteria.
If there is no semiconductor chip 2a,
In addition to the pad 2a, the pad 18 and the bump
It is determined that there is a poor electrical connection with the pump 16. in this case
After taking appropriate measures, the semiconductor wafer 2 and the probe
The alignment with the blank card 10 is redone. In this method, the contact between the pad 18 and the bump 16 is
Not only when the temperature is normal, but also when
The present invention can also be applied to the case of the temperature at the time of the intake. this
When the output signal criterion is
It should be set to the standard. According to the semiconductor device inspection method of the first aspect,
According to the report, all electrodes and probe
Make sure that all probe terminals of the
Can be confirmed, multiple semi-conductors on the semiconductor wafer
Simultaneous burn-in of conductor chips in wafer state
be able to. [0069]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram showing how an operating current is measured in a semiconductor device inspection method according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing a state of measuring a total operating current in the semiconductor device inspection method according to the first embodiment of the present invention. FIG. 3 is an explanatory diagram showing a state of measuring a threshold voltage of a semiconductor element of an input protection circuit formed on a semiconductor chip in a semiconductor device inspection method according to a second embodiment of the present invention. FIG. 4 shows a first wiring group and a second wiring group in each of a row and a column in a semiconductor device inspection method according to a third embodiment of the present invention.
FIG. 5 is an explanatory diagram showing a state in which each semiconductor chip is scanned using a probe card having the wiring group of FIG. FIG. 5 is a cross-sectional view showing a state where bumps of a probe card are connected to pads of a semiconductor chip. FIG. 6 is a side view of the alignment device. [Description of Signs] 1 Vacuum chuck 2 Semiconductor wafer 2a Semiconductor chip 3 Probe needle 4 Needle-type probe card 5 Wiring layers 6, 14 on needle-type probe card Power supply 7, 15 Ground 8 Input signal sources 9, 13, 23 Current 10, 37 Thin film probe card 11 First wiring layer 12 Second wiring layer 16, 31 Bump 17 Input signal wiring layer 18, 30 Pad 19 Input protection circuit 20 N-channel MOS transistor 21 Resistor 22 Internal circuit 24 voltage source 25 first wiring group 26 second wiring group 27 third wiring group 28 probe card 29 semiconductor chip 32 wiring layer 33 flexible substrate 34 contact 35 probe card position detection camera 36 semiconductor wafer stage 38 semiconductor wafer alignment Camera 39 Probe card stage 40 X Control motor control motor 41 Y-axis control motor 42 theta 43 Z-axis control mechanism 44 heater

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Akira Miyanaga 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-6-310577 (JP, A) JP-A-2- 216477 (JP, A) Special Table Hei 5-507177 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/66 G01R 1/073 G01R 31/26

Claims (1)

(57) [Claim 1] A step of actually measuring each operating current value of a plurality of semiconductor chips formed on a semiconductor wafer, and a step of calculating a sum of the respective operating current values by calculation; Connecting the electrodes of the plurality of semiconductor chips to the probe terminals of the probe card; measuring the total operating current value of the plurality of semiconductor chips; and summing the operating current values and the total operating current value. Calculating the difference between the two, and when the difference between the sum of the operating current values and the total operating current value is smaller than the minimum value of the operating current values, all the electrodes of the plurality of semiconductor chips and A step of deeming that all probe terminals of the probe card are connected.