JP3474669B2 - Semiconductor device inspection method and probe card - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection method for simultaneously inspecting and burning in a plurality of semiconductor chips on a semiconductor wafer in a wafer state, and a probe card used for this inspection.

[0002]

2. Description of the Related Art In recent years, there have been remarkable advances in miniaturization and cost reduction of electronic equipment equipped with a semiconductor integrated circuit device, and there is an increasing demand for miniaturization and cost reduction of the semiconductor integrated circuit device. There is. Usually, a semiconductor integrated circuit device is electrically connected to a lead frame by wire bonding or the like, supplied in a form sealed with resin or ceramic, and mounted on a printed circuit board of an electronic device.

However, due to the demand for miniaturization of electronic equipment, a method of directly mounting a semiconductor integrated circuit device in a state of being cut out from a semiconductor wafer (hereinafter referred to as a bare chip state) on a circuit board of the electronic equipment is developed. It is desired to supply bare chips with no quality guarantee at a low price.

In order to guarantee the quality of a semiconductor integrated circuit device in a bare chip state, it is necessary to perform burn-in in a semiconductor wafer state or a bare chip state. However, the burn-in in the bare chip state is very complicated in handling and cannot meet the demand for cost reduction. In addition, it takes a very long time to burn-in a large number of semiconductor integrated circuit devices (hereinafter referred to as semiconductor chips) simultaneously formed on a semiconductor wafer one by one or several times at a time. It is not realistic in terms of cost and cost.
Therefore, it is becoming important to burn-in all the semiconductor chips simultaneously in a semiconductor wafer state.

In order to carry out batch burn-in in a semiconductor wafer state, it is necessary to simultaneously apply a power supply voltage and an input signal to a plurality of semiconductor chips formed on the semiconductor wafer to operate them. For this purpose, it is necessary to prepare a probe card having an extremely large number of probe terminals (usually several thousand or more). However, the conventional needle type probe card cannot cope with the number of pins and the price. Therefore, a thin film type probe card in which bumps are provided on a flexible substrate has been considered (Nitto technique Vol. 28, No. 2).
Oct. 1990 pp. 57-62).

Burn-in using a thin film type probe card will be described below with reference to the drawings.

FIG. 6 is an explanatory view showing a state in which a thin film type probe card is connected to a semiconductor chip on a semiconductor wafer. In FIG. 6, 50 is a vacuum chuck, 51 is a semiconductor wafer, 52 is a semiconductor chip, 53 is a thin film type probe card, and 54 is a bump of the probe card 53.

At the time of wafer burn-in, the semiconductor wafer 51
Is placed on the vacuum chuck 50, and the vacuum chuck 50
The vacuum chuck 50 is fixed on the vacuum chuck 50 by drawing a vacuum through a plurality of holes provided on the upper surface. Further, a heater (not shown) and a temperature sensing device (not shown) are attached to the vacuum chuck 50, and the temperature of the semiconductor wafer 51 placed on the vacuum chuck 50 can be controlled.

The probe card 53 is provided with bumps 54 corresponding to the pads of the semiconductor chip 52 used at the time of burn-in for all the semiconductor chips 52 on the semiconductor wafer 51. The semiconductor chips 52
All pads and all bumps 5 on the probe card 53
4 and 4 can be connected at once.

FIG. 7 is a sectional view showing a state in which the pads of the semiconductor chip and the bumps of the probe card are connected. In FIG. 7, 53 is a probe card, 54 is a bump of the probe card 53, 55 is a wiring layer of the probe card 53, 56 is a flexible substrate made of a polyimide film, 5
7 is a contact, 52 is a semiconductor chip, 58 is a pad of the semiconductor chip 52, 59 is a passivation film,
60 is a polyimide film.

The probe card 53 is a flexible substrate 5.
6 has a wiring layer 55, bumps 54, and contacts 57 connecting them. On the other hand, the semiconductor chip 52 to be inspected is provided with pads 58 for power supply, ground, and input / output signals. Further, the surface other than the pad 58 has an insulating passivation film 59 for protecting the internal integrated circuit and an insulating material for preventing the surface of the semiconductor chip 52 from being separated from the package resin when the semiconductor chip 52 is packaged. Polyimide film 6
Covered by 0s.

The probe card 53 is pressed against the semiconductor chip 52 to connect the pad 58 and the bump 54. The pads 58 and the bumps 54 are connected to all the pads 58 and all the bumps 54 at the same time. In this state, the inspection can be performed by applying the power supply voltage or the input signal to the pad 58 via the wiring layer 55.

Normally, electrical measurement is performed in this state,
When performing measurement at high temperature during wafer burn-in,
By energizing the heater of the vacuum chuck 50,
And the semiconductor wafer 51 are heated.

[0014]

However, in the method of performing the batch burn-in in a wafer state by using the above-mentioned thin film type probe card, when defective semiconductor chips exist among a plurality of semiconductor chips on a semiconductor wafer, Since the power supply voltage and the input signal are supplied also to the defective semiconductor chip, there is a problem that batch burn-in in a wafer state becomes impossible.

As a reason why the defective semiconductor chips cannot be collectively burned in the wafer state, the case where the power supply line of the semiconductor chip is defective and the case where the input signal line of the semiconductor chip is defective will be described respectively.

First, the case where the power supply line is defective will be described. Usually, the power supply wiring layer on the probe card is shared in order to reduce the amount of the wiring layer on the probe card and the number of power supplies of the tester. In such a case, if the power supply wiring line of the defective semiconductor chip and another wiring line are short-circuited, a large current will flow through the defective semiconductor chip, and the power supply voltage of the defective semiconductor chip will decrease. Since the power supply voltage of the non-defective semiconductor chip also drops, normal burn-in cannot be performed. Also, if the wiring layer for the power supply is not shared on the probe card, the amount of the wiring layer on the probe card increases significantly, which is not realistic. Further, in any case, a large amount of current flows through the defective semiconductor chip and the wiring layer connected to the defective semiconductor chip to generate heat and the temperature rises, which causes an increase in the temperature of the peripheral semiconductor chips, which is an obstacle to normal burn-in. .

Next, the case where the input signal line is defective will be described. Similar to the case of the power supply line, it is desirable to share the input signal wiring layer on the probe card in order to reduce the number of wiring layers on the probe card and the number of input signal sources of the tester. In such a case, if the wiring line for the input signal of the defective semiconductor chip and another wiring line are short-circuited, the input signal on the wiring layer for the input signal will be abnormal and completely different from the normal signal. Signal becomes abnormal, an abnormal input signal is supplied to other good semiconductor chips, and normal burn-in cannot be performed. In order to avoid this, the wiring layers for input signals and the input signal sources for each semiconductor chip should be independent, but the amount of wiring layers on the probe card and the number of input signal sources of the tester increase, and It is not realistic because the cost of the device increases significantly.

Further, a defect in the power supply wiring line or the input signal wiring line may occur not only before the burn-in but also during the burn-in. Before the burn-in, the defective semiconductor chip is removed by some method. Even if it is removed, there is also a problem that it is not possible to remove all the defective semiconductor chips generated during burn-in.

In view of the above, it is an object of the present invention to provide a method for removing the influence of defective semiconductor chips on a semiconductor wafer when performing batch burn-in in a wafer state by using a low-cost inspection apparatus.

[0020]

In order to achieve the above object, a method of inspecting a semiconductor device according to the present invention uses a probe card for a plurality of semiconductor chips formed in a matrix on a semiconductor wafer. The present invention is directed to a method for inspecting a semiconductor device for determining the quality of a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a first electrode and a second electrode for supplying a power supply voltage and is arranged in the row direction. The first electrodes of the plurality of semiconductor chips are connected in common and the second electrodes of the plurality of semiconductor chips arranged in the column direction are connected in common, and the first electrodes of the plurality of semiconductor chips are connected to each other. Direction to supply a power supply voltage through the first switching means to perform an inspection for determining the quality of the plurality of semiconductor chips, and by operating the first switching means, While continuing the supply of the power supply voltage to the line only non-defective semiconductor chip in the body wafer is present, the step of stopping the supply of the power supply voltage to the line on which the semiconductor chip is present defective in a semiconductor wafer,
A step of supplying a power supply voltage to the second electrodes of the plurality of semiconductor chips from the column direction via the second switching means to perform an inspection for determining the quality of the plurality of semiconductor chips, and operating the second switching means. Thus, while continuing the supply of the power supply voltage to the row of the semiconductor wafer in which only good semiconductor chips exist, while stopping the supply of the power supply voltage to the row of the semiconductor wafer in which the defective semiconductor chip exists It is characterized by being

In the semiconductor device inspection method according to the present invention, it is preferable that the first switching means and the second switching means are formed in a plurality of semiconductor chips.

The probe card according to the present invention is intended for the probe card for carrying out the method for inspecting a semiconductor device according to the present invention. The probe card extends in the row direction and is provided in parallel in the column direction. A first wiring group formed of a plurality of wiring layers for commonly supplying a power supply voltage to one electrode is provided in parallel with the first wiring group extending in the column direction and in the row direction, and is connected to the second electrode of the semiconductor chip in each column. And a second wiring group composed of a plurality of wiring layers for commonly supplying a power supply voltage.

[0023]

According to the method of manufacturing a semiconductor device or the probe card of the present invention, the power supply voltage is supplied to a row or a column that does not include defective chips, that is, all the semiconductor chips are not defective chips. In the row or the column including the defective chip, the power supply voltage is not supplied because the current exceeding the standard value flows.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device inspection method and a probe card according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram of a method for removing a defective semiconductor chip in the semiconductor device inspection method according to the first reference example. In FIG. 1, 1 is a vacuum chuck, 2 is a semiconductor wafer, 2a is a semiconductor chip, 3 is a probe needle, 4 is a needle type probe card, 5 is each wiring layer of the probe card 4, 6 is a power supply, 7 is a ground, Reference numeral 8 is an input signal source, and 9 is an ammeter.

Before the burn-in of the semiconductor wafer 2, each semiconductor chip 2a on the semiconductor wafer 2 is subjected to a probe test to determine whether it is a good product or a defective product. In probe inspection, a full auto prober is usually used to inspect a plurality of semiconductor chips 2a formed on the semiconductor wafer 2 in a semiconductor wafer state. The semiconductor wafer 2 is vacuum-chucked by pulling a vacuum through a plurality of holes provided on the upper surface of the vacuum chuck 1 inside the full-auto prober.
Fixed to.

Next, a probe card 4 having a probe needle 3 made of, for example, tungsten is placed on the semiconductor wafer 2, and the probe needle is placed on each pad (not shown) of the semiconductor chip 2a on the semiconductor wafer 2. 3 and the semiconductor chip 2 via the wiring layer 5 on the probe card 4.
The power supply pad of a is connected to the ammeter 9 and the power supply 6, the ground pad of the semiconductor chip 2a is connected to the ground 7, and the input signal pad of the semiconductor chip 2a is input to the tester (not shown). By connecting to the signal source 8 and detecting the output signal, the semiconductor chips 2a are inspected one by one.

As a result of the inspection, if the semiconductor chip 2a is defective and the cause of the defect is an abnormally large current, the wiring line for power supply of the semiconductor chip 2a and another wiring line are short-circuited. It is believed that At this time, for the power supply wiring line of the semiconductor chip 2a,
A high voltage, for example 100 V, is applied by using the power source 6 of the tester through the power source pad, the probe needle 3 and the power source wiring layer 5 on the probe card. Since the wiring line of the semiconductor chip 2a is composed of a fine aluminum wiring layer having a width of about 10 μm and a thickness of about 1 μm,
By applying this high voltage, a large amount of current flows in the wiring line, the wiring temperature rises rapidly, and the wiring line melts and breaks. As a result, the power supply pad of the semiconductor chip 2a is electrically disconnected from the internal circuit.

If the cause of the defect of the semiconductor chip 2a is the leak of the pad for the input signal, it is considered that the wiring line for the input signal of the semiconductor chip 2a and another wiring line are short-circuited. At this time, a high voltage is applied to the input signal pad of the semiconductor chip 2a in the same manner as above,
Separate the electrical connection between the input signal pad and the internal circuit. Then, by the alignment function of the full-auto prober, the probe needle 3 is set on the pad for the input signal of the semiconductor chip 2a to be inspected next, and the inspection is performed in the same manner as above, and the high voltage to the pad having the leak is generated. The semiconductor chip 2a connected to the pad by applying the voltage
Break the wiring line of. By repeating this procedure, for all defective semiconductor chips 2a on the semiconductor wafer 2,
Disconnect the electrical connection between the leaking pad and internal circuitry.

After electrically disconnecting the defective semiconductor chip 2a, wafer burn-in is performed on the semiconductor wafer 2. For all of the semiconductor chips 2a on the semiconductor wafer 2, a thin film type probe card having a common power supply wiring layer and input signal wiring layer is accurately arranged, and pads on the semiconductor wafer 2 and thin film type The bumps on the probe card are electrically connected, the temperature is raised, and the power supply voltage and the input signal are applied.

At this time, since the pad having the input leak in the defective semiconductor chip 2a is separated from the internal circuit by the high voltage application at the time of the probe inspection, the defective semiconductor chip 2a is a thin film type probe card. It is not electrically connected to the upper common wiring layer. As a result, batch burn-in in a wafer state is normally performed on non-defective semiconductor chips 2a connected to the same common wiring layer at the time of probe inspection.

Next, a second reference example of the present invention will be described with reference to the drawings. FIG. 2 is a cross-sectional view showing the connection between the pads of the semiconductor chip and the bumps of the probe card at the time of wafer burn-in in the semiconductor device inspection method according to the second reference example. In FIG. 2, 10 is a thin film type probe card, 11 is a bump of the probe card 10, 12 is a wiring layer of the probe card 10, 13 is a flexible substrate made of a polyimide film, 14 is a contact, 2a is a semiconductor chip, and 15 is a semiconductor. The chip 2a is a pad, 16 is a passivation film, and 17 is a polyimide film.

In the second reference example, the probe inspection is performed before forming the passivation film 16. The probe inspection determines whether each semiconductor chip 2a on the semiconductor wafer is a good product or a defective product. Then, after forming the passivation film 16, the passivation film 16 on the pad 15 is formed.
The process of forming an opening is performed. A mask having a pattern for forming openings is prepared in advance. Next, a photoresist is applied to the surface of the semiconductor wafer, and the pattern of the opening on the mask is exposed and transferred onto the photoresist on the semiconductor chip 2a using a stepper every several chips. At this time, the mask is shielded from the defective semiconductor chip 2a found during the probe inspection so that the pattern of the opening on the mask is not transferred to the photoresist on the semiconductor chip 2a.

Then, when the photoresist is developed and the passivation film 16 is etched, an opening is formed in the passivation film 16 on the pad 15 for the good semiconductor chip 2a, but the defective semiconductor chip 2a is formed.
However, no opening is formed in the passivation film 16 on the pad 15, and the pad 15 is covered with the insulating passivation film 16. After that, the polyimide film 17 is formed over the entire surface of the semiconductor wafer. Then, openings are formed in the polyimide film 17 on the pads 15 of all semiconductor chips, not limited to non-defective products.

Thereafter, wafer burn-in is performed on this semiconductor wafer. Semiconductor chip 2 on a semiconductor wafer
For all of a, the probe card 10 having the common power supply wiring layer and input signal wiring layer is accurately arranged, and the pad 15 and the probe card 10 on the semiconductor wafer are arranged.
The bumps 11 are electrically connected to each other, and the temperature is raised to apply a power supply voltage and an input signal.

In the defective semiconductor chip 2a, the pad 15 in which the input leakage has occurred is covered with the insulating passivation film 16 covering the pad 15 to provide the probe card 10.
Since it is electrically insulated from the upper bump 11, the defective semiconductor chip 2 a is not electrically connected to the common wiring layer on the probe card 10. Therefore, the batch burn-in is normally executed in the wafer state for the good semiconductor chips 2a connected to the same common wiring layer.

Next, a third reference example of the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view showing the connection between the pads of the semiconductor chip and the bumps of the probe card at the time of wafer burn-in in the semiconductor device inspection method according to the third reference example. 3, the same members as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

In the third reference example, first, the passivation film 16 is formed over the entire surface of the semiconductor wafer. Then, after forming openings in the passivation film 16 on the pads 15 of all the semiconductor chips, a probe test is performed before forming the polyimide film 17. The probe inspection determines whether each semiconductor chip 2a on the semiconductor wafer is a good product or a defective product. After that, polyimide film 1
After forming 7, the step of forming an opening in the polyimide film 17 on the pad 15 is performed. A mask having a pattern of openings is prepared in advance. Next, a photosensitive polyimide film 17 is applied on the surface of the semiconductor wafer, and the pattern of the opening on the mask is exposed and transferred onto the polyimide film 17 on the semiconductor chip 2a using a stepper every several chips. At this time, the defective semiconductor chip 2 found during the probe inspection
For a, the mask is shielded from light so that the pattern of the opening on the mask is not transferred to the polyimide film 17 on the semiconductor chip 2a.

After that, when the polyimide film 17 is developed,
An opening is formed in the polyimide film 17 on the pad 15 for the non-defective semiconductor chip 2a, but no opening is formed in the polyimide film 17 on the pad 15 for the defective semiconductor chip 2a. 15 is covered with an insulating polyimide film 17.

Thereafter, wafer burn-in is performed on the semiconductor wafer. For all the semiconductor chips 2a on the semiconductor wafer, the probe card 10 having the common power supply wiring layer and input signal wiring layer is accurately arranged,
The pads 15 on the semiconductor wafer and the bumps 11 on the probe card 10 are electrically connected, and the temperature is raised to apply a power supply voltage or an input signal.

The pad 15 of the defective semiconductor chip 2a, which has an input leak, is electrically insulated from the bump 11 of the probe card 10 by the insulating polyimide film 17 covering the pad 15. The defective semiconductor chip 2a is not electrically connected to the common wiring layer on the probe card 10. Therefore, the batch burn-in in the wafer state is normally executed for the good semiconductor chips 2a connected to the same common wiring layer.

Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an explanatory diagram of a method for removing a defective semiconductor chip during wafer burn-in in the semiconductor device inspection method according to the first embodiment. In FIG. 4, 2 is a semiconductor wafer, 2a is a semiconductor chip formed in a matrix on the semiconductor wafer 2, 18 is a bump on a probe card (not shown), and 19 is a wiring layer for input signals on the probe card. Is.

Here, the semiconductor chip 2a is provided with two pads for power supply, and when a power supply voltage is supplied to one or both of the two pads for power supply, the semiconductor chip 2a is normally operated. On the other hand, when power is not supplied to both of the two power supply pads, the input signal pads of the semiconductor chip 2a and other pads are not electrically connected to the internal circuit of the semiconductor chip 2a. Designed to be separated.

Further, 20a, 20b, 20c, 20d and 20e are wiring layers on the probe card which are connected to the power source in the row direction as the first wiring group and are independent of each other, and the semiconductor chips 2a of each row are connected. The first power supply pad is connected in parallel. 21a, 21b, 21c, 21d and 21e are wiring layers on the probe card connected to the power source in the column direction as the second wiring group, which are independent of each other, and are the second power source of the semiconductor chips 2a in each column. Connected in parallel to the pad for. 22a, 22b, 22c, 22d and 22e are wiring layers for transmitting signals for turning on / off the row direction power supply switching means (first switching means) as the third wiring group, 23a, 23b, 23c,
Reference numerals 23d and 23e are wiring layers for transmitting a signal for turning on / off the column-direction power supply switching means (second switching means) as the fourth wiring group. Also, VD
D is a power supply voltage, and Sig is a switching signal.

Next, FIG. 5 is a circuit diagram showing an example of the switching means provided in the semiconductor chip 2a. In FIG. 5, 20 is the first wiring group 20a, 20b, 20c, 2
One wiring layer of 0d and 20e, 21 is one wiring layer of the second wiring groups 21a, 21b, 21c, 21d and 21e, and 22 is a third wiring group 22a, 22b, 22
One of the wiring layers c, 22d and 22e, and 23 is the fourth
Of one of the wiring groups 23a, 23b, 23c, 23d and 23e, 24 is a first P-channel MOS transistor as a first switching means, and 25 is a second P-channel MOS transistor as a second switching means. P-channel MO
The S transistor, 26 is a wiring line for power supply of the internal circuit of the semiconductor chip 2a.

In the above-mentioned structure, the semiconductor chip A is shown as an example in which the semiconductor chip A shown in FIG. 4 is short-circuited between the power supply and the ground during the wafer burn-in.
Exclude from the burn-in.

First, burn-in of all the semiconductor chips 2a on the semiconductor wafer 2 is performed in a wafer state. Power is supplied from the first wiring group 20a, 20b, 20c, 20d and 20e. At this time, the third wiring groups 22a, 22
Signals for turning on the first P-channel type MOS transistors connected to them are transmitted from b, 22c, 22d and 22e. In addition, the second wiring groups 21a, 21
Power supply from b, 21c, 21d, and 21e is stopped, and the fourth wiring groups 23a, 23b, 23c, and 23 are stopped.
A signal for turning off the second P-channel type MOS transistor connected thereto is transmitted from d and 23e. Further, an input signal for operating the semiconductor chip 2a is input to the semiconductor chip 2a from the input signal wiring layer 19.

In this state, for example, if the power supply line and the ground line are short-circuited in the semiconductor chip A and a defect that an overcurrent flows occurs, power is immediately supplied from the wiring layer 20b of the first wiring group. When stopped, the third wiring groups 22a, 22b, 22c, 22d and 2 are temporarily stopped.
A signal for turning off the first P-channel type MOS transistor is transmitted from 2e.

Referring to FIG. 5, first, power is supplied from one wiring layer 20 of the first wiring group, and power supply is stopped from one wiring layer 21 of the second wiring group. I'll do it. In addition, one wiring layer 2 of the third wiring group
2 is a “Low” level to turn on the first P-channel MOS transistor 24, and one wiring layer 23 of the fourth wiring group is a “High” level to the second P-channel MOS transistor 24.
The transistor 25 is turned off. When the above-mentioned defect occurs in the semiconductor chip A, the power supply from one wiring layer 20 of the first wiring group is stopped, and one wiring layer 21 of the second wiring group is further set. At the low level, the first P-channel MOS transistor 24 is turned off.

For these operations, a current sensor is provided externally for each row-direction power supply, and when a power supply in which a current exceeding the proper current range flows is generated, the function of stopping the power supply and the first P-channel MOS transistor 2
A function of generating a signal for turning off 4 may be added.

After that, the second wiring groups 21a, 21b, 2
A signal for starting the power supply from 1c, 21d and 21e and turning on the second P-channel MOS transistor 25 connected to them from the fourth wiring group 23a, 23b, 23c, 23d and 23e. To convey.
Since an overcurrent flows through the wiring layer 21c of the second wiring group this time, immediately when the overcurrent is detected, the power supply from the wiring layer 21c of the second wiring group is stopped and the fourth A signal for turning off the second P-channel type MOS transistor 25 is transmitted from the wiring layer 23c of the wiring group of. After that, a signal for turning on the first P-channel MOS transistor 24 of the third wiring group 22a, 22c, 22d, and 22e other than the row in which the overcurrent flows is transmitted, and the power supply to those rows is performed. Start.

The other semiconductor chips 2a in the same row as the semiconductor chip A have second wiring groups 21a, 21b, 21d and 21.
The power is supplied from e, and the other semiconductor chips 2a in the same column as the semiconductor chip A are connected to the first wiring groups 20a, 20
Power is supplied from c, 20d, and 20e. The wiring layer 20b of the first wiring group and the power supply wiring line inside the semiconductor chip 2a connected to the wiring layer 20b and the second wiring layer 20b
The wiring layer 21c of the wiring group and the wiring line for the power supply inside each semiconductor chip 2a connected to the wiring layer 21c are cut off by switching off the switching means.

Normally, when an overcurrent defect occurs in the semiconductor chip 2a on the semiconductor wafer 2 during burn-in, the defective semiconductor chip A generates heat due to the current and the temperature of the other good semiconductor chip 2a rises. However, there is a problem that the burn-in temperature is changed and a problem that the correct power supply voltage cannot be applied to the other good semiconductor chip 2a due to the overcurrent.
Another non-defective semiconductor chip 2 via the wiring layer 20b of the first wiring group and the wiring layer 21c of the second wiring group
The current does not flow from the defective semiconductor chip A to the defective semiconductor chip A, and these problems can be solved, and the power supply to only the semiconductor chip A can be stopped and the semiconductor chip A can be removed from the burn-in.

In the first embodiment, the semiconductor chip A is described as having a defect. However, even if another semiconductor chip 2a on the semiconductor wafer 2 has a defect, the semiconductor chip A can be similarly removed during burn-in.

Although the defective semiconductor chip A generated during burn-in is removed in the first embodiment, it can also be used for removing the defective semiconductor chip 2a before burn-in.

Although the switching means is provided in the semiconductor chip 2a in the first embodiment, it may be provided in the probe card.

Furthermore, in the first embodiment, a short circuit defect between the power supply line and the ground line of the semiconductor chip A is taken as an example, but other defects can be removed from the burn-in. It detects an output signal from each semiconductor chip 2a, and as a result, supplies a signal for turning off the switching means to the semiconductor chip 2a in which the defect is found, while stopping the power supply from the row direction and the column direction. .

[0058]

According to the semiconductor device inspection method or the probe card of the present invention, the power supply voltage is supplied to the rows or columns in which no defective chips are included, that is, all the semiconductor chips are not defective chips. On the other hand, in the row or column including the defective chip, the power supply voltage is not supplied because the current more than the standard value flows, so that the burn-in inspection for the normal semiconductor chip is hindered due to the decrease of the power supply voltage. The situation will not occur.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a method for removing a defective semiconductor chip in a semiconductor device inspection method according to a first reference example of the present invention.

FIG. 2 is a cross-sectional view showing a connection between a pad of a semiconductor chip and a bump of a probe card at the time of burn-in in a semiconductor device inspection method according to a second reference example of the present invention.

FIG. 3 is a cross-sectional view showing a connection between a pad of a semiconductor chip and a bump of a probe card at the time of burn-in in a semiconductor device inspection method according to a third reference example of the present invention.

FIG. 4 is an explanatory diagram of a method for removing a defective semiconductor chip during burn-in in the semiconductor device inspection method according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a switching means in the semiconductor device inspection method according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a connection state between a conventional semiconductor wafer and a thin film type probe card.

FIG. 7 is a cross-sectional view showing a connection between a pad of a conventional semiconductor chip and a bump of a thin film type probe card.

[Explanation of symbols]

1,50 vacuum chuck 2,51 semiconductor wafer 2a, 52 semiconductor chips 3 probe needle 4-needle probe card 5, 12, 55 wiring layers 6 power supplies 7 grand 8 input signal sources 9 ammeter 10,53 Thin film probe card 11, 18, 54 bumps 13,56 flexible board 14,57 contacts 15,58 pads 16,59 passivation film 17,60 Polyimide film 19 Input signal wiring layer 20a, 20b, 20c, 20d, 20e First wiring group 20 One wiring layer of the first wiring group 21a, 21b, 21c, 21d, 21e Second wiring group 21 One wiring layer of the second wiring group 22a, 22b, 22c, 22d, 22e Third wiring group 22 One wiring layer of the third wiring group 23a, 23b, 23c, 23d, 23e Fourth wiring group 23 One wiring layer of the fourth wiring group 24 First P-Channel MOS Transistor 25 Second P-channel MOS transistor Wiring line for 26 power supplies VDD power supply voltage Sig switching signal A defective semiconductor chip

Continuation of the front page (56) Reference JP-A-4-196241 (JP, A) JP-A-5-2111219 (JP, A) JP-A-5-3239 (JP, A) JP-A-6-5677 (JP , A) JP-A-5-121502 (JP, A) JP-A-6-5673 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/66 G01R 1/073 H01L 21/822 H01L 27/04

Claims (3)

(57) [Claims] 1. A probe card is used for a plurality of semiconductor chips formed in a matrix on a semiconductor wafer .
And collectively judge the quality of the semiconductor chips.
A method of inspecting a semiconductor device, wherein each of the plurality of semiconductor chips is for supplying a power supply voltage.
The semiconductor chip includes a first electrode and a second electrode, and the first electrodes of the plurality of semiconductor chips arranged in the row direction are shared.
The plurality of halves are connected to each other and are arranged in the row direction.
The second electrodes of the conductor chips are commonly connected to the first electrodes of the plurality of semiconductor chips in the row direction .
A step of supplying a power supply voltage through the switching means to carry out an inspection for judging the quality of the plurality of semiconductor chips, and by operating the first switching means, only good semiconductor chips in the semiconductor wafer are while continuing the supply of the power supply voltage against the row exists, the row in which the semiconductor chip of the defective in the semiconductor wafer is present
Step and, from said column direction to the second electrode of the plurality of semiconductor chips second to stop the supply of the power supply voltage against the
The step of supplying a power supply voltage through the switching means to perform an inspection for determining the quality of the plurality of semiconductor chips, and operating the second switching means
There are only good semiconductor chips on the semiconductor wafer.
To while continuing the supply of the power supply voltage to the column, the column on which the semiconductor chip of the defective in the semiconductor wafer is present
A method of inspecting a semiconductor device, characterized by comprising a step of stopping the supply of the power supply voltage against the. 2. The method for inspecting a semiconductor device according to claim 1 , wherein the first switching means and the second switching means are formed in the plurality of semiconductor chips. 3. A semiconductor device inspection method according to claim 1.
A probe card for carrying out the method, comprising: a plurality of wiring layers that extend in the row direction and are provided in parallel in the column direction, and that commonly supply a power supply voltage to the first electrodes of the semiconductor chips in each row. A second wiring group which is provided in parallel with one wiring group and which is provided in parallel in the column direction and in the row direction and which supplies a common power supply voltage to the second electrodes of the semiconductor chips in each column. A probe card characterized by comprising: