JP3443947B2 - Burn-in dedicated wafer and burn-in method using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burn-in dedicated wafer for performing burn-in of a burn-in wafer in a wafer state and a burn-in method using the same.

[0002]

2. Description of the Related Art Conventionally, a screening test for burn-in to an IC chip (intentionally applying stress due to temperature and voltage to an IC chip in a wafer state to eliminate an initial failure) is performed on the same wafer. Screening by setting probe pins for each of a number of IC chips and supplying power to perform testing, or scribing after each IC chip, then packaging, and then supplying power from lead pins. The method of doing the test is taken.

However, such a method for each IC chip is complicated and requires a large number of test steps. On the other hand, a method in which a plurality of IC chips in a wafer state are burned in at the same time is disclosed in JP-A-6-6
9298 and the like. In this device, each IC chip is provided with wiring such as a power supply line and a ground line, and a voltage is supplied in parallel to all the IC chips so that burn-in is performed at the same time.

[0004]

However, in this device, wiring such as a power supply line and a ground line to each IC chip is formed on a scribe line between the chips. Since a test transistor or the like for process control is usually formed on this scribe line, it is not preferable to form a burn-in wiring on such a scribe line to supply voltage.

The present invention has been made in view of the above problems. For a burn-in wafer to be burned in,
An object of the present invention is to solve the above-mentioned problem by supplying a voltage for burn-in by using a burn-in-dedicated wafer bonded to this.

[0006]

In order to achieve the above object, the present invention provides a plurality of I's according to the invention described in claim 1.
A plurality of burn-in dedicated chips (2) are formed at positions corresponding to the plurality of IC chips (8) on a burn-in wafer (7) having C chips (8),
A burn-in dedicated wafer (1) bonded and fixed to the burn-in target wafer (7) when performing burn-in, wherein each of the burn-in dedicated chips (2) is
Wherein together with a voltage supply means for supplying voltage to the position of the IC chip against <br/> respond when the burn-in wafer (7) is bonded (8) (61, 62), burn Shin
Built-in burn-in circuit (5)
The burned-in wafer (7)
When it is exposed, the IC chip (8) is electrically contacted with
Burn-in signal supply means for supplying a burn-in signal (6
3, 64) .

According to a second aspect of the present invention, in the first aspect of the present invention, a wiring pattern (3, 4) for supplying a burn-in voltage to each surface of the plurality of burn-in dedicated chips (2). Are formed on the wiring pattern (3, 4).
2) is electrically connected.
According to the invention described in claim 3, in the invention described in claim 2,
And each of the plurality of burn-in chips (2)
The wiring pattern (3, 4) formed on the surface of the
Only two, pattern (3) and ground pattern (4)
It is characterized by In the invention according to claim 4,
Is the burn-in target according to the third aspect of the invention.
The size of the burned-in wafer is larger than that of the wafer (7).
The power pattern when the wafer (7) is attached
The power contact (31) of (3) and the ground pad
The ground contact (41) of the turn (4) should be
So that it is located outside the outer circumference of the burn-in wafer (7)
It is characterized by becoming. According to a fifth aspect of the invention, in the invention according to any one of the first to fourth aspects, the voltage supply means (61, 62) is electrically connected when the burn-in wafer (7) is bonded. It is characterized in that it is a bump for voltage supply (61, 62) that contacts the IC chip and supplies a voltage to the IC chip (8).
In the invention according to claim 6, any one of claims 1 to 5
In the invention described in one aspect, the burn-in dedicated circuit
(5) is reset when the burn-in voltage is supplied.
The power-on reset circuit (54) that outputs a
The burn-in is opened after the reset signal is output.
It is characterized by starting.

[0008]

According to a seventh aspect of the invention, there is provided a burn-in method in which the burn-in wafer (7) is burned in using the burn-in-dedicated wafer (1) according to any one of the first to sixth aspects. The burn-in wafer (7) is bonded and fixed to the burn-in dedicated wafer (1), and the voltage supply means (61) is applied to each of the burn-in dedicated chips (2) in the bonded and fixed state. sparse line voltage supplied through the 62)
Both are through the burn-in signal supply means (63, 64)
And performing the burn-in by supplying the burn-in signal .

According to an eighth aspect of the invention, in the seventh aspect , the bonding step includes the burn-in wafer (7) and the burn-in-only wafer (1).
It is characterized in that it is a step of bonding the two with an anisotropic conductive sheet (10) interposed therebetween. In addition,
The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0011]

According to the burn-in-dedicated wafer of the first aspect of the invention, a plurality of burn-in-dedicated chips are formed at positions corresponding to a plurality of IC chips on a burn-in wafer having a plurality of IC chips. It was done. This burn-in wafer is bonded and fixed to the burn-in wafer when performing burn-in. When the burn-in wafers are bonded, each of the burn-in-dedicated chips has an IC at a corresponding position.
Supply voltage to the chip.

Therefore, since the burn-in voltage is individually supplied to each IC chip of the burn-in wafer, the conventional problem of forming the burn-in wiring on the scribe line is solved. be able to. In the invention according to claim 1,
Each burn-in dedicated chip generates a burn-in signal.
It has a built-in burn-in circuit. Therefore, the covered bar
Burn-in wafers have a burn-in
Since it is not necessary to form a dedicated circuit for burn-in, its configuration
Can be simplified. In the invention of claim 2, a wiring pattern for supplying a burn-in voltage is formed on each surface of the burn-in-dedicated chips, and the voltage supply means is electrically connected to the wiring pattern. There is.

Therefore, since the wiring pattern is formed not on the burn-in wafer but on the surface of the burn-in dedicated chip of the burn-in dedicated wafer, the wiring pattern can be formed thick. Therefore, the resistance of the wiring can be set extremely low, so that each IC of the burn-in wafer is
It is possible to supply a stable burn-in voltage to the chip.

The voltage supply from the burn-in-dedicated chip to the IC chip can be carried out by using voltage supply bumps for supplying a voltage to both wafers when they are bonded to each other .

Further, when performing burn of the burn-in wafer, as in the invention according to claim 7, to be burn-wafer bonding and secured to burn only the wafer, the voltage is supplied from a burn only the wafer to be burn wafer Burn in. At this time, as described in claim 8 , the anisotropic conductive sheet is interposed between the burned-in wafer and the burn-in dedicated wafer to bond the both, so that the electrical connection between the both can be surely performed. it can.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view of a burn-in dedicated wafer viewed from the pattern surface, FIG. 2 is an enlarged view of a portion A, and FIG. 3 is an enlarged view of a portion B in FIG. A plurality of burn-in dedicated chips 2 having the same chip size and pitch as the burn-in wafer 7 to be described later are formed on the burn-in dedicated wafer 1, and a power source Al pattern 3 and a ground Al pattern 4 are formed on these burn-in dedicated chips 2. The pattern is formed as shown in FIG.

Each burn-in dedicated chip 2 is
A power supply bump 61, a ground bump 62, and a plurality of burn-in signal bumps 63 and 64 are formed, and a burn-in dedicated circuit 5 is provided inside thereof. In addition, the power supply bump 61 and the ground bump 62 are the power supply Al.
The pattern 3 and the ground Al pattern 4 are electrically connected to each other and supply a power supply and a ground voltage to a burn-in wafer 7 to be described later.

As shown in FIG. 3, the burn-in dedicated circuit 5 is composed of an oscillation circuit 51, a frequency dividing circuit 52, a programmable logic array circuit (PLA) 53, etc., and includes a power source Al pattern 3 and a ground Al pattern 4. It operates by receiving the power supply of. A specific configuration of the burn-in dedicated circuit 5 is shown in FIG. When a reset signal is output from the power-on reset circuit (POR) 54 by the start of power supply, the oscillation circuit 51 then oscillates.
The oscillation output from the oscillation circuit 51 is frequency-divided by a frequency dividing circuit 52 including a plurality of counters. The clock (CL
K) signal and a test (TEST) signal are output. These signals are supplied from the burn-in signal bumps 63 and 64 to the corresponding IC chips of the burn-in wafer 7 described later.

FIG. 5 shows a state in which the burn-in wafer 1 is attached to the burn-in wafer 7. Further, FIG. 6 shows an enlarged view of the C portion in FIG. The burn-in-dedicated wafer 1 has a size larger than that of the burn-in-dedicated wafer 7, and the power contact 31 of the power Al pattern 3 and the ground contact 41 of the ground Al pattern 4 formed on the burn-in-dedicated wafer 1 are burned-in. It is located outside the outer periphery of the wafer 7. The power contact 31 and the ground contact 41 are electrically connected to the power connector 15 and the ground connector 16 of the housing 11 shown in FIG.

A plurality of burn-in chips (hereinafter simply referred to as IC chips) 8 having substantially the same size as the burn-in dedicated chip 2 are formed on the burn-in wafer 7, and each IC chip 8 has a power pad 81 and a ground pad. 82 and burn-in signal pads 83, 84 are formed. Then, in the state where the burn-in-only wafer 1 is attached to the burn-in wafer 7, the IC chip 8
Power is supplied to the power source through the power pad 81 and the ground pad 82. Here, FIG. 7 which is a DD ′ cross section in FIG.
As shown in FIG.
, And the anisotropic conductive sheet 10 to electrically connect to the power supply pad 81 of the IC chip 8. The ground pad 82 and the burn-in signal pads 83 and 84 are similarly electrically connected. In addition, 9 in the figure is a protective film.

The anisotropic conductive sheet 10 allows a current to flow only in the vertical direction and has a high impedance in the horizontal direction. Therefore, each bump 61 to 6
Even if the anisotropic conductive sheet 10 is used in the electrical connection according to No. 4, they can be electrically separated. As described above, the anisotropic conductive sheet 10 is used so that reliable electrical contact can be made even if the bumps 61 to 64 of the burn-in dedicated wafer 1 have height variations or the wafer is warped. This is because Therefore, the anisotropic conductive sheet 10 may be omitted if the electrical contact is surely made.

Further, burn-in signal bumps 63, 64
Supplies a clock signal and a test signal to the burn-in signal pads 83 and 84 of the IC chip 8. Each element in the IC chip 8 receives a test signal and enters a test mode, and receives a clock signal to perform a test operation. Since this type of test operation is well known in the art, its description is omitted. As the signal for the test operation, other signals than the clock signal and the test signal may be used, and in that case, the required number of burn-in signal pads are provided.

In the burn-in wafer 1,
The power source Al pattern 3 and the ground Al pattern 4 can be formed with a thick wiring pattern having a width of about half the chip size of the burn-in dedicated chip 2. For this reason,
A sufficient voltage can be supplied to each IC chip 8 of the burn-in wafer 7 via the power supply bump 61 and the ground bump 62.

That is, when power is supplied to all IC chips in parallel as described in Japanese Patent Laid-Open No. 6-69298, if wiring resistance is high or current consumption of individual IC chips is high, it may occur. Has a problem that a voltage drop of several volts occurs between the IC chip closest to the power supply part and the IC chip farthest from the power supply part, and it becomes impossible to perform burn-in to all the IC chips under the same conditions.
By forming the power source Al pattern 3 and the ground Al pattern 4 of the thick power source wiring on the burn-in wafer 1 as described above, the resistance of the power source wiring can be set extremely low. Therefore, sufficient power can be supplied to the entire IC chips, and simultaneous burn-in of them can be reliably performed.

The burn-in dedicated circuit 5 can be designed so that all burn-in wafers can be supported by the Al option or the like, and each burn-in wafer has a chip size, the number of burn-in signals, and a burn-in signal waveform. This can be handled by changing the Al option of the PLA 53 to be determined, the total number of bumps and the arrangement of each bump, and the power supply and ground Al patterns in consideration of the above. The layout of the power supply and ground Al patterns for the burn-in signal pads, which are different in number and arrangement for each burn-in wafer, can be easily laid out.

Next, burn-in will be described. The burn-in is performed by the device shown in FIG. In FIG. 8, a plurality of bonded wafers in which the burn-in wafer 7 is bonded to the burn-in dedicated wafer 1 are set in the housing 11. A power supply connector 15 and a ground connector 16 are provided above and below each wafer housing portion of the housing 11, and the power supply contact 31 and the ground contact 41 of each wafer are set by setting the wafer in the housing 11.
Then, the power connector 15 and the ground connector 16 are in electrical contact with each other.

Therefore, the power from the power supply device 12 is simultaneously supplied to a plurality of bonded wafers through the power supply wiring 13, the ground wiring 14, the power supply connector 15 of the housing 11 and the ground connector 16 to perform burn-in. Next, a procedure for performing this burn-in will be described. First, the burn-in wafer 1 is attached to the burn-in wafer 7. At that time, when it is necessary to make a reliable electrical contact as described above, the anisotropic conductive sheet 10 is sandwiched between the sheets and bonded. The bonded wafers are mechanically pressure-bonded with a wafer-dedicated clip or the like to maintain electrical contact.

This bonded wafer is set in the housing 11 shown in FIG. 8 and burn-in is performed. That is, by setting the bonded wafers in the housing 11, power is supplied from the power supply device 12 to each wafer via the power supply wiring 13, the ground wiring 14, the power supply connector 15, and the ground connector 16. PLA53
Burn-in signals such as clock signals and test signals output from the IC chip 8 are supplied to the IC chips 8 via the routes of the burn-in signal bumps 63 and 64 to the burn-in signal pads 83 and 84. Constant temperature bath (120 ° C-150 ° C) in this state
The housing 11 is put in and burn-in is performed. Further, in this burn-in, the voltage applied to each IC chip is
The voltage is, for example, 6 to 9 V for an IC chip operating at 5 V.

After the burn-in is completed, the burn-in-dedicated wafer 1 is removed and each IC chip 8 of the burn-in wafer 7 is removed.
On the other hand, a tester inspection is performed, and defective chips are sorted and removed by inking or the like. When performing burn-in in the wafer state, if a defective chip with a large current consumption is included,
The current may be concentrated on the defective chip, and an appropriate voltage may not be applied to other non-defective chips. Therefore, the wafer inspection is performed prior to the burn-in. As for the defective chip in this inspection, a fuse is made in series in the power supply Al array and the fuse automatically cuts off the power supply path when an excessive current flows, or Be sure to cut the fuse with a laser cutter, laser trimming, etc. Therefore, the burn-in is performed only on the chips which are determined to be non-defective in this wafer inspection.

[Brief description of drawings]

FIG. 1 is a view of a burn-in dedicated wafer showing an embodiment of the present invention as seen from a pattern surface.

FIG. 2 is an enlarged view of part A in FIG.

FIG. 3 is an enlarged view of a B part in FIG.

FIG. 4 is a circuit diagram showing a specific configuration of a burn-in dedicated circuit 5.

FIG. 5 is a diagram showing a state in which a burn-in dedicated wafer is attached to a burn-in wafer.

FIG. 6 is an enlarged view of a C portion in FIG.

7 is a cross-sectional view taken along the line D-D 'in FIG.

FIG. 8 is a configuration diagram of a burn-in device.

[Explanation of symbols]

1 Burn-in dedicated wafer 2 Burn-in dedicated chip 3 power supply Al pattern 4 Grand Al pattern 5 Burn-in circuit 7 Burn-in wafer 8 IC chips 10 Anisotropic conductive sheet 61 Power bump 62 grand bump 63, 64 Burn-in signal bump 81 Power pad 82 Grand Pad 83, 84 Burn-in signal pad

Front page continuation (72) Inventor Tetsuo Fujii 1-1-1, Showa-cho, Kariya city, Aichi Japan Denso Co., Ltd. (56) Reference JP-A-3-171749 (JP, A) JP-A-2-297941 (JP , A) JP-A-6-342600 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/66 G01R 31/26 G01R 31/28

Claims (8)

(57) [Claims] 1. A burn-in wafer having a plurality of IC chips, a plurality of burn-in dedicated chips are formed at positions corresponding to each of the plurality of IC chips, and are bonded and fixed to the burn-in wafer when performing burn-in. a burn-only wafer to be, each of the burn dedicated chip, which has a voltage supply means for supplying voltage to the position of the IC chip that corresponds to when the object to be burn-wafer is bonded,
Built-in burn-in dedicated circuit to create burn-in signal
And the burn-in wafer is bonded
When the IC chip is electrically contacted with the IC chip,
A burn-in dedicated wafer having burn-in signal supply means for supplying a burn-in signal . 2. A wiring pattern for supplying a burn-in voltage is formed on the surface of each of the burn-in-dedicated chips, and the voltage supply means is electrically connected to the wiring pattern. The burn-in dedicated wafer according to claim 1, wherein the wafer is a burn-in dedicated wafer. 3. That of said plurality of burn-in-only chips
The wiring pattern formed on each surface is the power supply pattern.
And a ground pattern
The dedicated burn-in wafer according to claim 2. 4. The size is larger than the burn-in wafer.
Before the burn-in wafer is bonded.
The power contact of the power pattern and the ground
The ground contact of the turn is the burn-in wafer
Characterized by being located outside the outer periphery of
The burn-in dedicated wafer according to claim 3. 5. The voltage supply means electrically contacts the IC chip when the burn-in wafers are bonded to each other, and
Burn dedicated wafer according to any one of claims 1 to 4, characterized in that a voltage supply bumps supplying voltage to the chip. 6. The burn-in-only circuit is the burn-in circuit.
When the input voltage is supplied, the power that outputs the reset signal
Provide a work-on reset circuit and output the reset signal
The burn-in is started later.
The burn-in dedicated wafer according to any one of 1 to 5
Ha. 7. A burn-in method of performing burn-in the target burn-in wafer using burn dedicated wafer according to any one of claims 1 to 6, bonding the target burn-in wafer into the burn dedicated wafer and fixing, via the front row Utotomoni the burn signal supply unit a voltage supply via the voltage supply means to each of the burn dedicated chip at the bonded fixed state
And a step of performing burn-in by supplying a burn-in signal . Wherein said bonding step is described wherein between the target burn-in wafers of the burn dedicated wafer to claim 7, characterized in that by interposing an anisotropic conductive sheet is a step of bonding the two Burn-in method.