JPH08279538A - Inspection of semiconductor device and probe card - Google Patents

Abstract

PURPOSE: To remove a defective semiconductor chip on a semiconductor wafer at the time when a batch-burn-in for semiconductor chips in the state of the wafer is conducted. CONSTITUTION: Before burn-in of a wafer is conducted, semiconductor chips 2a on the semiconductor wafer 2 are inspected using a needle probe card 4. A high voltate is applied to a pad of the semiconductor chip 2a detected to be a defective as the result of the inspection from a power supply 6 or an input signal source 8. When the high voltage is applied to the pad, a wiring pattern of an internal circuit connected with the pad is disconnected and the defective semiconductor chip 2a is electrically cut off from the other non- defective semiconductor chips 2a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device inspection method for simultaneously inspecting and burning in a plurality of semiconductor chips on a semiconductor wafer in a wafer state, and a probe card used for this inspection.

[0002]

2. Description of the Related Art In recent years, there have been remarkable advances in miniaturization and cost reduction of electronic equipment equipped with a semiconductor integrated circuit device, and there is an increasing demand for miniaturization and cost reduction of the semiconductor integrated circuit device. There is. Usually, a semiconductor integrated circuit device is electrically connected to a lead frame by wire bonding or the like, supplied in a form sealed with resin or ceramic, and mounted on a printed circuit board of an electronic device.

However, due to the demand for miniaturization of electronic equipment, a method of directly mounting a semiconductor integrated circuit device in a state of being cut out from a semiconductor wafer (hereinafter referred to as a bare chip state) on a circuit board of the electronic equipment is developed. It is desired to supply bare chips with no quality guarantee at a low price.

In order to guarantee the quality of a semiconductor integrated circuit device in a bare chip state, it is necessary to perform burn-in in a semiconductor wafer state or a bare chip state. However, the burn-in in the bare chip state is very complicated in handling and cannot meet the demand for cost reduction. In addition, it takes a very long time to burn-in a large number of semiconductor integrated circuit devices (hereinafter referred to as semiconductor chips) simultaneously formed on a semiconductor wafer one by one or several times at a time. It is not realistic in terms of cost and cost.
Therefore, it is becoming important to burn-in all the semiconductor chips simultaneously in a semiconductor wafer state.

In order to carry out batch burn-in in a semiconductor wafer state, it is necessary to simultaneously apply a power supply voltage and an input signal to a plurality of semiconductor chips formed on the semiconductor wafer to operate them. For this purpose, it is necessary to prepare a probe card having an extremely large number of probe terminals (usually several thousand or more). However, the conventional needle type probe card cannot cope with the number of pins and the price. Therefore, a thin film type probe card in which bumps are provided on a flexible substrate has been considered (Nitto Gikou Vol. 28, No. 28).
2 Oct. 1990 pp. 57-62).

Burn-in using a thin film type probe card will be described below with reference to the drawings.

FIG. 6 is an explanatory view showing a state in which a thin film type probe card is connected to a semiconductor chip on a semiconductor wafer. In FIG. 6, 50 is a vacuum chuck, 51 is a semiconductor wafer, 52 is a semiconductor chip, 53 is a thin film type probe card, and 54 is a bump of the probe card 53.

At the time of wafer burn-in, the semiconductor wafer 51
Is placed on the vacuum chuck 50, and the vacuum chuck 50
The vacuum chuck 50 is fixed on the vacuum chuck 50 by drawing a vacuum through a plurality of holes provided on the upper surface. Further, a heater (not shown) and a temperature sensing device (not shown) are attached to the vacuum chuck 50, and the temperature of the semiconductor wafer 51 placed on the vacuum chuck 50 can be controlled.

The probe card 53 is provided with bumps 54 corresponding to the pads of the semiconductor chip 52 used at the time of burn-in for all the semiconductor chips 52 on the semiconductor wafer 51. The semiconductor chips 52
All pads and all bumps 5 on the probe card 53
4 and 4 can be connected at once.

FIG. 7 is a sectional view showing a state in which the pads of the semiconductor chip and the bumps of the probe card are connected. In FIG. 7, 53 is a probe card, 54 is a bump of the probe card 53, 55 is a wiring layer of the probe card 53, 56 is a flexible substrate made of a polyimide film, 5
7 is a contact, 52 is a semiconductor chip, 58 is a pad of the semiconductor chip 52, 59 is a passivation film,
60 is a polyimide film.

The probe card 53 is a flexible substrate 5.
6 has a wiring layer 55, bumps 54, and contacts 57 connecting them. On the other hand, the semiconductor chip 52 to be inspected is provided with pads 58 for power supply, ground, and input / output signals. Further, the surface other than the pad 58 has an insulating passivation film 59 for protecting the internal integrated circuit and an insulating material for preventing the surface of the semiconductor chip 52 from being separated from the package resin when the semiconductor chip 52 is packaged. Polyimide film 6
Covered by 0s.

The probe card 53 is pressed against the semiconductor chip 52 to connect the pad 58 and the bump 54. The pads 58 and the bumps 54 are connected to all the pads 58 and all the bumps 54 at the same time. In this state, the inspection can be performed by applying the power supply voltage or the input signal to the pad 58 via the wiring layer 55.

Normally, electrical measurement is performed in this state,
When performing measurement at high temperature during wafer burn-in,
By energizing the heater of the vacuum chuck 50,
And the semiconductor wafer 51 are heated.

[0014]

However, in the method of performing the batch burn-in in a wafer state by using the above-mentioned thin film type probe card, when defective semiconductor chips exist among a plurality of semiconductor chips on a semiconductor wafer, Since the power supply voltage and the input signal are supplied also to the defective semiconductor chip, there is a problem that batch burn-in in a wafer state becomes impossible.

As a reason why the defective semiconductor chips cannot be collectively burned in the wafer state, the case where the power supply line of the semiconductor chip is defective and the case where the input signal line of the semiconductor chip is defective will be described respectively.

First, the case where the power supply line is defective will be described. Usually, the power supply wiring layer on the probe card is shared in order to reduce the amount of the wiring layer on the probe card and the number of power supplies of the tester. In such a case, if the power supply wiring line of the defective semiconductor chip and another wiring line are short-circuited, a large current will flow through the defective semiconductor chip, and the power supply voltage of the defective semiconductor chip will decrease. Since the power supply voltage of the non-defective semiconductor chip also drops, normal burn-in cannot be performed. Also, if the wiring layer for the power supply is not shared on the probe card, the amount of the wiring layer on the probe card increases significantly, which is not realistic. Further, in any case, a large amount of current flows through the defective semiconductor chip and the wiring layer connected to the defective semiconductor chip to generate heat and the temperature rises, which causes an increase in the temperature of the peripheral semiconductor chips, which is an obstacle to normal burn-in. .

Next, the case where the input signal line is defective will be described. Similar to the case of the power supply line, it is desirable to share the input signal wiring layer on the probe card in order to reduce the number of wiring layers on the probe card and the number of input signal sources of the tester. In such a case, when the wiring line for the input signal of the defective semiconductor chip and another wiring line are short-circuited, the input signal on the wiring layer for the input signal is abnormally different from the normal signal. Signal becomes abnormal, an abnormal input signal is supplied to other good semiconductor chips, and normal burn-in cannot be performed. In order to avoid this, the wiring layers for input signals and the input signal sources for each semiconductor chip should be independent, but the amount of wiring layers on the probe card and the number of input signal sources of the tester increase, and It is not realistic because the cost of the device increases significantly.

Further, a defect in the power supply wiring line or the input signal wiring line may occur not only before the burn-in but also during the burn-in. Before the burn-in, the defective semiconductor chip is removed by some method. Even if it is removed, there is also a problem that it is not possible to remove all the defective semiconductor chips generated during burn-in.

In view of the above, it is an object of the present invention to provide a method for removing the influence of defective semiconductor chips on a semiconductor wafer when performing batch burn-in in a wafer state by using a low-cost inspection apparatus.

[0020]

In order to achieve the above object, the invention of claim 1 electrically disconnects the defective semiconductor chip by disconnecting the internal wiring pattern by applying a high voltage to the electrode of the defective semiconductor chip. It is to be cut off.

Specifically, a solution means taken by the invention of claim 1 is a method of inspecting a semiconductor device, comprising a step of inspecting a plurality of semiconductor chips formed on a semiconductor wafer to determine whether they are good or bad, and a plurality of the plurality of semiconductor chips. A step of cutting an internal wiring pattern connected to the electrode of the semiconductor chip determined to be defective by applying a high voltage to the electrode of the semiconductor chip determined to be defective of the semiconductor chips; To do.

According to the second aspect of the invention, the electrode of the defective semiconductor chip is covered with an insulating film to electrically disconnect the defective semiconductor chip.

Specifically, a solution means taken by the invention of claim 2 is a method of inspecting a semiconductor device, comprising a step of inspecting a plurality of semiconductor chips formed on a semiconductor wafer to determine whether they are good or bad, and the semiconductor wafer. A step of forming an insulating film over the entire surface of the semiconductor chip, and removing the insulating film on the electrode of the semiconductor chip determined to be a good product among the plurality of semiconductor chips, while determining the defective product of the plurality of semiconductor chips And a step of leaving the insulating film on the electrodes of the formed semiconductor chip.

According to a third aspect of the present invention, in addition to the configuration of the second aspect, the insulating film is a passivation film.

According to a fourth aspect of the present invention, in addition to the configuration of the second aspect, a configuration in which the insulating film is a polyimide film is added.

According to a fifth aspect of the present invention, the power supply voltage is supplied from the row direction to stop the power supply voltage supply to the row in which the defective semiconductor chip exists, and then the power supply voltage is supplied from the column direction to remove the defective semiconductor chip. The supply of the power supply voltage to the existing column is stopped to electrically disconnect the defective semiconductor chip.

Specifically, a solution means taken by the invention of claim 5 is a method of inspecting a semiconductor device, comprising: a first and a first power supply voltage supply method for supplying each of a plurality of semiconductor chips formed in a matrix on a semiconductor wafer. Providing a second electrode,
Supplying a power supply voltage to the first electrodes of the plurality of semiconductor chips from one of the row direction and the column direction via the first switching means, and performing an inspection for determining the quality of the plurality of semiconductor chips; By operating the first switching means, the supply of the power supply voltage to the row or column of the semiconductor wafer in which a good semiconductor chip is present is continued, while the row or column of the semiconductor wafer in which a defective semiconductor chip is present. To the second electrodes of the plurality of semiconductor chips from the other in the row direction or the column direction through the second switching means to supply the power supply voltage to the semiconductor chips of the plurality of semiconductor chips. Step of performing inspection to determine pass / fail, and supply of power supply voltage to row or column in which defective semiconductor chip exists in the semiconductor wafer It is an arrangement and a step of stopping by the second switching means.

According to a sixth aspect of the present invention, the first switching means and the second switching means are formed in the plurality of semiconductor chips in addition to the configuration of the fifth aspect. .

According to a seventh aspect of the present invention, the probe card is inspected for acceptability with respect to a plurality of semiconductor chips which are formed in a matrix on a semiconductor wafer and each of which has first and second electrodes for supplying a power supply voltage. A probe card for performing a wiring, the first wiring comprising a plurality of wiring layers that extend in the row direction and are provided in parallel in the column direction, and that supply a power supply voltage to the first electrodes of the semiconductor chips in each row. And a second wiring group formed of a plurality of wiring layers that extend in the column direction and are provided in parallel in the row direction and that supply a power supply voltage to the second electrodes of the semiconductor chips in each column. It is to be configured.

[0030]

According to the structure of claim 1, the power supply wiring line, which is short-circuited with the other wiring line of the defective semiconductor chip found at the time of the probe inspection, is disconnected in the semiconductor chip, thereby making the probe card. Since it can be electrically separated from the upper wiring layer, a large amount of current flows through the defective semiconductor chip, causing a voltage drop in the common power supply wiring layer on the probe card and a rise in temperature due to heat generation. It does not affect the burn-in or inspection of other semiconductor chips.

Further, by disconnecting the input signal wiring line, which is short-circuited with other wiring lines, inside the semiconductor chip, it can be electrically separated from the wiring layer on the probe card. It is possible to prevent the input signal on the wiring layer for the input signal that is shared on the card from becoming abnormal, and it does not affect the burn-in or inspection of other semiconductor chips.

Therefore, for a good semiconductor chip at the time of probe inspection, a thin film type probe card in which a wiring layer for power supply and a wiring layer for input signal are commonly used for collective burn-in or inspection in a wafer state It can be executed normally at low cost.

According to the structure of claim 2, by covering the electrode for power supply and the electrode for input signal which are short-circuited with another wiring line of the defective semiconductor chip found at the time of probe inspection with an insulating film. Since the electrode of the defective semiconductor chip and the electrode of the probe card can be insulated and electrically separated from the wiring layer on the probe card, the defective semiconductor chip has a common power supply wiring on the probe card. The layers and the wiring layers for input signals are not electrically connected, and the common wiring layers do not affect burn-in or inspection of other semiconductor chips.

Further, since the power supply voltage is not supplied to the defective semiconductor chip, the defective semiconductor chip or the wiring layer for the power supply on the probe card does not generate heat due to current, and the burn-in of another semiconductor chip is caused by the heat generation. Or, it will not affect the inspection.

Therefore, batch burn-in or inspection of non-defective semiconductor chips in a wafer state at the time of probe inspection can be normally performed at low cost by using a probe card having a common power supply wiring layer and input signal wiring layer. It becomes possible to carry out.

According to the configuration of claim 5, the supply of the power supply voltage to one of the row or the column where the defective semiconductor chip exists is stopped by the first switching means, and the row or the column where the defective semiconductor chip exists. Since the supply of the power supply voltage to the other is stopped by the second switching means, the supply of the power supply voltage from both the row and the column is stopped for the defective semiconductor chip. Further, since the power supply voltage is continuously supplied to the row and the column in which the defective semiconductor chip does not exist, the power supply voltage is supplied to the non-defective semiconductor chip from at least one of the row and the column.

According to the structure of claim 7, the power supply voltage is supplied to the semiconductor chips in each row on the semiconductor wafer from each wiring layer forming the first wiring group, and the semiconductor chips in each column on the semiconductor wafer are supplied. A power supply voltage can be supplied from each wiring layer forming the second wiring group.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device inspection method and a probe card according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory view of a method for removing a defective semiconductor chip in the semiconductor device inspection method according to the first embodiment. In FIG. 1, 1 is a vacuum chuck, 2 is a semiconductor wafer, 2a is a semiconductor chip, 3 is a probe needle, 4 is a needle type probe card, 5 is each wiring layer of the probe card 4, 6 is a power supply, 7 is a ground, Reference numeral 8 is an input signal source, and 9 is an ammeter.

Before the burn-in of the semiconductor wafer 2, each semiconductor chip 2a on the semiconductor wafer 2 is subjected to a probe test to determine whether it is a good product or a defective product. In probe inspection, a full auto prober is usually used to inspect a plurality of semiconductor chips 2a formed on the semiconductor wafer 2 in a semiconductor wafer state. The semiconductor wafer 2 is vacuum-chucked by pulling a vacuum through a plurality of holes provided on the upper surface of the vacuum chuck 1 inside the full-auto prober.
Fixed to.

Next, a probe card 4 having a probe needle 3 made of, for example, tungsten is placed on the semiconductor wafer 2, and the probe needle is placed on each pad (not shown) of the semiconductor chip 2a on the semiconductor wafer 2. 3 and the semiconductor chip 2 via the wiring layer 5 on the probe card 4.
The power supply pad of a is connected to the ammeter 9 and the power supply 6, the ground pad of the semiconductor chip 2a is connected to the ground 7, and the input signal pad of the semiconductor chip 2a is input to the tester (not shown). By connecting to the signal source 8 and detecting the output signal, the semiconductor chips 2a are inspected one by one.

As a result of the inspection, if the semiconductor chip 2a is defective and the cause of the defect is an abnormally large current, the power supply wiring line of the semiconductor chip 2a and another wiring line are short-circuited. It is believed that At this time, for the power supply wiring line of the semiconductor chip 2a,
A high voltage, for example 100 V, is applied by using the power source 6 of the tester through the power source pad, the probe needle 3 and the power source wiring layer 5 on the probe card. Since the wiring line of the semiconductor chip 2a is composed of a fine aluminum wiring layer having a width of about 10 μm and a thickness of about 1 μm,
By applying this high voltage, a large amount of current flows in the wiring line, the wiring temperature rises rapidly, and the wiring line melts and breaks. As a result, the power supply pad of the semiconductor chip 2a is electrically disconnected from the internal circuit.

When the cause of the defect of the semiconductor chip 2a is the leak of the pad for the input signal, it is considered that the wiring line for the input signal of the semiconductor chip 2a and another wiring line are short-circuited. At this time, a high voltage is applied to the input signal pad of the semiconductor chip 2a in the same manner as above,
Separate the electrical connection between the input signal pad and the internal circuit. Then, by the alignment function of the full-auto prober, the probe needle 3 is set on the pad for the input signal of the semiconductor chip 2a to be inspected next, and the inspection is performed in the same manner as above, and the high voltage to the pad having the leak is generated. The semiconductor chip 2a connected to the pad by applying the voltage
Break the wiring line of. By repeating this procedure, for all defective semiconductor chips 2a on the semiconductor wafer 2,
Disconnect the electrical connection between the leaking pad and internal circuitry.

After electrically disconnecting the defective semiconductor chip 2a, wafer burn-in is performed on the semiconductor wafer 2. For all of the semiconductor chips 2a on the semiconductor wafer 2, a thin film type probe card having a common power supply wiring layer and input signal wiring layer is accurately arranged, and pads on the semiconductor wafer 2 and thin film type The bumps on the probe card are electrically connected, the temperature is raised, and the power supply voltage and the input signal are applied.

At this time, since the pad having the input leakage in the defective semiconductor chip 2a is separated from the internal circuit by the high voltage application during the probe inspection, the defective semiconductor chip 2a is a thin film type probe card. It is not electrically connected to the upper common wiring layer. As a result, batch burn-in in a wafer state is normally performed on non-defective semiconductor chips 2a connected to the same common wiring layer at the time of probe inspection.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a cross-sectional view showing the connection between the pad of the semiconductor chip and the bump of the probe card at the time of wafer burn-in in the semiconductor device inspection method according to the second embodiment. In FIG. 2, 10 is a thin film type probe card, 11 is a bump of the probe card 10, 12 is a wiring layer of the probe card 10, 13 is a flexible substrate made of a polyimide film, 14 is a contact, 2a is a semiconductor chip, and 15 is a semiconductor. The chip 2a is a pad, 16 is a passivation film, and 17 is a polyimide film.

In the second embodiment, the probe inspection is performed before forming the passivation film 16. The probe inspection determines whether each semiconductor chip 2a on the semiconductor wafer is a good product or a defective product. Then, after forming the passivation film 16, the passivation film 16 on the pad 15 is formed.
The process of forming an opening is performed. A mask having a pattern for forming openings is prepared in advance. Next, a photoresist is applied to the surface of the semiconductor wafer, and the pattern of the opening on the mask is exposed and transferred onto the photoresist on the semiconductor chip 2a using a stepper every several chips. At this time, the mask is shielded from the defective semiconductor chip 2a found during the probe inspection so that the pattern of the opening on the mask is not transferred to the photoresist on the semiconductor chip 2a.

Then, when the photoresist is developed and the passivation film 16 is etched, an opening is formed in the passivation film 16 on the pad 15 for the good semiconductor chip 2a, but the defective semiconductor chip 2a is formed.
However, no opening is formed in the passivation film 16 on the pad 15, and the pad 15 is covered with the insulating passivation film 16. After that, the polyimide film 17 is formed over the entire surface of the semiconductor wafer. Then, openings are formed in the polyimide film 17 on the pads 15 of all semiconductor chips, not limited to non-defective products.

Thereafter, wafer burn-in is performed on this semiconductor wafer. Semiconductor chip 2 on a semiconductor wafer
For all of a, the probe card 10 having the common power supply wiring layer and input signal wiring layer is accurately arranged, and the pad 15 and the probe card 10 on the semiconductor wafer are arranged.
The bumps 11 are electrically connected to each other, and the temperature is raised to apply a power supply voltage and an input signal.

In the defective semiconductor chip 2a, the pad 15 in which the input leakage has occurred is covered by the insulating passivation film 16 covering the pad 15 so that the probe card 10 can be protected.
Since it is electrically insulated from the upper bump 11, the defective semiconductor chip 2 a is not electrically connected to the common wiring layer on the probe card 10. Therefore, the batch burn-in is normally executed in the wafer state for the good semiconductor chips 2a connected to the same common wiring layer.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a sectional view showing the connection between the pads of the semiconductor chip and the bumps of the probe card at the time of wafer burn-in in the semiconductor device inspection method according to the third embodiment. 3, the same members as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

In the third embodiment, first, the passivation film 16 is formed over the entire surface of the semiconductor wafer. Then, after forming openings in the passivation film 16 on the pads 15 of all the semiconductor chips, a probe test is performed before forming the polyimide film 17. The probe inspection determines whether each semiconductor chip 2a on the semiconductor wafer is a good product or a defective product. After that, polyimide film 1
After forming 7, the step of forming an opening in the polyimide film 17 on the pad 15 is performed. A mask having a pattern of openings is prepared in advance. Next, a photosensitive polyimide film 17 is applied on the surface of the semiconductor wafer, and the pattern of the opening on the mask is exposed and transferred onto the polyimide film 17 on the semiconductor chip 2a using a stepper every several chips. At this time, the defective semiconductor chip 2 found during the probe inspection
For a, the mask is shielded from light so that the pattern of the opening on the mask is not transferred to the polyimide film 17 on the semiconductor chip 2a.

After that, when the polyimide film 17 is developed,
An opening is formed in the polyimide film 17 on the pad 15 for the non-defective semiconductor chip 2a, but no opening is formed in the polyimide film 17 on the pad 15 for the defective semiconductor chip 2a. 15 is covered with an insulating polyimide film 17.

Thereafter, wafer burn-in is performed on the semiconductor wafer. For all the semiconductor chips 2a on the semiconductor wafer, the probe card 10 having the common power supply wiring layer and input signal wiring layer is accurately arranged,
The pads 15 on the semiconductor wafer and the bumps 11 on the probe card 10 are electrically connected, and the temperature is raised to apply a power supply voltage or an input signal.

In addition, the pad 15 of the defective semiconductor chip 2a, which had an input leak, is electrically insulated from the bump 11 of the probe card 10 by the insulating polyimide film 17 covering the pad 15. The defective semiconductor chip 2a is not electrically connected to the common wiring layer on the probe card 10. Therefore, the batch burn-in in the wafer state is normally executed for the good semiconductor chips 2a connected to the same common wiring layer.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an explanatory diagram of a method for removing a defective semiconductor chip during wafer burn-in in the semiconductor device inspection method according to the fourth embodiment. In FIG. 4, 2 is a semiconductor wafer, 2a is a semiconductor chip formed in a matrix on the semiconductor wafer 2, 18 is a bump on a probe card (not shown), and 19 is a wiring layer for input signals on the probe card. Is.

Here, two pads for power supply are provided on the semiconductor chip 2a, and when a power supply voltage is supplied to one or both of the two pads for power supply, the semiconductor chip 2a is normally operated. On the other hand, when power is not supplied to both of the two power supply pads, the input signal pads of the semiconductor chip 2a and other pads are not electrically connected to the internal circuit of the semiconductor chip 2a. Designed to be separated.

Further, 20a, 20b, 20c, 20d and 20e are wiring layers on the probe card connected to the power source in the row direction as the first wiring group, which are independent of each other and of the semiconductor chips 2a of each row. The first power supply pad is connected in parallel. 21a, 21b, 21c, 21d and 21e are wiring layers on the probe card connected to the power source in the column direction as the second wiring group, which are independent of each other, and are the second power source of the semiconductor chips 2a in each column. Connected in parallel to the pad for. 22a, 22b, 22c, 22d and 22e are wiring layers for transmitting a signal for turning on / off the row direction power supply switching means (first switching means) as the third wiring group, 23a, 23b, 23c,
Reference numerals 23d and 23e are wiring layers for transmitting a signal for turning on / off the column-direction power supply switching means (second switching means) as the fourth wiring group. Also, VDD
Is a power supply voltage, and Sig is a switching signal.

Next, FIG. 5 is a circuit diagram showing an example of the switching means provided in the semiconductor chip 2a. In FIG. 5, 20 is the first wiring group 20a, 20b, 20c, 2
One wiring layer of 0d and 20e, 21 is one wiring layer of the second wiring groups 21a, 21b, 21c, 21d and 21e, and 22 is a third wiring group 22a, 22b, 22
One of the wiring layers c, 22d and 22e, and 23 is the fourth
Of one of the wiring groups 23a, 23b, 23c, 23d and 23e, 24 is a first P-channel MOS transistor as a first switching means, and 25 is a second P-channel MOS transistor as a second switching means. P-channel MO
The S transistor, 26 is a wiring line for power supply of the internal circuit of the semiconductor chip 2a.

In the above-described structure, the semiconductor chip A will be described by taking as an example the case where a short circuit between the power supply and the ground occurs in the semiconductor chip A shown in FIG. 4 during the wafer burn-in.
Exclude from the burn-in.

First, burn-in of all the semiconductor chips 2a on the semiconductor wafer 2 is performed in a wafer state. Power is supplied from the first wiring group 20a, 20b, 20c, 20d and 20e. At this time, the third wiring groups 22a, 22
Signals for turning on the first P-channel type MOS transistors connected to them are transmitted from b, 22c, 22d and 22e. In addition, the second wiring groups 21a, 21
Power supply from b, 21c, 21d, and 21e is stopped, and the fourth wiring groups 23a, 23b, 23c, and 23 are stopped.
A signal for turning off the second P-channel type MOS transistor connected thereto is transmitted from d and 23e. Further, an input signal for operating the semiconductor chip 2a is input to the semiconductor chip 2a from the input signal wiring layer 19.

In this state, for example, if the power supply line and the ground line are short-circuited in the semiconductor chip A, and a fault in which an overcurrent flows occurs, power is immediately supplied from the wiring layer 20b of the first wiring group. When stopped, the third wiring groups 22a, 22b, 22c, 22d and 2 are temporarily stopped.
A signal for turning off the first P-channel type MOS transistor is transmitted from 2e.

Referring to FIG. 5, first, power is supplied from one wiring layer 20 of the first wiring group, and power supply is stopped from one wiring layer 21 of the second wiring group. I'll do it. In addition, one wiring layer 2 of the third wiring group
2 is a "Low" level, the first P-channel MOS transistor 24 is turned on, and one wiring layer 23 of the fourth wiring group
Turns off the second P-channel MOS transistor 25 at "High" level. When the above-mentioned defect occurs in the semiconductor chip A, one wiring layer 20 of the first wiring group
Power supply from the second wiring group is stopped, and one wiring layer 21 of the second wiring group is set to the "High" level to turn off the first P-channel MOS transistor 24.

For these operations, a current sensor is provided externally for each row-direction power supply, and when a power supply in which a current exceeding the proper current range flows is generated, the function of stopping the power supply and the first P-channel MOS transistor 2
A function of generating a signal for turning off 4 may be added.

After that, the second wiring groups 21a, 21b, 2
A signal for starting the power supply from 1c, 21d and 21e and turning on the second P-channel MOS transistor 25 connected to them from the fourth wiring group 23a, 23b, 23c, 23d and 23e. To convey.
Since an overcurrent flows through the wiring layer 21c of the second wiring group this time, immediately when the overcurrent is detected, the power supply from the wiring layer 21c of the second wiring group is stopped and the fourth A signal for turning off the second P-channel type MOS transistor 25 is transmitted from the wiring layer 23c of the wiring group of. After that, a signal for turning on the first P-channel MOS transistor 24 of the third wiring group 22a, 22c, 22d, and 22e other than the row in which the overcurrent flows is transmitted, and the power supply to those rows is performed. Start.

The other semiconductor chips 2a in the same row as the semiconductor chip A have second wiring groups 21a, 21b, 21d and 21.
The power is supplied from e, and the other semiconductor chips 2a in the same column as the semiconductor chip A are connected to the first wiring groups 20a, 20
Power is supplied from c, 20d, and 20e. The wiring layer 20b of the first wiring group and the power supply wiring line inside the semiconductor chip 2a connected to the wiring layer 20b and the second wiring layer 20b
The wiring layer 21c of the wiring group and the wiring line for the power supply inside each semiconductor chip 2a connected to the wiring layer 21c are cut off by switching off the switching means.

Normally, when an overcurrent defect occurs in the semiconductor chip 2a on the semiconductor wafer 2 during burn-in, the defective semiconductor chip A generates heat due to the current to raise the temperature of other good semiconductor chips 2a. However, there is a problem that the burn-in temperature is changed and a problem that the correct power supply voltage cannot be applied to the other good semiconductor chip 2a due to the overcurrent.
Another non-defective semiconductor chip 2 via the wiring layer 20b of the first wiring group and the wiring layer 21c of the second wiring group
The current does not flow from the defective semiconductor chip A to the defective semiconductor chip A, and these problems can be solved, and the power supply to only the semiconductor chip A can be stopped and the semiconductor chip A can be removed from the burn-in.

In the fourth embodiment, the semiconductor chip A has been described as having a defect. However, even if another semiconductor chip 2a on the semiconductor wafer 2 has a defect, the semiconductor chip A can be similarly removed during burn-in.

Although the defective semiconductor chip A generated during burn-in is removed in the fourth embodiment, it can also be used to remove the defective semiconductor chip 2a before burn-in.

Further, although the switching means is provided in the semiconductor chip 2a in the fourth embodiment, it may be provided in the probe card.

Further, in the fourth embodiment, a short circuit defect between the power supply line and the ground line of the semiconductor chip A is taken as an example, but other defects can be removed from the burn-in. It detects an output signal from each semiconductor chip 2a, and as a result, supplies a signal for turning off the switching means to the semiconductor chip 2a in which the defect is found, while stopping the power supply from the row direction and the column direction. .

[0072]

According to the method of inspecting a semiconductor device of the first aspect, a defective semiconductor chip is electrically disconnected from another semiconductor chip by disconnecting the internal wiring pattern when a high voltage is applied to its electrode. Since the semiconductor chips are separated from each other, the good semiconductor chips are not affected, and the burn-in can be collectively performed in the wafer state.

According to the semiconductor device inspection method of the second aspect, since the electrode of the defective semiconductor chip is covered with the insulating film, the defective semiconductor chip is electrically separated from the other semiconductor chips. No influence is exerted, and burn-in can be performed collectively in a wafer state.

According to the semiconductor device inspection method of the third aspect, since the insulating film is the passivation film used for protecting the internal integrated circuit, it is not necessary to form the insulating film again.

According to the semiconductor device inspection method of the fourth aspect, since the insulating film is a polyimide film used to prevent the surface of the semiconductor chip and the package resin from being separated from each other, it is necessary to form the insulating film again. Absent.

According to the semiconductor device inspection method of the fifth aspect, the supply of power supply voltage from both the row and column directions to the defective semiconductor chip is stopped, while the supply to the non-defective semiconductor chip is stopped. Since the power supply voltage is supplied from at least one of the row and the column, the burn-in can be simultaneously performed on all good semiconductor chips on the semiconductor wafer in a wafer state at the same time.

According to the semiconductor device inspection method of the sixth aspect, since the first and second switching means are formed in the semiconductor chip, each semiconductor chip in a row or column in which a defective semiconductor chip exists. It is possible to stop the supply of the power supply voltage to each semiconductor chip in the row or column in which the defective semiconductor chip is present by operating the first and second switching means.

According to the probe card of claim 7,
A power supply voltage can be supplied to each semiconductor chip in each row on the semiconductor wafer from each wiring layer that constitutes the first wiring group, and
Since the power supply voltage can be supplied to the semiconductor chips in each column from each wiring layer forming the second wiring group, the power supply voltage is supplied from both the row and column directions to the defective semiconductor chips on the semiconductor wafer. On the other hand, the supply of the power supply voltage from at least one of the row and the column can be continued for the non-defective semiconductor chip.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a method for removing a defective semiconductor chip in a semiconductor device inspection method according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a connection between a pad of a semiconductor chip and a bump of a probe card at the time of burn-in in a semiconductor device inspection method according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a connection between a pad of a semiconductor chip and a bump of a probe card at the time of burn-in in a semiconductor device inspection method according to a third embodiment of the present invention.

FIG. 4 is an explanatory diagram of a method for removing a defective semiconductor chip during burn-in in a semiconductor device inspection method according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of switching means in a semiconductor device inspection method according to a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a connection state between a conventional semiconductor wafer and a thin film type probe card.

FIG. 7 is a cross-sectional view showing a connection between a pad of a conventional semiconductor chip and a bump of a thin film type probe card.

[Explanation of symbols]

1, 50 Vacuum chuck 2, 51 Semiconductor wafer 2a, 52 Semiconductor chip 3 Probe needle 4 Needle type probe card 5, 12, 55 Wiring layer 6 Power supply 7 Ground 8 Input signal source 9 Ammeter 10, 53 Thin film type probe card 11, 18, 54 Bumps 13, 56 Flexible substrate 14, 57 Contacts 15, 58 Pads 16, 59 Passivation film 17, 60 Polyimide film 19 Input signal wiring layers 20a, 20b, 20c, 20d, 20e First wiring group 20th One wiring layer of one wiring group 21a, 21b, 21c, 21d, 21e Second wiring group 21 One wiring layer of the second wiring group 22a, 22b, 22c, 22d, 22e Third wiring layer Wiring group 22 One wiring layer of the third wiring group 23a, 23b, 23c, 23d, 23e 4 wiring group 23 one wiring layer of the 4th wiring group 24 first P-channel type MOS transistor 25 second P-channel type MOS transistor 26 wiring line for power supply VDD power supply voltage Sig switching signal A defective Semiconductor chip

Claims (7)

[Claims] 1. A step of performing an inspection for determining the quality of a plurality of semiconductor chips formed on a semiconductor wafer, and applying a high voltage to an electrode of a semiconductor chip of the plurality of semiconductor chips determined to be defective. And a step of cutting the internal wiring pattern connected to the electrode of the semiconductor chip determined to be defective by the method of inspecting the semiconductor device. 2. A step of performing an inspection for judging the quality of a plurality of semiconductor chips formed on a semiconductor wafer, a step of forming an insulating film over the entire surface of the semiconductor wafer, and a step of forming a plurality of semiconductor chips among the plurality of semiconductor chips. Removing the insulating film on the electrode of the semiconductor chip determined to be non-defective, while leaving the insulating film on the electrode of the semiconductor chip determined to be defective among the plurality of semiconductor chips. A method for inspecting a semiconductor device, comprising: 3. The method for inspecting a semiconductor device according to claim 2, wherein the insulating film is a passivation film. 4. The method for inspecting a semiconductor device according to claim 2, wherein the insulating film is a polyimide film. 5. A step of providing first and second electrodes for supplying a power supply voltage to each of a plurality of semiconductor chips formed in a matrix on a semiconductor wafer, and the first electrodes of the plurality of semiconductor chips being provided. A step of supplying a power supply voltage from one of the row direction or the column direction through the first switching means to perform an inspection for judging the quality of the plurality of semiconductor chips; and operating the first switching means, Continuing to supply a power supply voltage to a row or a column in which a good semiconductor chip exists in the semiconductor wafer, while stopping the supply of a power supply voltage to a row or a column in which a defective semiconductor chip exists in the semiconductor wafer, A power supply voltage is supplied to the second electrodes of the plurality of semiconductor chips from the other in the row direction or the column direction via the second switching means. The method further includes a step of performing an inspection for determining the quality of the plurality of semiconductor chips, and a step of stopping the supply of the power supply voltage to the row or the column in the semiconductor wafer where the defective semiconductor chip exists by the second switching means. A method for inspecting a semiconductor device, comprising: 6. The method of inspecting a semiconductor device according to claim 5, wherein the first switching means and the second switching means are formed in the plurality of semiconductor chips. 7. A probe card for inspecting the quality of a plurality of semiconductor chips, which are formed in a matrix on a semiconductor wafer and each have first and second electrodes for supplying a power supply voltage. A first wiring group extending in the row direction and provided in parallel in the column direction, the first wiring group including a plurality of wiring layers for supplying a power supply voltage to the first electrodes of the semiconductor chips in each row; And a second wiring group formed of a plurality of wiring layers for supplying a power supply voltage to the second electrodes of the semiconductor chips in each column, the probe card being provided in parallel with each other.