JPS6187349A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To enable a burn-in to a large number of semiconductor elements under a wafer state by fitting a switch element controlling the feed operation of a power-supply electrode section and a grounding electrode section into a feed path to at least one of the power-supply electrode section and the grounding electrode section formed onto the semiconductor element. CONSTITUTION:Power supply potential is fed from an external power supply by a probe pin to an electrode section 203 on a wafer and ground potential to an electrode section 202, and potential is distributed to all chips through wirings 107, 105 in a cutting-margin section 11. Supply potential is fed to power- supply electrodes 103 through the wirings 106 from the wiring 105 on a chip 10, and connected to switching circuits 110 through wirings 109 from the wiring 107, and potential corresponding to the ground potential of the wiring 107 is fed to grounding electrodes 104 through wirings 108 when the switching circuits 110 are turned ON. The switching circuits 110 are brought to a conductive state only when high potential and low potential are each fed to the electrode sections 202, 203 for a burn-in under a wafer state, and switches brought to a non-conductive state in cases other than that are manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer for facilitating screening tests of semiconductor devices.

[Conventional technology]

Conventionally, screening tests such as burn-in of semiconductor devices (hereinafter referred to as burn-in) have been performed by setting up probe pins and supplying power to each of a large number of semiconductor devices formed on the same wafer, or by scribing each semiconductor device. After that, packaging is performed, and then testing is performed by supplying power from the REET' pin.

[Problem that the invention seeks to solve]

However, the former method of testing by setting up probe pins for each semiconductor element is complicated and requires a large number of testing man-hours. Another disadvantage is that if a large number of probe pins are used to automatically test at the same time, the test equipment becomes complicated. Furthermore, if a screening test is performed on each individual element after packaging, there is a drawback that removal of defective products becomes slow.

In view of the above points, an object of the present invention is to provide a semiconductor wafer that enables burn-in of a large number of semiconductor devices in wafer state.

In particular, it is an object of the present invention to provide a semiconductor wafer in which a switch element is provided in a power supply path for burn-in to limit the power supply operation, thereby reliably preventing erroneous power supply at times other than burn-in. .

[Failure to solve the problem]

The present invention provides a semiconductor wafer in which a large number of semiconductor elements are formed on the same semiconductor substrate, which has a power supply electrode part and a ground electrode part formed on the semiconductor element, and a power supply path for at least one of the two electrode parts. A switch element for controlling the power supply operation is provided at the electrode section, and the operating state of the switch element is changed depending on the potential state of the power supplied to the electrode section.

Furthermore, the present invention is characterized in that a wiring pattern consisting of a power supply line and a ground line for feeding power to the power supply electrode part and the ground electrode part is provided in the margin part of the wafer.

〔Example〕

An embodiment of the present invention will be described below.

The structure of an LSI chip for realizing the present invention is shown in FIG. 1, and the structure on a wafer on which this chip is formed is shown in FIG. 101 is an LSI chip which is a semiconductor element, 102 is an electrode on the chip (commonly called a bat), and 103 is an electrode 10.
A power supply electrode for supplying a power supply potential to the chip as a part of 2,
Reference numeral 105 indicates a wiring area formed in the cutting margin 111 (commonly called scribe area) of the chip and is used to supply power potential to the power supply electrode 103 during burn-in, and 106 indicates the electrode 1.
03 and the wiring area 105, both the wiring areas 105 and 106 are formed by the same means as the wiring inside the chip. Reference numeral 107 denotes a wiring area formed in the cutting margin 111 of the chip and used to supply ground potential to the chip during burn-in; 104 denotes a ground electrode which is a part of the electrode 102 and is used to supply ground potential to the chip; 110
108 is a switch circuit that controls whether or not to supply the potential of the wiring 107 to the ground electrode 104;
109 is a wiring area that connects the wiring 107 and the switch circuit 110,
107, 108, and 109 are all formed by the same means used to form wiring inside the chip.

FIG. 2 shows the configuration when a chip having the above-described configuration is formed on a wafer, where 201 is a semiconductor wafer, 101 is an LSI chip with the above configuration, and 202 is a power supply for supplying ground potential to the wafer from an external power source. 205 is the power supply section 202
This wiring connects the wiring 107 on the chip to the wiring 107 on the chip, and is formed in the margin 111 of the chip. Reference numeral 203 denotes a power supply unit for supplying a power supply potential from an external power supply to the wafer, and 204 indicates a wiring that connects the power supply unit 203 and the wiring 105 on the chip, which is formed in the cutting margin 111 of the chip. The above power supply unit 20
2 and 203, and wirings 204 and 205 are all formed by the same means as that used to form wiring inside the chip.

Next, a method for performing burn-in in a wafer state will be explained based on the operation of each component. In order to perform burn-in on a wafer, it is essential to supply power to each chip on the wafer, and to achieve this, probe bins are set up against the electrodes of the chips (102, 103°, 104, etc.). But it's possible.

However, there are problems such as the operation is cumbersome and the equipment for this purpose is complicated to do this for all chips.

The configuration of the present invention is intended to easily supply power to all chips by wiring (105, 107, etc.) formed in the cutout portion 111 of the chip, that is, the power supply potential is applied to the electrode portion 203 on the wafer. , a ground potential is supplied to the electric flask part 202 from an external power supply through a probe bottle, and the cutting margin part 1
This is intended to be distributed to the metal knobs through the wires 107 and 105 of No. 11. That is, on the chip, a power supply potential is supplied from a wiring 105 to a power supply electrode 103 via a wiring 106, and is connected to a switch circuit 110 from a wiring 107 to a wiring 109.

When the child circuit 110 is ON, a potential corresponding to the ground potential of the wiring 107 is supplied to the ground electrode 104 via the wiring 108 . According to this, it is possible to use two probe pins per wafer for power supply, and it goes without saying that this is easy.

Next, the functions of the switch/circuit 110 among the above operations will be supplementarily explained. The switch circuit 110 includes wiring lines 105 and 1 configured to enable burn-in on the wafer.
07 etc. only during burn-in), i.e., during wafer testing to determine whether the chip 101 is good or not, and during product testing in the packaged state after assembly.
■This was added to ensure that it does not affect the original circuit function of the 1000-knob in the fully loaded operating state after the product is shipped.

Therefore, in order to perform burn-in in the wafer state,
The switch circuit 110 has a feature that it becomes conductive only when high potential and low potential are supplied to the electric crosspieces 202 and 203, respectively, and becomes non-conductive in other cases, that is, in the cases ① to ① above. It is a switch that has been installed. Such a switch is easily manufactured using conventional techniques and can be manufactured by the same means as the other circuit components that make up the chip.

Therefore, the operation of the present invention will be explained in more detail. Second
In the figure, a ground potential is supplied to each chip 101 formed on a silicon wafer 201 through a power supply electrode 202 and wiring sections 205 and 107 connected thereto, and a power supply electrode 203 and a wiring section 204 connected thereto, A power supply potential is supplied through 105. The power supply electrodes 202 and 203 receive two reference potentials, power and ground, from an external power source through a probe bottle or the like, and distribute them to all chips on the wafer through the wiring section.

Further, the chip receives a potential difference corresponding to the potential difference between the two reference potentials through its power supply electrode 103 and ground electrode 104, and becomes energized. Power supply electrode 202.2 used in this configuration
The wiring part of 03, 105, 107° 204.205 is
Since it is formed by the same means used to form wiring and electrodes within the chip, there is no need to add or change the manufacturing process. In addition, these wires conventionally have a wiring width that can be formed in the area used as the margin 111 of the wafer,
Therefore, it does not affect the chip size and does not limit the number of chips on the wafer.

The method for supplying power to all chips on a wafer has been explained above.
The operation on the SI chip will be explained with reference to FIGS. 1 and 3. Wires 105 and 107 in Figure 1 are 106 and 10
9 wirings respectively connect the power supply electrode 103 and the switch circuit 1.
Connect to 10. The power supply electrode 103 is the power supply electrode 20 in FIG.
The power supply potential from the external power supply supplied to 3 is directly supplied. On the other hand, the ground potential supplied to the power supply electrode 202 in FIG. 2 is supplied to the ground electrode 104 via the switch circuit 110.

The configuration and operation of the switch circuit 110 will be explained below. FIG. 3 shows an example of the configuration of the switch circuit 110. Terminal 301 is connected to wiring 109 in FIG. 1, and terminal 302 is connected to wiring 108 in FIG. A P-type MOS transistor 303 has a source connected to the terminal 302, a drain connected to a current limiting fuse 304, and a gate connected to the drain via a protective resistor 305. The fuse 304 is made of the same conductive material as the wiring 109, /l or An! The wiring width is made narrower so that the current path is narrower than the wiring 109 as shown in FIG. 5(A'), or the wiring thickness is made thinner as shown in FIG. 5(B). When an excessive current flows through the transistor 303, the current density of the fuse portion 304 increases, and cutting occurs due to electromigration or fusing occurs due to heat generation, thereby interrupting the excessive current.

FIG. 4 shows the switch 110 and the power supply electrode 10 of the LSI.
This is an equivalent circuit when the current path from 3 to the ground electrode 104 is replaced with a resistor for simplicity, and 402 corresponds to the power supply electrode 103 in FIG. The resistor 401 is a resistor that isometrically replaces the current path from the power supply electrode 103 to the ground electrode 104 of the chip 101. At this time, when the high voltage VH is supplied to the terminal 402 and the low voltage V is applied to the terminal 301, the voltage V M at the terminal 302 becomes MM=VL+V<VH.
occurs.

It is assumed that the impedance of the switch section in FIG. 4 is sufficiently smaller than the impedance of the equivalent resistance 40,
Further, VTP' is the sum of the threshold voltage VTP of the MOS transistor 303 and the variation ΔVTP due to the substrate effect.
It is a voltage expressed as TR'=VTR+ΔVTP. The VM is the voltage generated at the ground electrode 104, and therefore LS
There is a VH between the power supply electrode 103 and the ground electrode 104 of the I chip.
A potential difference VFl is applied, and this potential difference enables the operation of the LSI. Conversely, this vH-vM is L
By applying the potentials of VH and 2 so as to be equal to the power supply potential difference when burning in the SI, a predetermined potential difference can be supplied to the LSI chip.

Next, a case where the switch circuit 110 is not conductive will be described.

During testing to determine the quality of LSI chips,
After assembling the chip and sealing the package, it is LS.
The two reference potentials of the power supply and ground applied to operate I are the power supply electrode 103 and the ground electrode 1 shown in FIG. 1, respectively.
04 directly. That is, in FIG. 4, the power supply potential is supplied to the terminal 402 and the ground potential is supplied to the terminal 302. At this time, in order to make the MOS transistor 303 conductive, a negative potential (?) lower than the ground potential is applied to the terminal 301.
-V T P '(V)) must be applied.

However, since the LSI (in the case of CMO3) operates at a positive potential with respect to the ground potential, in the unlikely event that a failure occurs, the wiring 10
Even if 7 is shorted to a component inside the chip (for example, the VCC potential in the case of a 0MO5 substrate or an N-type substrate), the above-mentioned potential -VTP' (Vl) is not supplied, and therefore the switch MOS transistor 303 is conductive. Therefore, there is no influence on the ground electrode 104 to which the ground potential is supplied, and the operation of the internal circuits of the chip is guaranteed.

In the above explanation, AC potential fluctuations due to capacitive coupling etc. to the wiring 107 are ignored, but a configuration for reducing the AC influence is possible at the time of design, and there is no problem in practice.

The above is an explanation of the operation of the switch circuit 110, but the effect of adding the switch circuit 110 compared to the case of not adding it is: This is demonstrated during tests in the product state after the chip is sealed in a package and during operation in the mounted state. Specifically, in the case of In this case, the current consumption of the chip cannot be measured, so detection of pass/fail is a post-process. In the case of ■, wiring 10 as described above.
This has the effect that even if 7 is short-circuited to a component inside the chip such as a substrate for some reason, this will not cause a defect or malfunction.

Incidentally, in the above embodiment, for each chip 101 on the wafer, 7
Although this configuration performs study burn-in by supplying only the power supply type and ground potential, it is possible to perform clocked burn-in by adding multiple layers of wiring to the cutting margin and configuring it so that clock signals can also be applied.
rn in ) is also possible.

Further, in the embodiment described above, the switch circuit 101 is configured on the ground potential power supply side, but it may be configured on the power supply potential power supply side.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to burn-in each semiconductor element in the wafer state, and it is possible to perform testing very efficiently and to sufficiently increase the yield in subsequent processes. Moreover, since a switch element is provided in the power supply path for performing burn-in to limit the power supply operation, it is possible to reliably prevent power from being erroneously supplied at times other than burn-in.

[Brief explanation of the drawing]

Fig. 1 is an enlarged partial plan view of a semiconductor chip portion according to an embodiment of the present invention, Fig. 2 is a semiconductor wafer used in the same embodiment, and Figs. 3 and 4 are equivalent circuit diagrams of a switch circuit portion. , FIG. 5(Δ), and FIG. 5(B) are a plan view and a sectional view showing an example of the structure of the fuse portion. 101...LSI chip, 103...power supply type) A1
．． 104... Ground electrode, 105, 106, 107, 1
08.109... Wiring area, 110... Switch circuit, 111... Relief portion, 201... Semiconductor wafer, 202.203... Power supply portion, 303... MOS transistor, 304...・Current limiting fuse.

Claims (2)

[Claims] (1) In a semiconductor wafer in which a large number of semiconductor elements are formed on the same semiconductor substrate, the semiconductor wafer has a power supply electrode part and a ground electrode part formed on the semiconductor element, and a power supply path for at least one of both electrode parts is provided. A semiconductor wafer, comprising: a switch element for controlling the power supply operation; and an operating state of the switch element is changed depending on a potential state of the electric power supplied to the electrode section. (2) A semiconductor wafer according to claim 1, characterized in that a wiring pattern consisting of a power supply line and a ground line for supplying power to the power supply electrode section and the ground electrode section is provided in the margin section of the wafer. .