JPH09199672A - Semiconductor integrated circuit device and method of inspection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove defective chips on a semiconductor wafer in a lump burning-in of the semiconductors at wafer state by connecting a first and a second electrodes and wiring to each branch line of conductor lines that comprise three branch lines and the branch lines connected to the wiring comprise fuses. SOLUTION: A first and a second electrodes 2 and 3 of pad electrodes and wiring 4 that is connected to an internal circuit are provided on an integrated circuit chip 1. The first and the second electrodes 2 and 3 and the wiring 4 are connected to each branch line of a conductor line 5 that comprises three branch lines that are extended branching in three directions. The branch line connected to the wiring 4 comprises a fuse 9 made of Al and a part of Al wiring 8 that is connected serially. The fuses are blown for the defective chips by supplying power of more than the maximum allowable power to the first and the second electrodes 2 and 3 and the power supply to the inside circuit is stopped. With this, the effect from the defective chips at the lump burning-in of the semiconductor chips in the wafer state can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of inspecting a plurality of semiconductor wafers simultaneously, that is, in a wafer state, and an inspection method thereof.

[0002]

2. Description of the Related Art In recent years, there has been remarkable progress in miniaturization and price reduction of electronic devices equipped with semiconductor integrated circuit devices, and there is a strong demand for semiconductor integrated circuit devices to be reduced in size and cost. Usually, a semiconductor integrated circuit device is electrically connected to a lead frame by a wire bonding method and mounted on a circuit board in a form sealed with resin or ceramics. A state in which the device is cut out from a semiconductor wafer (hereinafter, "bare chip"
Therefore, a method of mounting directly on a circuit board has been developed, and it is desired to provide a bare chip with a guaranteed quality at a low price.

[0003] However, the burn-in using the bare chip is very complicated to handle and cannot meet the demand for cost reduction. In addition, it is very difficult to perform burn-in screening by dividing a large number of semiconductor integrated circuit devices (hereinafter, sometimes referred to as “integrated circuit chips” in some cases) simultaneously formed on the same substrate one by one or several. It takes time and is not realistic in terms of time and cost.

Therefore, it is important to perform burn-in screening on all integrated circuit chips simultaneously in a wafer state. In order to perform batch burn-in in a wafer state, it is necessary to apply a power supply voltage or an input signal to a plurality of integrated circuit chips formed on the same semiconductor wafer at the same time to operate. For this purpose, it is necessary to prepare a probe card having a very large number (usually several thousand or more) of probe terminals, and the conventional needle type probe card cannot cope with the number of pins and the cost. Therefore, it is conceivable to adopt a thin-film probe card in which bump electrodes are provided on a flexible substrate (Nitto Technical Report Vo)
l. 28, No. 2 Oct. 1990pp. 57-6
2).

Burn-in screening by a thin film probe card using a flexible substrate with bumps will be described below with reference to FIGS. 4 (a) and 4 (b).

4A and 4B show a state in which the thin film type probe card a is connected to the integrated circuit chip c on the semiconductor wafer b. The semiconductor wafer b is placed on the upper surface of the vacuum chuck d during burn-in, and is fixed so as not to move by being evacuated from a plurality of pores (not shown) formed on the upper surface of the vacuum chuck d. I have. The vacuum chuck d is equipped with a heater and a temperature sensing device (both are not shown) so that the temperature of the semiconductor wafer b mounted on the upper surface of the vacuum chuck d can be controlled.

The thin film type probe card a is provided with a polyimide substrate e as a flexible substrate, and a wiring f is formed on the polyimide substrate e, and the wiring f is a bump electrode i inserted in the through hole h. It is connected to the.

On the other hand, on each integrated circuit chip c of the semiconductor wafer b, a pad electrode j serving as a power source, a ground and an input / output terminal of the integrated circuit is formed, and at the time of burn-in, the bump electrode i of the thin film type probe card a. Is a semiconductor wafer b
It corresponds to the pad electrodes j of all the integrated circuit chips c above, whereby all the pad electrodes j of the plurality of integrated circuit chips c and all the bump electrodes i of the thin film type probe card a are connected. I try to connect at once.

The surface of each of the integrated circuit chips c other than the pad electrode j is covered with a passivation film k that is electrically insulating to protect the integrated circuit, and the integrated circuit chip c is covered with the passivation film k. The surface of the package is covered with an electrically insulating polyimide film m to prevent the package resin from peeling off when the package is formed.

The point of performing the burn-in screening using the thin film type probe card a is to press the thin film type probe card a against the semiconductor wafer b fixed to the vacuum chuck d, and all the pads of the plurality of integrated circuit chips c. The electrode j and all the bump electrodes i of the thin film type probe card a are connected at once. In this state, a power supply voltage and an input signal are applied via the wiring f of the thin-film probe card a, and an electrical measurement is performed in this state for inspection. When performing measurement at high temperature during burn-in, use the vacuum chuck d
This heater is energized to heat the vacuum chuck d and the semiconductor wafer b fixed on the upper surface thereof.

[0011]

However, when performing the batch burn-in in the wafer state using the thin film type probe card as described above, if there is a defective chip, the batch burn-in in the wafer state may not be possible. . The causes include a power supply voltage and an input signal, which will be described below.

First, the power supply voltage will be described. Usually, in order to reduce the amount of wiring on the thin film type probe card and to reduce the number of power sources of the tester, the wiring is commonly used on the thin film type probe card. At this time, if a short circuit occurs between the power supply wiring in the defective chip and another wiring, a large current flows through the defective chip, and not only the voltage of the power supply terminal of the defective chip drops, but also the power supply terminal of another good chip. , The normal burn-in or inspection becomes impossible.

On the other hand, if the power supply wiring is not shared on the thin film type probe card, the amount of wiring on the thin film type probe card increases greatly, which is not realistic. In either case, a large amount of current flows through the defective chip and the wiring connected to the defective chip to generate heat and the temperature rises. This raises the temperature of the peripheral non-defective chips, which hinders normal burn-in or inspection.

Next, the input signal will be described. In order to reduce the wiring amount on the thin film type probe card and to reduce the number of input signal sources of the tester in the same manner as in the case of the power supply wiring, on the thin film type probe card. It is desirable to use common wiring. At this time, if a short circuit occurs between the input signal wiring in the defective chip and another wiring, an input signal on the input signal wiring becomes an abnormal signal completely different from a normal signal. Therefore, an abnormal input signal is supplied to another non-defective chip having the same input signal wiring on the thin film type probe card, which makes normal burn-in or inspection impossible.

In order to avoid this, the input signal wiring and the input signal source for each semiconductor chip may be made independent, but this method increases the wiring amount on the thin film type probe card and the input signal source of the tester. The number increases,
This method is not feasible because the cost of the inspection device will increase significantly. The above-described failure of the power supply wiring or the input signal wiring is not only present before the burn-in, but may also occur during the burn-in. If the defective chip is removed by any method before the burn-in, the defective chip during the burn-in may be removed. Not all can be removed.

The present invention solves the above problems and prevents the defective chip from causing an abnormal potential of the power supply wiring or the input signal wiring, or the rise of temperature due to heat generation of the defective chip. Along with this, it is possible to avoid an increase in the amount of power supply wiring and input signal wiring on the thin film type probe card and the number of power supplies and input signal sources of the tester. The purpose is to remove the influence of defective chips on the semiconductor wafer.

[0017]

In order to achieve the above object, the present invention provides:
Two power supply pads are provided in advance on each integrated circuit chip on the semiconductor wafer, and when a voltage outside the allowable input range is supplied to both of these two power supply pads, the wiring of the power supply and the internal circuit in the chip after that. Is characterized in that it is designed to be disconnected.

Specifically, the present invention is directed to the semiconductor integrated circuit device and the inspection method thereof as described above, and has taken the following solving means.

That is, the first and second solving means of the present invention relate to the former semiconductor integrated circuit device,
A first solution is to provide first and second electrodes for supplying a power supply voltage and a wiring connected to an internal circuit on an integrated circuit chip. Further, the first and second electrodes and the wiring are respectively connected to each branch line of a conductive line formed of three branch lines extending in three directions. Further, the branch line connected to the wiring is constituted by a fuse.

A second solving means is characterized in that, in the first solving means, at least a part of the two branch lines connected to the first and second electrodes are both constituted by a resistance wire.

The third to sixth solving means of the present invention relates to the latter method of inspecting a semiconductor integrated circuit device.
3. The method for inspecting a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed in a matrix on a semiconductor wafer, wherein each of the semiconductor integrated circuit devices arranged in a lateral direction among the semiconductor integrated circuit devices. The power supply voltage is supplied to the first electrode of the semiconductor integrated circuit device through a common wiring, and the second electrode of each of the semiconductor integrated circuit devices among the semiconductor integrated circuit devices arranged in the vertical direction is connected through a common wiring. A step of supplying a power supply voltage to determine whether each semiconductor integrated circuit device is good or bad; and common to each of the first and second electrodes of the semiconductor integrated circuit device determined to be defective among the semiconductor integrated circuit devices. A fuse for a conductive wire connecting the first and second electrodes of the semiconductor integrated circuit device determined to be defective to the internal circuit by simultaneously applying a power supply voltage outside the allowable input range through the wiring Characterized in that it comprises a step of cutting.

A fourth solving means is, in the third solving means, a good semiconductor integrated circuit device having a common wiring with the first and second electrodes of the semiconductor integrated circuit device determined to be defective, The good semiconductor integrated circuit when one of the first and second electrodes is supplied with a power supply voltage outside the allowable input range and the other of the first and second electrodes is supplied with a power supply voltage within the allowable input range. Retaining the connection between the first and second electrodes of the device and the internal circuit.

A fifth solving means is, when a fuse of a conductive wire connecting the first and second electrodes of the semiconductor integrated circuit device determined to be defective in the third solving means and an internal circuit is cut off. The input terminal is electrically floated.

According to a sixth solving means, in the third solving means, the power supply voltage outside the allowable input range supplied to the first and second electrodes of the semiconductor integrated circuit device determined to be defective is a negative voltage. It is characterized by being.

With the above structure, in the first to sixth means for solving the problems of the present invention, not only the defective chips existing before burn-in but also the defective chips generated during burn-in are
Can be removed from burn-in.

That is, with respect to the defective chip, a voltage outside the allowable input range is supplied to both the first and second electrodes at the time of burn-in from the vertical direction and the horizontal direction, and the power supply and the internal circuit are provided inside the defective chip. The circuit wiring is broken. As a result, the defective chip can be electrically separated from the wiring on the inspection device (probe card), so that a large amount of current flows through the defective chip, thereby lowering the voltage of the power supply wiring shared on the probe card. The temperature rise due to heat generation and heat generation does not affect the burn-in or inspection of other good chips.

In addition, by disconnecting the wiring between the power supply and the internal circuit inside the defective chip and stopping the supply of power to the internal circuit, the input signal terminal which is short-circuited with other wiring inside the chip by the function designed in advance is removed. Can be floating. As a result, the input signal wiring in the chip can be electrically separated from the common input signal wiring on the probe card, so that the input signal on the common input signal wiring on the probe card should not be abnormal. Therefore, it does not affect the burn-in and inspection of other good chips. For this reason, it is possible to perform low-cost, normal burn-in or inspection of non-defective chips at the time of probe inspection using a thin-film probe card with common power supply wiring and input signal wiring. Become.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit device A according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an integrated circuit chip, and on the integrated circuit chip 1, first and second electrodes 2 and 3 for supplying a power supply voltage, which are pad electrodes,
Wiring 4 connected to an internal circuit (not shown) is provided. The first and second electrodes 2 and 3 and the wiring 4 are
Conductive wire 5 consisting of three branch lines extending in three directions
Is connected to each branch line. Among the three branch lines of the conductive line 5, the branch line connected to the first electrode 2 is an Al wiring 6, a resistance line 7 made of polycide (a silicide layer is formed on a polysilicon film), and an Al line. The branch line formed by connecting a part of the wiring 8 in series and connected to the second electrode 3 also has a resistance composed of an Al wiring 6 and polycide (a silicide layer is formed on a polysilicon film). The line 7 and a part of the Al wiring 8 are connected in series, and the branch line connected to the wiring 4 is configured by connecting a part of the Al fuse 9 and the Al wiring 8 in series. Here, the resistance value of the resistance wire 7 is 200Ω per piece,
The width of the Al wirings 6, 8 is, for example, 20 μm, and the width of the fuse 9 is, for example, 2 μm.
The width is smaller than the width.

When the normal integrated circuit chip 1 is used, the two first and second electrodes 2 and 3 are supplied with the power supply voltage during normal use within the allowable input range, for example, 3.3V. . Since the power supply current at this time is not large, the voltage of the Al wiring 8 connecting the resistance line 7 and the fuse 9 becomes substantially equal to the power supply voltage. Therefore, the power supply voltage is supplied to the internal circuit via the fuse 9 and the wiring 4 connected to the internal circuit.
In this way, the structure of this power supply wiring does not hinder normal use of the integrated circuit chip 1.

When performing burn-in, the power supply voltage at the time of burn-in, for example, 6.0 V, is supplied to the two first and second electrodes 2 and 3. Since the power supply current at this time is not large, the voltage of the Al wiring 8 connecting the resistance line 7 and the fuse 9 becomes substantially equal to the power supply voltage. Therefore, the power supply voltage is supplied to the internal circuit via the fuse 9 and the wiring 4 connected to the internal circuit. In this way, the structure of this power supply circuit does not hinder burn-in of the integrated circuit chip 1.

The integrated circuit chip 1 is regularly inspected during burn-in. The power supply voltage at this time is made equal to that during normal use. The voltage state during normal use described above is realized. At this time, an output signal from the integrated circuit chip 1 to be inspected is detected by using a tester (not shown) connected to an output pad (not shown). If the output signal is determined to be normal based on a predetermined standard, the integrated circuit chip 1 is determined to be non-defective and the burn-in voltage is set to 2 again.
The first and second electrodes 2 and 3 are applied. When it is determined that the output signal is not normal based on the predetermined standard, the integrated circuit chip 1 is determined to be defective. At this time, a voltage outside the allowable input range, particularly a negative high voltage, for example −20 V, is applied to the two first and second electrodes 2 and 3 of the defective chip.
Are applied together.

FIG. 2 is an explanatory view of a current path in a CMOS inverter which is a typical internal circuit when a negative high voltage is applied to the two first and second electrodes 2 and 3 of the integrated circuit chip 1. Is. In FIG. 2, 11 is a P well and 1
2 is an NMOSFET gate electrode formed on the P well 11, 13 is an NMOSFET gate oxide film, 14 is an NMOSFET source, 15 is an NMOSFET drain, 16 is an N well, and 17 is formed on the N well 16. Gate electrode of PMOSFET, 18 is PMOSFE
T is a gate oxide film, 19 is a PMOSFET drain,
20 is the source of the PMOSFET, 21 is the wiring that is the input of the inverter, 22 is the wiring that is the output of the inverter, 2
Reference numeral 3 is a power supply wiring, 24 is a wiring for applying a substrate voltage, and 25 is a wiring connected to the ground.

The wiring 24 for supplying the substrate voltage and the wiring 25 connected to the ground are separate in the DRAM, but normally connected in the other CMOS circuits. The power supply wiring 23 is connected to the N well 16 together with the source 20 of the PMOSFET.

When the power supply voltage Vcc is a negative voltage whose absolute value is larger than the substrate voltage Vbb, the P well 11 and the N well 1
The PN junction between 6 is forward and current flows. This current is represented by I (-) in FIG. 2, and flows from the wiring 24 that gives the substrate voltage, through the P well 11 and the N well 16 and into the power supply wiring 23.

The power supply voltage Vcc is a negative high voltage, for example -2.
When the voltage is about 0 V, the P well 11 and the N in the forward direction
The resistance between the wells 16 becomes very small, and the voltage of the wiring 4 connected to the internal circuit is fixed at about -0.6V. Therefore, a difference of 19.4V between the power supply voltage of -20V and the voltage of the wiring 4 connected to the internal circuit of -0.6V is applied to the combined resistance of 100Ω of the two 200Ω resistance lines 7 connected in parallel. As a result, a large current of 194 mA flows into the fuse 9 of FIG. 1, and the fuse 9 is blown due to heat generated by electric resistance. As a result, the electrical connection between the internal circuit of the defective chip and the power supply wiring on the probe card can be cut off.

On the other hand, due to the configuration of the common power supply wiring on the probe card, the negative high voltage −20 is applied to the two first and second electrodes 2 and 3 for the defective chip as described above.
When V is applied, both of the two first and second electrodes 2 and 3 are 0V for the non-defective chip, or a negative high voltage of -20V is applied to one and 0V is applied to the other. To be done.

When 0V is applied to both of the two first and second electrodes 2 and 3, the PN junction between the P well 11 and the N well 16 in FIG. 2 is not in the forward direction, No current flows. Therefore, the fuse 9 of FIG. 1 is not blown, and the electrical connection between the internal circuit of the non-defective chip and the power supply wiring on the probe card is maintained.

When one of the two first and second electrodes 2 and 3 has a negative high voltage of -20V and the other has 0V, the resistance between the P well 11 and the N well 16 in the forward direction is extremely low. And the voltage of the wiring 4 connected to the internal circuit is -0.6.
It is fixed at about V. Therefore, 19.4 V is applied to the resistance line 7 of 200 Ω between the first or second electrode 2 or 3 and the Al wiring 8 to which the negative high voltage −20 V is applied. A current of 97 mA flows from the Al wiring 8 toward one of the first and second electrodes 2 and 3. In addition, the other first or second electrode 2, 3 to which 0 V is applied and A
0.6 V is applied to the resistance wire 7 of 200Ω between the 1 wirings 8, and a current of 3 mA flows to the resistance wire 7 from the other first or second electrode 2 or 3 toward the Al wiring 8. . As a result, a current of 94 mA flows through the fuse 9 from the wiring 4 connected to the internal circuit toward the Al wiring 8. This current value is about half the value for a defective chip. At this current value, the heat generation of the fuse 9 is not so large that the fuse 9 is blown, and the electrical connection between the internal circuit of the good chip and the power supply wiring on the probe card is maintained.

With the configuration of the common power supply wiring on the probe card as described above, when a negative high voltage of -20 V is applied to the two power supply pads for a defective chip, the chip becomes a good chip. On the other hand, both of the two first and second electrodes 2 and 3 are set to 0V, or a negative high voltage of -20V is applied to one and 0V is applied to the other, so that The internal circuit and the power supply wiring on the probe card are retained, and the electrical connection between the internal circuit and the power supply wiring on the probe card can be disconnected only for the defective chip.

Further, the input signal wiring in the integrated circuit chip 1 and the input signal wiring on the probe card are designed by preliminarily designing the input terminals to be in an electrically floating state when power is not supplied to the internal circuit. The electrical connection with can be disconnected.

A probe card used for applying a power supply voltage to the two first and second electrodes 2 and 3 of the integrated circuit chip 1 will be described. FIG. 3 is an explanatory diagram of the configuration of the probe card according to the present invention. In FIG. 3, 31 is a semiconductor wafer, 1 is an integrated circuit chip formed on the semiconductor wafer 31 in a matrix, 33 is a bump electrode on a probe card (not shown), and 34 is a first power source of the tester (see FIG. Wiring on the probe card connected to (not shown),
35 is wiring on the probe card connected to the second power supply (not shown) of the tester, 36 is wiring on the probe card connected to the first input signal source (not shown) of the tester,
Reference numeral 37 is a wiring on the probe card connected to a second input signal source (not shown) of the tester.

In this structure, the wiring to each bump electrode 33 on the probe card is independently wired one by one for the wiring 34 connected to the first power source of the tester, and the wiring for the second electrode of the tester. The wirings 35 connected to the power supply are individually wired in vertical columns. Then, one of the two first and second electrodes 2 and 3 provided on each integrated circuit chip 1 is independent of one common wiring 34 extending in the lateral direction and connected to the first power source of the tester. To the second of the tester
One common wire 3 extending in the vertical direction connected to the power supply of
Connect to 5 independently. The wirings 36 and 37 connected to the input signal source of the tester and the wiring (not shown) connected to the ground of the tester are common to all integrated circuit chips 1.

Next, the inspection procedure will be described.

First, after the probe inspection, the bump electrodes 33 of the probe card are connected to the first and second electrodes 2 and 3 of the integrated circuit chip on the semiconductor wafer 31 by the method described in the prior art. As a result, the wiring 3 connected to the first power source of the tester is connected to the first electrode 2 of the integrated circuit chip 1.
4, a wiring 35 connected to the second power source of the tester on the second electrode 3 of the integrated circuit chip 1, wirings 36 and 37 connected to the input signal source on the input terminal, and a tester on the output terminal. The wiring connected to the output signal detector of the bump electrode 33
Connect through.

Thereafter, the temperature of the semiconductor wafer 31 is raised,
Apply a voltage for burn-in. At this time, with respect to the defective chip found in the probe inspection, the wiring 34 connected to the first electrode 2 of the tester extending in the lateral direction on the probe card and the second wire of the tester extending in the vertical direction on the probe card. Both of the wirings 35 connected to the electrodes 3 are applied with the above-mentioned negative high voltage -20V. The other power supply voltage is fixed at 0V.

As a result, for a defective chip, a large current is caused to flow through the fuse 9 between the first and second electrodes 2 and 3 and the internal circuit shown in FIG. Disconnect electrical connection to internal circuits. This makes it possible to remove a defective chip existing before burn-in from the burn-in. By blowing the fuse 9, the defective chip does not electrically affect burn-in or inspection of another integrated circuit chip 1 through the common power supply wiring. Further, since the defective chip is not supplied with power, the defective chip and the power supply wiring on the probe card do not generate heat due to the current, and the temperature rise due to the heat generation does not affect burn-in or inspection of other integrated circuit chips 1. . For this reason, it is possible to carry out batch burn-in or inspection in a wafer state for a non-defective chip at the time of probe inspection at low cost and without problems using a probe card having a common power supply.

In addition, due to the function designed in advance, the input terminals of the defective chip are brought into an electrically floating state, and the input signal wiring inside the integrated circuit chip 1 and the common input signal wiring on the probe card are electrically connected. The physical connection is disconnected. Thus, it is possible to prevent the signal of the shared input signal wiring on the probe card from becoming abnormal due to a short circuit between the input signal wiring in the defective chip and another wiring. As a result, a normal input signal is supplied to another non-defective chip having a common input signal wiring on the probe card, and normal burn-in or inspection can be performed.

At this time, only one of the two first and second electrodes 2 and 3 has a negative high voltage in the non-defective chip which is in the same horizontal and vertical directions as the defective chip, and the other one has a negative high voltage. The number is fixed at 0V. As described above, in this case, due to the action of the resistance wire 7 between the two first and second electrodes 2 and 3 in the integrated circuit chip 1, the value of the current flowing through the fuse 9 is a defective chip. To about half, and the fuse 9 does not blow. Therefore, the operation of blowing the fuse 9 inside the defective chip does not disconnect the non-defective chip from the power supply wiring.

Defective chips generated during burn-in are found by regularly inspecting during burn-in. For defective chips found during burn-in,
Similarly to the case of a defective chip found at the time of probe inspection, a negative high voltage is applied to both the wiring 34 connected to the first power supply and the wiring 35 connected to the second power supply of the tester, and Fix the wiring to 0V. This disconnects the electrical connection between the defective chip generated during the burn-in and the power supply wiring, and removes the defective chip generated during the burn-in. In this way, the batch burn-in of the good chip in the wafer state can be normally executed.

[0051]

As described above, according to the present invention, the first and second electrodes are provided on each integrated circuit chip on the semiconductor wafer, and these first and second electrodes are connected to the internal circuit on the way. Install a fuse in. For a defective chip, a voltage outside the allowable input range is supplied to both of the two first and second electrodes to blow the fuse so that power supply to the internal circuit is stopped. Therefore, when performing batch burn-in on an integrated circuit chip formed on a semiconductor wafer in a wafer state, defective chips found at the time of inspection or burn-in are removed together, and normal burn-in is performed only on good chips. It is possible to At this time, there is no increase in inspection cost due to an increase in the amount of wiring of the probe card or an increase in the number of power supplies and input signal sources of the tester. Therefore, it is possible to improve the reliability of the product in the market at low cost.

[Brief description of drawings]

FIG. 1 is a power supply wiring configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of current paths in an internal circuit when a negative high voltage is applied to first and second electrodes of an integrated circuit chip.

FIG. 3 is a configuration diagram of a thin film type probe card.

FIG. 4A is a perspective view showing a connection state between a conventional semiconductor wafer and a thin film type probe card, and FIG. 4B is an enlarged sectional view showing a main part thereof.

[Explanation of symbols]

 1 Integrated Circuit Chip 2 1st Electrode 3 2nd Electrode 4 Wiring 5 Conductive Line 6 Al Wiring (Branching Line) 7 Resistance Wire (Branching Line) 8 Al Wiring (Branching Line) 9 Fuse (Branching Line) 31 Semiconductor Wafer A Semiconductor integrated circuit device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/66 G01R 31/28 U Y

Claims (6)

[Claims] 1. An integrated circuit chip is provided with first and second electrodes for supplying a power supply voltage and wiring connected to an internal circuit, and the first and second electrodes and wiring are A semiconductor integrated circuit device, comprising: a branch line connected to each branch line of a conductive line formed by three branch lines branching in a direction, and the branch line connected to the wiring line being a fuse. 2. The semiconductor integrated circuit device according to claim 1, wherein at least a part of each of the two branch lines connected to the first and second electrodes is formed of a resistance line. 3. The method for inspecting a semiconductor integrated circuit device according to claim 1, which is formed in a matrix on a semiconductor wafer, wherein each semiconductor integrated circuit device among the semiconductor integrated circuit devices is arranged in a lateral direction. A power supply voltage is supplied to each first electrode of each of the semiconductor integrated circuit devices through a common wiring, and a common wiring is provided to each of the second electrodes of the semiconductor integrated circuit devices arranged in the vertical direction among the semiconductor integrated circuit devices. A step of supplying a power supply voltage via each of the semiconductor integrated circuit devices to determine pass / fail of each semiconductor integrated circuit device; and, for each of the first and second electrodes of the semiconductor integrated circuit device determined to be defective among the semiconductor integrated circuit devices, A fuse for a conductive line connecting the first and second electrodes of the semiconductor integrated circuit device determined to be defective to the internal circuit by simultaneously applying a power supply voltage outside the allowable input range through the common wiring of A method of inspecting a semiconductor integrated circuit device, characterized in that a step for cutting. 4. A permissible input range for one of the first and second electrodes of a good semiconductor integrated circuit device having a common wiring with the first and second electrodes of the semiconductor integrated circuit device determined to be defective. When the external power supply voltage is supplied and the power supply voltage within the input allowable range is supplied to the other of the first and second electrodes,
4. The connection between the first and second electrodes of the good semiconductor integrated circuit device and the internal circuit is maintained.
A method for inspecting a semiconductor integrated circuit device as described above. 5. An electrically floating state of an input terminal when a fuse of a conductive line connecting the first and second electrodes of a semiconductor integrated circuit device determined to be defective to an internal circuit is cut. 4. The method for inspecting a semiconductor integrated circuit device according to claim 3. 6. The power supply voltage outside the allowable input range supplied to the first and second electrodes of the semiconductor integrated circuit device determined to be defective is a negative voltage. Inspection method of semiconductor integrated circuit device.