JP3408757B2 - Burn-in device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burn-in device, and more particularly to a burn-in device for confirming signal line connection when performing a screening process in a wafer state.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices have been used as a screening process for improving the reliability of semiconductor devices.
125 ° C while applying a power supply voltage that is rated or slightly overvoltage and applying a signal close to actual operation to each signal input electrode
Burn-in is performed for several hours in a high temperature state. Conventionally, this burn-in process is often performed in a product state in which a semiconductor device is housed in a package. The semiconductor device housed in the package was equipped with a terminal for drawing out the signal line, and when burn-in was performed, the burn-in process could be easily performed without inserting the socket and checking the connection. .

However, in recent years, it has been desired to perform burn-in on semiconductor chips in a wafer state for the purpose of screening in a more upstream process. In order to realize burn-in to a semiconductor chip in a wafer state, it is necessary to connect a signal line to a bonding pad that is an extraction electrode of a plurality of semiconductor chips formed on a wafer and apply a signal. The signal line connection method may differ slightly depending on the type of device such as memory or logic, but here, an example of a memory device will be described.

Usually, 100 to 400 semiconductor chips are formed on a wafer, and each semiconductor chip has from 20 to 20 bonding pads which are electrodes of a micro size of about 100 μm.
About 40 electrodes are arranged and a total of 2000 to 16000 signal line connections per wafer must be accurately connected to these electrodes. That is, in order to realize burn-in to a semiconductor chip in a wafer state, it is necessary to make a large number of signal line connections, and it is desirable to confirm that the signal line connections are correctly made before performing burn-in. There is.

FIG. 3 shows the state of signal line connection to the wafer. In FIG. 3, 11 is a wafer,
A large number of semiconductor chips are formed on this. As a concrete example, as the center row on the wafer 11, 21, 2
2, 23, 24, 25, 26, 27, 28 semiconductor chips, and peripheral rows include 31, 32, 33, 34 semiconductor chips and 41, 42 semiconductor chips.

Reference numeral 12 is a contactor, which is composed of contacts electrically connected to all the electrodes of the semiconductor chip formed on the wafer 11 and signal lines drawn from the contacts, and contacts the wafer 11. Use (contact under pressure). The important point at this time is not to draw out the signal line independently for each semiconductor chip on the wafer, but as shown in FIG. 3, a plurality of semiconductor chips arranged in a circle are arranged in columns and rows. It is common practice to connect the signal lines to the semiconductor chip in parallel and lead them out.

Specifically, the semiconductor chips 21 in the central row,
Horizontal signal lines corresponding to 22, 23, 24, 25, 26, 27, 28
51, there are horizontal signal lines 52 corresponding to the semiconductor chips 31, 32, 33, 34 in the peripheral rows, and there are horizontal signal lines 53 corresponding to the semiconductor chips 41, 42. Further, there are vertical signal lines 54 corresponding to the semiconductor chips 24, 32, 41 in the central row of the wafer, and vertical signal lines 55 corresponding to the semiconductor chips 25, 33, 42 in the central row. . In this example, the horizontal signal lines 51, 52, and 53 include the address lines A0 to A7, the data lines D0 to D3, and the write control line WE among the signal lines that drive the memory. The direction signal lines 54 and 55 include the read control line OE among the signal lines for driving the memory.

With such a signal line configuration, writing is simultaneously performed on each semiconductor chip 21, 22, 23, 24, 25, 26, 27, 28, and at the time of reading, each semiconductor chip 21 is read using the read control line OE. , 22, 23, 24, 25, 26, 27, 28 can be sequentially read and tested one chip at a time.

FIG. 4 shows a concrete example. FIG. 4 shows address lines A0 to A7 and data lines D0 to D0 included in the horizontal signal line 52.
D3, the write control line WE, the vertical signal line 54, and the read control line OE included in the vertical signal line 55 are shown. That is, the signal lines of the address lines A0 to A7, the data lines D0 to D3, and the write control line WE are drawn out in parallel from the respective electrodes of the semiconductor chips 31, 32, 33, 34. In addition, the semiconductor chips 24, 32,
The signal line 54 of the read control line OE is drawn in parallel from the OE electrode of 41, and the signal line 55 of the read control line OE is drawn in parallel from the OE electrodes of the semiconductor chips 25, 33, 42.

As a means for confirming the signal line connection between the wafer and the contactor, there is a method of testing the state of the signal line by direct current as shown in FIG. In FIG. 5, 31, 32, 3
Reference numerals 3 and 34 are semiconductor chips formed on the wafer 11. Describing one electrode of the semiconductor chips 31, 32, 33, 34, protection electrodes for protecting input signals 61, 62, 63, 64 are built in the semiconductor chip at the electrodes, respectively. Reference numeral 52 is a signal line provided in the contactor, which is connected to each electrode through a contact and is led out to the outside of the contactor. Reference numeral 65 denotes a power supply, which can generate direct currents having different positive and negative polarities of about 100 μA and apply them to the signal line 52. However, a limit circuit is incorporated so that a semiconductor chip on the wafer is not destroyed and a voltage higher than a positive and negative limit voltage of about 5 V is not generated. 66 is a digibol, and the signal line 52
And measures the DC voltage of the signal line 52.

The operation will be described below. When the electrodes of the semiconductor chip are measured from the outside due to the presence of the protection diode, a high resistance is exhibited when a positive voltage is applied, and a diode characteristic by the protection diode is exhibited when a negative voltage is applied. Therefore, when a positive current of 100 μA is applied to the signal line 52 from the power supply 65, the semiconductor chips 31, 3 are normally connected to the signal line.
No current flows when 2, 33 and 34 are connected. Therefore, the DC potential of the signal line 52 becomes a positive limit voltage, and the potential can be read by the digibol 66. If any of the semiconductor chips 31, 32, 33, 34 is damaged,
When the contact is not normally made and a short circuit occurs between the contact and the adjacent contact, current leakage occurs and a low voltage below the limit voltage is observed.

Next, when a negative current of 100 μA is applied to the signal line 52 from the power supply 65, the semiconductor chip 31,
When 32, 33 and 34 are connected, a current flows through the protection diode built in each semiconductor chip. Signal line 52
The DC electric potential of becomes a voltage of about -0.3 V, and the electric potential can be read by the digibol 66. Semiconductor chip 3
When any one of 1, 32, 33, 34 is damaged or the contact is not made normally and a short circuit occurs with the adjacent contact, current leakage occurs and a low voltage less than −0.3V. Is observed. Also, the contact is not made normally,
When all the contacts cannot be connected, no current flows, the DC potential of the signal line 52 becomes a negative limit voltage, and the potential can be read by the digibol 66.

[0013]

However, in the conventional method of applying positive and negative direct currents, the semiconductor chip 3
When any one of 1, 32, 33, 34 is damaged, or contact is not made normally and a short circuit occurs between adjacent contacts, or contact is not made normally, semiconductor chips 31, 32, 33 , When all the contacts of 34 cannot be connected, an abnormality is found, but semiconductor chips 31, 32, 33,
If any of the 34 are open, no anomaly is known.

That is, in the test using direct current according to the conventional method shown in FIG. 5, since the signal line connection to the chips on the wafer is performed in parallel for each column and each row, some connections are incomplete. However, it could not be detected, and semiconductor chips 31, 3
If any of the connections of 2, 33, 34 are opened, no abnormality is found, so it is difficult to check the connection of all semiconductor chips connected to that signal line, which prevents its practical application. I was there.

An object of the present invention is to solve the above-mentioned conventional problems and to make it possible to confirm the connection of signal lines when performing burn-in in a wafer state.

[0016]

In order to solve the above problems, in the present invention, a burn-in device is provided with a divided power line or ground line connected to a semiconductor chip formed on a wafer to be burned in. , A signal line orthogonal to the power supply line or the ground line and connected to the semiconductor chip, a means for supplying a direct current between the power supply line or the ground line and the signal line, and a connection between the power line or the ground line and the signal line It is configured to have a means for measuring the voltage and a means for confirming the connection between the semiconductor chip and the signal line by the value of the measured voltage. That is,
While the signal lines are wired horizontally, the power supply or ground line is divided horizontally to be supplied, and each divided independent vertical power line / ground line is connected to each signal line. Measure the DC characteristics of. Signal lines are connected in the horizontal direction to a large number of semiconductor chips arranged in the wafer, while power supply or ground, or both power supply / ground for each row in the vertical direction divided in the horizontal direction. Supplied by wire. By passing a direct current between each of the divided power / ground lines and the signal line in the lateral direction, the voltage generated at both ends thereof is measured.

With this configuration, the diode characteristics can be independently measured for each chip, and the connection between the contact provided on the contact and the electrode of the semiconductor chip can be independently and reliably confirmed. By independently measuring the current flowing through the protection diode between the signal electrode of the semiconductor chip and the power / ground electrode for each chip, the contact between the contactor of the contactor and the electrode of the semiconductor chip is independent and secure. Can be confirmed.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention is
A divided power line or ground line connected to the semiconductor chip formed on the wafer to be burned in, a signal line orthogonal to the power line or ground line and connected to the semiconductor chip, and the power line or Means for flowing a direct current between the ground line and the signal line, means for measuring the voltage between the power line or the ground line and the signal line, the semiconductor chip and the signal by the value of the measured voltage The burn-in device is provided with a means for confirming the wire connection, and has an effect of independently and surely confirming the connection between the contact provided on the contactor and the electrode of the semiconductor chip.

According to a second aspect of the present invention, a power supply line or a ground line divided into semiconductor chips formed on a wafer to be burned in is connected, and a signal line orthogonal to the power supply line or the ground line is connected. Is connected to the semiconductor chip, a direct current is passed between the power line or ground line and the signal line, the voltage between the power line or ground line and the signal line is measured, and the measured voltage It is a burn-in method for confirming the connection between the semiconductor chip and the signal line by a value, and has an effect of independently and surely confirming the connection between the contact provided on the contactor and the electrode of the semiconductor chip.

FIG. 1 shows an embodiment of the present invention.
Will be described in detail with reference to FIG.

(Embodiment) In the embodiment of the present invention, a divided power line and a signal line orthogonal to the power line are connected to a semiconductor chip formed on a wafer to be burned in, and the power line is connected. Is a burn-in device that selects a signal line with a switch, applies a direct current, measures the voltage between the power line and the signal line, and confirms the connection between the semiconductor chip and the signal line based on the measured voltage value.

FIG. 1 is a block diagram of a burn-in system according to an embodiment of the present invention. In FIG. 1, 11 is a wafer, in which the chip 1 (31), chip 2 (32), chip 3 (33), chip 4 (34) and chip 5 (41), chip 6 (4)
A large number of semiconductor chips composed of 2) are formed. Each of these chips has the internal structure shown in FIG.

In FIG. 2, 101 is the signal electrode A1,
It constitutes a part of a bonding pad that provides an address signal to the memory. A signal electrode A2 102 constitutes a part of a bonding pad for supplying an address signal to the memory. Reference numeral 103 denotes a signal electrode A3, which constitutes a part of a bonding pad that gives an address signal to the memory. 104 is a power supply electrode, which is a bonding pad for supplying power to the memory. Reference numeral 105 denotes a ground electrode, which is a bonding pad that supplies ground to the memory.

Reference numeral 111 denotes a protection diode, which is a signal electrode A1.
Signal electrode A1 for protection against (101) input signal
And the ground electrode 105. Reference numeral 112 denotes a protection diode, which is arranged between the signal electrode A2 and the ground electrode 105 for the purpose of protecting the signal electrode A2 (102) against an input signal. 113 is a protection diode, which is a signal electrode A3 (10
It is arranged between the signal electrode A3 and the ground electrode 105 for the purpose of protecting the input signal of 3). Reference numeral 114 denotes a protection diode, which is arranged between the signal electrode A1 and the power supply electrode 104 for the purpose of protecting the signal electrode A1 (101) against an input signal. 115 is a protection diode, signal electrode A2 (102)
Is arranged between the signal electrode A2 and the power supply electrode 104 for the purpose of protecting the input signal of the. Reference numeral 116 denotes a protection diode, which is arranged between the signal electrode A3 and the power supply electrode 104 for the purpose of protecting the signal electrode A3 (103) against an input signal.

That is, semiconductors 111, 112, 113, 114, 115 and 116 are provided between the signal electrodes 101, 102 and 103 of the semiconductor chips 31, 32, 33 and 34 and the power electrode 104 and the ground electrode 105, respectively. There is a diode characteristic due to the protection diode of the chip.

Returning to FIG. 1, the structure of the burn-in device according to the embodiment of the present invention will be described. Reference numeral 71 denotes a power supply line VCC1 provided in the contactor, which supplies power to each of a vertical row of chips including the chip 1 (31) through contacts to respective power supply electrodes. Reference numeral 72 is a power supply line VCC2 provided in the contactor, and for the vertical row of chips including the chip 2 (32),
Power is supplied to each power electrode through a contact. 73
Is the power supply line VCC3 provided in the contactor, and the chip 3
Power is supplied to each of the chips in a vertical line including (33) through a contact point to each power electrode. Reference numeral 74 denotes a power supply line VCC4 provided in the contactor, which supplies power to each group of chips in a vertical line including the chip 4 (34) through contacts to respective power supply electrodes.

Reference numeral 75 denotes a signal line A1 provided in the contactor, which is connected to the electrode A1 of each chip through a contact, and is connected to the chip 1 (31), chip 2 (32), chip 3 (33),
Address of each chip in the horizontal row including chip 4 (34)
The A1 signal is pulled out of the contactor. Reference numeral 76 is a signal line A2 provided in the contactor, which is connected to the electrode A2 of each chip through a contact, and is connected to the chip 1 (3
The address A2 signal of each chip in the horizontal row including 1), the chip 2 (32), the chip 3 (33), and the chip 4 (34) is extracted to the outside of the contactor. Reference numeral 77 is a signal line A3 provided in the contactor, which is connected to the electrode A3 of each chip through a contact, and is connected to the chip 1 (31), chip 2 (32), chip 3 (33), chip 4 (34). The address A3 signal of each chip in a row in the horizontal direction including is drawn to the outside of the contactor.

Reference numeral 91 is a power source, which can generate direct currents having different positive and negative polarities of about 100 μA and can be applied between the signal line and the power source line. However, a limit circuit is incorporated so that a voltage above the positive and negative limit voltages of about 5 V is not generated so as not to damage the semiconductor chip on the wafer.
Reference numeral 92 is a digibol, which is connected to the signal line and measures the DC voltage between the signal line and the power supply line.

Reference numeral 81 is a switch 1, which is inserted in the power supply line VCC1 (71) to turn on / off the connection between the power supply 91 and the digibol 92 and the power supply line VCC1. Reference numeral 82 is a switch 2, which is a power supply line VCC2 (7
Inserted in 2) turns on / off the connection between the power supply 91 and digibol 92 and the power supply line VCC2. 83 is a switch 3 and a power supply line VC
It is inserted in C3 (73) and power supply 91 and digibol 92 and power supply line VCC3
Turn the connection on and off. 84 is a switch 4, which is inserted in the power supply line VCC4 (74) and is connected to the power supply 91, digibol 92 and power supply line.
Turn the VCC4 connection on and off. 85 is a switch 5,
It is inserted into the signal line A1 (75) to turn on / off the connection between the power supply 91 and the digibol 92 and the signal line A1. A switch 6 is inserted in the signal line A2 (76) to turn on / off the connection between the power supply 91 and the digibol 92 and the signal line A2. A switch 7 is inserted in the signal line A3 (77) to turn on / off the connection between the power supply 91 and the digital signal 92 and the signal line A3.

The operation of the burn-in device of the embodiment of the present invention configured as described above will be described below. First, turn on switch 1 (81) and switch 5 (85),
All other switches are turned off and set so that current can be applied to the power supply line 71 and the signal line 75. In this state, the electrodes of the semiconductor chip are externally measured using the power supply 91 and the digibol 92.

When a negative voltage is applied to the signal line A1 (75) with respect to the power supply line 71, a high resistance is exhibited, and when a positive voltage is applied, a diode characteristic due to a protection diode is exhibited. Therefore, when a negative current of 100 μA from the power supply 91 is applied to the power supply line VCC1 (71) from the signal line A1 (75), the A1 signal of the semiconductor chip 31 is normally connected to the signal line A1 (75) and the power supply is Line VCC1
No current flows when the power electrode of the semiconductor chip 31 is normally connected to (71). Therefore, the DC potential of the signal line 52 becomes a negative limit voltage, and the potential can be read by the digibol 92. When the semiconductor chip 31 is damaged or contacts are not normally made and a short circuit occurs between adjacent contacts, current leakage occurs and a low voltage below the limit voltage is observed.

Next, when a positive current of 100 μA is applied from the power supply 91 to the power supply line VCC1 (71) from the signal line A1 (75), the signal line A1 (75)
When the A1 signal of the semiconductor chip 31 is normally connected to (75) and the power electrode of the semiconductor chip 31 is normally connected to the power supply line VCC1 (71), the protection diode built in the semiconductor chip is connected. An electric current flows. The DC potential of the signal line A1 (75) is about +0.3 V with respect to the power supply line VCC1 (71), and the potential can be read by the digibol 92. When the semiconductor chip 31 is damaged or a contact is not made normally and a short circuit occurs with an adjacent contact, current leakage occurs and a low voltage of less than +0.3 V is observed. Also, when the contact is not made normally and the connection with the contact cannot be established, no current flows and the DC potential of the signal line A1 (75) becomes a positive limit voltage with respect to the power supply line VCC1 (71). The electric potential can be read by the digibol 92.

Third, the switch 1 (81) and the switch 6
With (86) turned on and all other switches off,
By performing the above measurement, the connection between the signal line A2 (76) and the signal terminal A2 (102) of the chip 1 (31) can be tested.

Fourth, the switch 1 (81) and the switch 7
With (87) turned on and all other switches off,
By performing the above measurement, the connection between the signal line A3 (77) and the signal terminal A3 (103) of the chip 1 (31) can be tested.

Fifth, the switch 2 (82) and the switch 5
With (85) turned on and all other switches off,
By performing the above measurement, the connection between the signal line A1 (75) and the signal terminal A1 (101) of the chip 2 (32) can be tested. Similarly, the connection between each signal line and each electrode can be tested independently for each chip in the same manner.

That is, in the burn-in device of the present embodiment, the switches are switched to sequentially select the combination of the power supply line and the signal line connected to the chip,
By applying the positive and negative direct currents, it is possible to independently confirm the contact between the power supply line and the power supply electrode and the signal line and the signal electrode for each semiconductor chip. This makes it possible to confirm the connection of all the semiconductor chips connected to the signal line, guarantee all the connections between the wafer and the contactor, and promote the practical use of burn-in in the wafer state.

Although the power supply line is divided in this embodiment,
The same effect can be obtained by dividing the ground line or the substrate signal line, and a better effect can be obtained by dividing both the power supply line and the ground line or the substrate signal line. Further, even if the power supply / ground line or the substrate signal line is not divided into every one chip in the horizontal direction, or if it is combined into a plurality of chips, the degree of guarantee of connection is reduced, but the same effect is obtained. be able to. As a practical means, power supply /
A method of supplying a ground / substrate signal is effective.

As described above, in the embodiment of the present invention,
The burn-in device connects the divided power line and the signal line orthogonal to the power line to the semiconductor chip formed on the wafer to be burned in, and selects the power line and the signal line with the switch to generate the direct current. Since the voltage between the power line and the signal line is measured and the connection between the semiconductor chip and the signal line is confirmed by the measured voltage value, the semiconductor chip
When any one of the connections of 31, 32, 33, 34 is opened, the abnormality can be detected.

[0039]

As described above, according to the present invention, the burn-in device is provided with the divided power line or ground line connected to the semiconductor chip formed on the wafer to be burned in, and the power line or ground line. Signal lines that are orthogonal to each other and are connected to the semiconductor chip, means for flowing a direct current between the power supply line or the ground line and the signal line, and means for measuring the voltage between the power supply line or the ground line and the signal line, Since it is configured to have a means for confirming the connection between the semiconductor chip and the signal line based on the measured voltage value, the abnormality can be detected even when any of the semiconductor chip connections is opened. The effect that the connection confirmation of the signal line is easy and reliable can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a burn-in device according to an embodiment of the present invention,

FIG. 2 is a diagram showing an internal configuration of a semiconductor chip to be burned in;

FIG. 3 is a diagram showing a semiconductor chip on a wafer and signal lines on a contactor;

FIG. 4 is a detailed view of a signal line on a contactor,

FIG. 5 is a diagram of a test using a conventional direct current.

[Explanation of symbols]

11 wafers 12 contactors 21-28 Semiconductor chip 31-34 Semiconductor chip 41-42 Semiconductor chip 51 to 55 signal line 61-64 protection diode 65 power 66 Digibol 71 to 74 Power line 75 to 77 signal line 81-87 switch 91 Power 92 Digibol 101-103 Signal electrode 104 power electrode 105 Ground electrode 111-116 Protection diode

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/66 G01R 31/26

Claims (2)

(57) [Claims] 1. A divided power line or ground line connected to a semiconductor chip formed on a wafer to be burned in, and a signal line orthogonal to the power line or ground line and connected to the semiconductor chip. A means for supplying a direct current between the power supply line or ground line and the signal line; a means for measuring the voltage between the power supply line or ground line and the signal line; A burn-in device comprising a semiconductor chip and means for confirming connection between the signal line. 2. A divided power line or ground line is connected to a semiconductor chip formed on a wafer to be burned in, and a signal line orthogonal to the power line or ground line is connected to the semiconductor chip, A direct current is passed between the power line or ground line and the signal line, the voltage between the power line or ground line and the signal line is measured, and the semiconductor chip and the signal line are measured according to the measured voltage value. The burn-in method characterized by confirming the connection of.