KR20100053296A - Method, device and recording medium for testing multi-chip package - Google Patents

Abstract

PURPOSE: A method and a device for testing a multi-chip package and a recording media with a program for performing the method are provided to rapidly verify the assembly quality of the multi-chip package using an open-short test. CONSTITUTION: The input-output pads of a first chip and a second chip are bonded with a connection unit in order to form a multi-chip package. A test device(310) is connected to the VDD power source of the first chip(VDD-1), a ball grid array(BGA) ball(120) and the VDD power source of the second chip(VDD-2). The test device is connected to the VSS power source of the first chip(VSS-1), the BGA ball and the VSS power source of the second chip(VSS-2). The first diode(230a) of the first chip, the second diode(235a) of the first chip, the first diode(230b) of the second chip and the second diode(235b) of the second chip are successively tested. The VSS power source is capable of being ground power source.

Description

Method, device and recording medium for testing multi-chip package

The present invention relates to a test method and apparatus for a multi-chip package (MCP).

As the performance of electric and electronic products is improved, various technologies for providing high capacity semiconductor modules have been researched and developed. Methods for implementing high-capacity semiconductor modules include, for example, high integration of devices, a method of manufacturing a stack structured package, and a reduction in the size of a package, thereby increasing the number of packages in a limited size printed circuit board. There is a method to be mounted. In response to these various technologies, various types of packages such as thin small outline package (TSOP), fine pitch ball grid array (FBGA), and multi chip package (MCP) have been developed.

In addition, as the speed and miniaturization of the multimedia system are increasing, components mounted therein are gradually becoming smaller. For example, in the case of semiconductor ICs, miniaturization is achieved through reduction of memory chips, and board mounting efficiency is increased by mounting several chips in one package.

1 is a diagram illustrating a configuration of a general multi-chip package.

As shown in the drawing, a package having several chips having different functions in one package is generally called a multi-chip package (MCP).

Each chip in the multichip package is attached to one substrate and electrically connected to each other to perform one function. That is, I / O pads 115-11 and 115-12 provided in the first chip 110-1 and I / O pads provided in the second chip 110-2. The 115-21 and 115-22 are connected to each other by a wire bonding method around the ball grid array (BGA) balls 120-1 and 120-2. Although FIG. 1 illustrates that only a few input / output pads are provided in each chip, the number of input / output pads provided may be variously determined and applied.

As implemented in this way, a multichip package product may include a plurality of chips in one package, thereby greatly reducing the size of the applied system.

However, in the multichip packaged products, the electrical connection between each chip that is electrically connected to each other to perform one function is normally performed (for example, the wire bonding connecting the BGA ball and the input / output pads of each chip is normally performed. Whether a chip is lost, etc.), and the multichip package should be checked before release.

However, if the input / output pins of the input / output pads 115-23 of any of the chips are connected to the ground pins, the conventional test method may not verify whether the electrical connection between the chips is normally performed. there was.

The present invention is to provide a test method and apparatus for a multi-chip package that can accurately test the electrical connection between each chip provided in the multi-chip package (Multi-Chip Package).

In addition, the present invention is to provide a test method and apparatus for a multi-chip package that can accurately test the electrical connection between each chip even when the input and output pins of a particular chip provided in the multi-chip package is connected to the ground pin.

In addition, the present invention is to provide a test method and apparatus for a multi-chip package that can quickly determine whether the assembly of the multi-chip package product using an open / short test concept.

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the present invention, a test apparatus for a multi-chip package (wire-bonding) is implemented by the wire bonding of the input and output pads of the first chip and the input and output pads of the second chip via the connecting member. A test medium and a recording medium having recorded thereon a program for performing the test method are provided.

 According to one or more exemplary embodiments, a test method includes: applying a first voltage to a VDD power terminal and the connection member of the first chip; And sinking current through the VDD power terminal of the second chip and measuring a voltage across the VDD power terminal of the second chip. Here, an input / output pin (I / O pin) may be connected to a ground pin or a VSS terminal in one or more of the plurality of input / output pads included in the second chip.

When the voltage measured at the VDD power terminal of the second chip coincides within an error value with the turn-on voltage of the PMOS diode of the electrostatic discharge protection circuit provided in the input / output pad of the second chip. It may be determined that wire bonding between the connection member and the input / output pad is normal.

The first voltage may have an arbitrary voltage value greater than the turn-on voltage of the PMOS diode.

The current sinking into the VDD power terminal of the second chip may be at least a current value required to turn on the PMOS diode.

Current sinking through the VDD power terminal of the second chip may flow in the direction of the connection member, the PMOS diode, and the VDD power terminal.

In addition, the test method described above may be implemented as a software program.

According to another aspect of the present invention, a test is performed on a multi-chip package in which an input / output pad of a first chip and an input / output pad of a second chip are wire bonded through a connecting member. A test apparatus is provided.

According to one or more exemplary embodiments, a test apparatus includes: means for applying a first voltage to a VDD power terminal and the connection member of the first chip, respectively; And means for measuring a voltage applied to the VDD power terminal of the second chip by sinking current through the VDD power terminal of the second chip. Here, an input / output pin (I / O pin) may be connected to a ground pin or a VSS terminal in one or more of the plurality of input / output pads included in the second chip.

When the voltage measured at the VDD power terminal of the second chip coincides within an error value with the turn-on voltage of the PMOS diode of the electrostatic discharge protection circuit provided in the input / output pad of the second chip. It may be determined that wire bonding between the connection member and the input / output pad is normal.

The first voltage may have an arbitrary voltage value greater than the turn-on voltage of the PMOS diode.

The current sinking into the VDD power terminal of the second chip may be at least a current value required to turn on the PMOS diode.

Current sinking through the VDD power terminal of the second chip may flow in the direction of the connection member, the PMOS diode, and the VDD power terminal.

The present invention has the effect of accurately testing the electrical connection between each chip provided in the multi-chip package (Multi-Chip Package).

In addition, the present invention also has the effect of accurately testing the electrical connection state between each chip even when the input and output pins of the particular chip provided in the multichip package is connected to the ground pin.

In addition, the present invention also has the effect of being able to quickly determine whether the assembly of the multi-chip package product using the open / short test concept.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the present specification will be described with reference to a multi-chip package consisting of two chips, it is obvious that the present invention can be applied to a multi-chip package consisting of more than one chip without limitation.

2 is a view showing a conventional electrostatic discharge protection circuit.

The input / output pad provided in the microprocessor chip is provided with a protection diode for protecting the internal circuit from abnormal external signals input into the input / output pin. The protection diode also serves to prevent electrostatic discharge or electrostatic discharge (ESD) caused by the application of voltages significantly exceeding the normal operating voltage range to internal circuitry that must be operated with low voltage values.

The present invention is to test whether the wire bonding (wire bonding) is normal by using a protection diode provided to prevent the electrostatic breakdown phenomenon, and to determine whether the connectivity between the plurality of chips is normal or bad based on the test result. do.

Hereinafter, a conventional electrostatic discharge protection circuit will be described with reference to FIG. 2.

2, a conventional electrostatic discharge protection circuit includes an input pad 210, a connection line of an internal circuit 220 connected to the input pad 210, an input pad 210, and an internal circuit 220 and a first power source. The first diode 230 is connected between the VDD power supply, which is the voltage, and the second diode 235 is connected between the connection line of the input pad 210 and the internal circuit 220 and the VSS power supply, which is the second power supply voltage. Here, the VSS power supply may be ground.

The first diode 230 includes a PMOS transistor, and a source and a gate are connected in common. The second diode 235 is formed of an NMOS transistor, and a source and a gate are connected in common.

When a strong electrostatic voltage is applied to the input pad 210, it is discharged by diodes 230 and 235 formed of a pull-up transistor and a pull-down transistor.

For example, a static electricity of -2000 to + 2000V may be induced by a human hand. When static electricity of such a voltage level flows into the device, electrostatic breakdown may occur. When 230 is turned on and the voltage drops to the VDD power supply, when -2000V flows, the second diode 235 is turned on to drop the voltage toward the VSS power supply.

3 is a circuit diagram illustrating a method of testing a connection state of a multichip package according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the test apparatus 310 includes a VDD power supply VDD-1 and a BGA ball of the first chip 110-1 for purposes of voltage application, current sourcing, and current sinking. And a VDD power source VDD-2 of the 120 and the second chip 110-2, respectively. In addition, although not shown, the test apparatus 310 may include a VSS power supply (VSS-1) of the first chip 110-1, a VGA power supply of the BGA ball 120, and a VSS power supply (VSS−) of the second chip 110-2. 2) may be further connected to each.

Subsequently, the first diode 230a of the first chip 110-1, the second diode 235a of the first chip 110-1, the first diode 230b of the second chip 110-2, The test is performed in the order of the second diode 235b of the second chip 110-2. Of course, the test order of each diode is not limited, and it is natural that the test order may be different.

Hereinafter, referring to the circuit diagram of FIG. 3, a method of testing whether the diodes are normally operated to confirm whether the wire bonding between the BGA ball 120 and the input / output pads of each chip is normal will be described. In addition, for convenience of description, the first diode 230b and the second diode 235b of the second chip 110-2 will be described based on the test. Although only described with respect to the second chip 110-2, it will be easily understood that this test scheme is equally applied to the first diode 230a and the second diode 235a of the first chip 110-1. to be.

In addition, it will be described in detail by exemplarily specifying a voltage value, a current value, etc. applied to each position. Of course, the voltage value and the current value below are exemplary values, and it is obvious that different values may be specified. In addition, if there is a voltage basically applied through VDD and VSS of each chip, the test device 310 may apply a voltage proportional to the voltage value for testing each diode.

First, a test method of the first diode 230b provided in the input / output pad of the second chip 110-2 will be described.

The test apparatus 310 tests the first diode 230b by applying a voltage higher than a turn on voltage of the first diode 230b and higher than the voltage applied through VDD-2. In this case, the voltages applied to VSS-1 and VSS-2 may be 0V as in the ground state, and a voltage having the same magnitude as VDD-1 may be applied to the BGA ball 120.

Assuming that the turn-on voltage of the first diode 230b is 0.7V, the test apparatus 310 applies a voltage higher than 0.7V to VDD-1 and a voltage of 0V to VDD-2, and then applies the first voltage. In order to allow the diode 230b to turn on, 200 mA (micro amps) flows toward the BGA ball 120 (current sourcing).

At this time, the current sourced from the test apparatus 310 flows in the direction having a low potential difference and in the direction of a device having a low resistance value. That is, the current flows in the direction in which the first diode 230b is turned on and flows into VDD-2 (i _2P ).

As such, the test device 310 may detect that the current flows in the VDD-2 direction, and thus, the first diode 230b in the specific input / output pad included in the second chip 110-2 may operate normally. .

Next, a test method of the second diode 235b provided in the input / output pad of the second chip 110-2 will be described.

The test apparatus 310 tests the second diode 235b by applying a voltage that is lower than the turn on voltage of the first diode 230b and lower than the voltage applied through the VSS-2. In this case, a voltage lower than VSS-2 may be applied to VSS-1.

Assuming that the turn-on voltage of the second diode 235b is 0.7V, the test apparatus 310 is VDD-1 and VDD to function as a current sink corresponding to the current value that turns on the second diode 235b. 0V is applied to -2, and a voltage lower than -0.7V is applied to VSS-1. At this time, -0.7V may be applied to the BGA ball 120.

At this time, the current sinked into the test apparatus 310 flows in the direction having a low potential difference and in the direction of a device having a low resistance value. That is, the current flows in the direction input to the test device 310 through the BGA ball 120 after turning on the second diode 235b from VSS-2 (i _2N ).

As such, the test apparatus 310 determines that the second diode 235b in the specific input / output pad provided in the second chip 110-2 operates normally by detecting that the current flows through the BGA ball 120. Can be.

In addition, according to the above-described process, the test apparatus 310 recognizes that the first diode 230b and the second diode 235b in the specific input / output pad included in the second chip are normal, so that the BGA ball 120 and the corresponding input / output pad are normal. It can be confirmed that wire bonding between the wires is normally completed.

4 is a circuit diagram illustrating a method of testing a connection state of a multichip package according to another exemplary embodiment of the present invention.

Referring to FIG. 3, a method of checking whether the wire bonding between the BGA ball 120 and the input / output pad is normal has been described. However, the above-described verification method of FIG. 3 is limitedly used only when one input / output pin (I / O pin) for input / output pads provided in a specific chip is not connected to a ground pin or a DSS power supply. That's how it can be. That is, if one or more input / output pads are connected to a ground pin or a DSS power supply, a conventional open / short test method for input / output pads of the chip cannot be used.

Hereinafter, an improved open / short test method that may be performed even when one or more input / output pads are connected to a ground pin or a DSS power source will be described with reference to FIG. 4. However, when the input / output pin of any one of the input / output pads provided in the second chip is connected to the ground pin (which can be confirmed in advance by data such as a product manual) and the VSS power supply of each input / output pad is 0V. It is assumed and described (shown as ground for convenience). Further, assume that these input / output pads are 115-11, 115-21, and 115-23 illustrated in FIG. In this case, since the input / output pads provided in the first chip can be tested by the method described with reference to FIG. 3, only the test procedure for the input / output pads of the second chip will be described. In addition, the illustrated BGA ball 120 is assumed as an example of a connecting member for electrically connecting a plurality of input and output pads, all the members for electrically connecting the plurality of input and output pads through wire bonding BGA ball ( 120).

Referring to FIG. 4, the test apparatus 310 checks whether an arbitrary input / output pad included in the BGA ball 120 and the second chip 110-2 is normally wire bonded, and thus, the first chip 110-1. Are connected to the VDD power source VDD-1, the BGA ball 120, and the VDD power source VDD-2 of the second chip 110-2. Here, since VDD-2 is common to each input / output pad included in the second chip 110-2, it may be briefly expressed as shown in FIG. 4.

The test apparatus 310 applies 3V to the VDD-1 and the BGA balls 120, respectively, and designates VDD-2 as the current sink stage. In this state, it is possible to check whether the wire bonding is normal by measuring the voltage applied to VDD-2 during current sinking by VDD-2.

Here, the magnitudes of the voltages applied to the VDD-1 and the BGA balls 120 may be changed as necessary, and the magnitude of the current to be sinked may be determined by wire bonding among the input / output pads provided in the second chip 110-2. The PMOS diode 230b of the input / output pad to be tested may be turned on or may be designated as a magnitude of a current higher than that. Assuming that the magnitude of the current that turns on the PMOS diode 230b is 20 mA, VDD-2 may be used as a current sinking terminal.

When measuring using the above-described voltage value and current value, if the wire bonding is normally connected (short state), the PMOS diode 230b is turned on and i _2P flows to VDD-2. At this time, the test device 310 detects a diode voltage (for example, 0.6 ~ 0.7V) corresponding to the turn-on voltage of the PMOS diode 230b at VDD-2.

However, when measuring using the above-described voltage and current values, if the wire bonding is not normally connected (open state), the current sinked to VDD-2 is generated at the input / output pads of the second chip 110-2. Will be done. That is, the N-MOS diode (235b), and P i-2 sikimyeo _2PG flowing toward VDD to turn on the P MOS diode (230c) from the i _2NP and ground pins sikimyeo turns on the MOS diode (230b) flows toward the VDD-2 is generated. In addition, i _2NG may be further generated to turn on the _NMOS diode 235c and flow toward the ground pin. As a result, the test device 310 is characterized in that the PMOS diode 230b at VDD-2 is significantly lower than the diode voltage (eg, 0.6 to 0.7V) corresponding to the turn-on voltage (eg, -0.35). V) is detected.

As described above, when one or more input / output pins of the input / output pads provided in any chip are connected to the ground pin, the normality of the wire bonding may be quickly determined by using the VDD power terminal as the current sinking terminal. In this case, the normality of the wire bonding may be determined as whether the voltage value measured through the VDD terminal is greater than the error value than the normal turn-on voltage of the PMOS diode. Here, the error value may be variously specified and applied according to statistical information by repetitive experiments, for example, may be specified as an arbitrary value corresponding to 0 to 100% of the normal turn-on voltage.

It is apparent that the above-described test method may be performed by an automated procedure according to a time series sequence by a software program or the like embedded in the test apparatus 310. The codes and code segments that make up the program can be easily deduced by a computer programmer in the field. The program is also stored in a computer readable media, and read and executed by a computer to implement the test method. The information storage medium includes a magnetic recording medium, an optical recording medium and a carrier wave medium.

Although the above has been described with reference to embodiments of the present invention, those skilled in the art may variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. And can be changed.

1 is a diagram illustrating a configuration of a general multi-chip package.

2 is a view showing a conventional electrostatic discharge protection circuit.

3 is a circuit diagram illustrating a method of testing a connection state of a multichip package according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating a method of testing a connection state of a multichip package according to another exemplary embodiment of the present disclosure.

Claims (11)

A test method of a test apparatus for a multi-chip package in which an input / output pad of a first chip and an input / output pad of a second chip are wire bonded through a connection member, Applying a first voltage to the VDD power terminal and the connection member of the first chip; And Sinking a current through the VDD power terminal of the second chip and measuring a voltage across the VDD power terminal of the second chip, And at least one I / O pin is connected to a ground pin or a VSS terminal in at least one of the plurality of input / output pads included in the second chip. The method of claim 1 When the voltage measured at the VDD power terminal of the second chip coincides within an error value with the turn-on voltage of the PMOS diode of the electrostatic discharge protection circuit provided in the input / output pad of the second chip. And a wire bonding between the connection member and the input / output pad is determined to be normal. The method of claim 2, And the first voltage has an arbitrary voltage value greater than the turn-on voltage of the PMOS diode. The method of claim 2 And the current sinked to the VDD power terminal of the second chip is at least greater than the current required to turn on the PMOS diode. The method of claim 2, And a current sinking through the VDD power terminal of the second chip flows in the direction of the connection member, the PMOS diode, and the VDD power terminal. A test apparatus for performing a test on a multi-chip package in which an input / output pad of a first chip and an input / output pad of a second chip are wire bonded through a connecting member, Means for applying a first voltage to the VDD power terminal and the connection member of the first chip, respectively; And Means for sinking current through the VDD power terminal of the second chip, thereby measuring a voltage across the VDD power terminal of the second chip, The I / O pin is connected to a ground pin or a VSS terminal in at least one of the plurality of input / output pads included in the second chip. The method of claim 6 When the voltage measured at the VDD power terminal of the second chip coincides within an error value with the turn-on voltage of the PMOS diode of the electrostatic discharge protection circuit provided in the input / output pad of the second chip. And determining that the wire bonding between the connecting member and the input / output pad is normal. The method of claim 7, wherein And the first voltage has an arbitrary voltage value greater than the turn-on voltage of the PMOS diode. The method of claim 7, And the current sinking into the VDD power terminal of the second chip is at least equal to a current value required to turn on the PMOS diode. The method of claim 7, wherein And a current sinking through the VDD power terminal of the second chip flows in the direction of the connection member, the PMOS diode, and the VDD power terminal. A recording medium on which a program of instructions that can be executed by a digital processing apparatus is tangibly implemented to perform the test method according to any one of claims 1 to 5, and records a program that can be read by the digital processing apparatus.

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