KR20070109434A - Method for open test and short test of semiconductor chip and semiconductor test system - Google Patents

Abstract

A method for performing open/short tests of a semiconductor chip and a semiconductor test system are provided to increase the number of semiconductors to be tested and to perform an open test and a short test simultaneously by merging leads to be short externally and adjusting voltages of data input/output pads inside the chip. A method for performing open and short tests of a semiconductor chip includes the steps of: dividing leads connected to data input/output pads into a plurality of groups(S310); connecting the group of leads to a tester by externally shorting leads to be electrically merged to a node(S320); and performing an open test and a short test for the individual group(S330).

Description

Method for open test and short test of semiconductor chip and Semiconductor test system {Method for open test and short test of semiconductor chip}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a conventional open test circuit.

2 is a conventional semiconductor test system.

3 is a flowchart illustrating a semiconductor test method according to an embodiment of the present invention.

4 is a flowchart illustrating a method of performing an open test and a short test according to an exemplary embodiment of the present invention.

5 is a structure of a semiconductor test system according to an embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a short between wire bondings in the semiconductor chip illustrated in FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test method and a semiconductor test system, and in particular, an open test and a short test for a larger number of leads using some pins provided by a tester. The present invention relates to a semiconductor test method and system for simultaneously performing a short test.

1 is a conventional open test circuit, and FIG. 2 is a conventional semiconductor test system.

A conventional open test method will be described with reference to FIG. 1. The open test is to check whether the lead 115 is normally connected or the wire bonding 113 between the pad 111 and the lead 115 is normally connected.

Currently commonly used open test uses a diode 117. All leads except the leads 115 to be tested of the semiconductor chip 110 are shorted, and a negative current is applied to the leads 115 to be tested. In the normal case, the diode 117 of the chip 110 is turned on, and the tester 130 measures the threshold voltage of the diode 117. However, when the lead 115 is not normally connected or the wire bonding 113 between the pad 111 and the lead 115 is not normally connected, the applied negative current does not flow and pile-up. As a result, a very large negative voltage value is measured in the tester 130. That is, when a negative current is applied to the lead 115, if the threshold voltage value of the diode 117 is measured, it is determined to be normally connected, and if a very large negative voltage value is measured, it is determined to be bad.

Referring to Figures 1 and 2 will be described with respect to the conventional short test (short test) method. The short test checks whether there is no electric short on the wire 113 in the semiconductor chip 110 and there is no electric short in the die.

All leads 213_1, 213_2, and 213_3 except for the leads 213_0 to be tested of the chip 210 apply a ground voltage Vss, and a voltage is applied to the leads 213_0 to be tested. In the normal case, since the diodes 117 of the semiconductor chips 210 and 110 are not turned on, only the current of the leakage current is measured in the testers 250 and 130. However, when there is a short circuit between the wire bonding 113, that is, when the short circuit 215 as shown in Figure 2 there is a current path (current path) that can flow the current much larger than the normal case is measured. That is, when a voltage is applied to the leads 213_0 and 115, it is determined that the current is normally connected when only a current of about leakage current is measured, and it is determined to be defective when a very large current value is measured.

Therefore, in the open test and the short test according to the related art, the pins of the tester should be connected to all the leads of the chip, so the number of semiconductor devices that can be inspected by one tester is very limited. In addition, the inconvenience of having to perform the open test and the short test separately.

An object of the present invention is to increase the number of semiconductor devices that can be inspected at one time, and to provide a semiconductor test method for simultaneously performing an open test and a short test.

Another object of the present invention is to provide a semiconductor test system for testing the semiconductor device using the semiconductor test method.

According to another aspect of the present invention, there is provided a semiconductor test method including: dividing leads connected to data input / output pads (DQs) into a plurality of groups; Shorting an external circuit chip to a tester such that leads divided into the groups are electrically merged into one node for each group; And performing an open test and a short test for each group.

The performing of the open test and the short test may maintain a voltage of one data input / output pad of the group in a first logic state and float the voltages of the remaining data input / output pads of the group. Maintaining a state; And measuring one of voltage and current in the tester to determine whether there is a failure, and repeating the above steps for all the data input / output pads of the group.

The performing of the open test and the short test may include maintaining the voltage of one of the data input / output pads of the group in a second logic state and floating the voltages of the remaining data input / output pads of the group. ) State; And determining whether there is a defect by measuring any one of voltage and current in the tester, and repeating the above steps for all the data input / output pads of the group.

The voltage of the data input / output pad is preferably maintained in a first logic state by using an output signal of a mode register set (MRS) and an on die termination (ODT) circuit in the semiconductor chip.

In the performing of the open test and the short test, when the voltage of the data input / output pad is in the first logic state, if one of the measured voltage and the measured current of the tester is less than or equal to a predetermined level, it is determined that the test is bad. .

The voltage of the data input / output pad is preferably maintained in a second logic state by using an output signal of a mode register set (MRS) and an on die termination (ODT) circuit in the semiconductor chip.

The performing of the open test and the short test may be determined to be bad when any one of the measured voltage and the measured current of the tester is higher than or equal to a predetermined level when the voltage of the data input / output pad is in the second logic state.

The dividing into a plurality of groups may be performed such that at least one lead belonging to another group is included among the leads belonging to the same group, and the leads divided into the groups may be sockets or boards. It is preferable to merge (merge) into one node for each group.

According to another aspect of the present invention, a semiconductor test system for testing a semiconductor device maintains a voltage of any one of a first logic state and a second logic state among data input / output pads (DQs). A semiconductor chip having a voltage control section capable of driving; A connection unit configured to divide the leads connected to the data input / output pads into a plurality of groups and to electrically merge the leads divided into the plurality of groups into one node for each group; And a tester configured to connect a tester pin to the node to perform an open test and a short test.

The voltage controller is configured to output the voltages of the respective data input / output pads (DQ) to the first logic state and the second logic state by using output signals of a mode register set (MRS) and on die termination (ODT) circuits in the semiconductor chip. It is characterized by maintaining any one of.

Preferably, the connection part is divided into groups such that at least one lead belonging to another group is included between each lead belonging to the same group.

When the voltage of the data input / output pad is the first logic state, the tester determines that one of the measured voltage and the measured current of the tester is less than or equal to a predetermined level. In the second logic state, if any one of the measured voltage and the measured current of the tester is a predetermined level or more, it is determined that the failure.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

5 is a structure of a semiconductor test system 500 according to an embodiment of the present invention.

Referring to FIG. 5, the semiconductor test system 500 may maintain a voltage of data input / output pads DQ0, DQ1, DQ2,... In one of a first logic state and a second logic state. A semiconductor chip 510 comprising 520, leads 515_0, 515_2, 515_4,... Are electrically merged to node N1 and leads 515_1, 515_3, 515_5,. .) Has a connection 550 configured to be electrically merged to an N2 node, i.e., a socket or a board, and connects a tester pin 571 to the N1 node to open and short test. And a tester 570 for connecting the tester pins 572 to the N2 node to perform the open test and the short test.

3 is a flowchart illustrating a semiconductor test method according to an embodiment of the present invention.

Referring to FIG. 3, the leads connected to the data input / output pad DQ are divided into a plurality of groups (S310), and the semiconductor chips are configured to electrically merge the leads into one node for each group. A short circuit outside the chip is connected to the tester at step S320. That is, leads are shorted to one node for each group, and the nodes are connected to pins of the tester, respectively. The tester performs a separate open test and a short test for each group (S330).

For example, when the test is divided into two groups as shown in FIG. 5, that is, the leads 515_0, 515_2, 515_4,... Are the first group, and the remaining leads 515_1, 515_3, 515_3,. The case of testing by dividing ..) into the second group will be explained. The leads 515_0, 515_2, 515_4,..., Belonging to the first group are shorted to the N1 node to be electrically merged in a socket or board 550 that is external to the semiconductor chip 510, so that the tester ( One pin 571 of 570 is connected, and the open test and the short test are performed in the tester 570. In addition, the leads 515_1, 515_3, 515_3, ... belonging to the second group are also shorted to the N2 node to be electrically merged in the socket or the board 550 outside the semiconductor chip 510, so that the other one of the tester 570 Is connected to pin 572, and the open test and the short test are performed by the tester 570.

Specifically, a method of performing the open test and the short test will be described with reference to FIGS. 4, 5, and 6.

4 is a flowchart illustrating a method of performing the open test and the short test according to an embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a short between wire bondings in the semiconductor chip illustrated in FIG. 5.

For example, a method of performing a test on the first group may be performed by maintaining the voltage of one data input / output pad DQ0 in a first logic state and remaining data input / output pads DQ1, DQ2, ... .) Is maintained in a floating state, and the second group applies the ground voltage Vss (S410). Hereinafter, in the present invention, the first logic state is a voltage high. The tester 570 measures the voltage or current at the tester pin 571 connected to the N1 node (S420) to determine whether the measured voltage or the measured current is below a predetermined level (S430).

In normal cases, the voltage or current of the data input / output pad DQ0 is measured at the tester pin 571 as it is. However, when the connection state of the lead 515_0 is poor, when the coupling between the lead 515_0 and the wire bonding is poor, when the coupling between the wire bonding and the data input / output pad DQ0 is poor, the measured voltage value or the current value is the same. Much lower than normal. In addition, when there is a short (Rs in FIG. 6) between the wire bonding connected to the lead 515_0 and the wire bonding connected to the lead 515_1, the N2 node is applied with a ground voltage Vss, and thus a current may flow. Since there is a current path, the measured voltage value or current value is much lower than in the normal case.

Therefore, it is determined whether the measured voltage or the measured current is below a predetermined level (S430). If the measured voltage is below the predetermined level, the semiconductor device is determined to be defective (S440). Maintaining the voltage of DQ2) in the first logic state and determining whether the semiconductor device is defective through the same steps as described above.

In addition, there may be a case in which a node having a voltage lower than the first logic state is not shorted, but may be shorted with the power supply voltage Vdd. ) Is maintained in a second logic state, and the remaining data input / output pads DQ2, DQ3,... Remain floating (S450). Hereinafter, in the present invention, the second logic state is a voltage low. As in the above method, the tester 570 measures the voltage or current at the tester pin 571 connected to the N1 node (S460) and determines whether the measured voltage or the measured current is equal to or greater than a predetermined level (S470).

In the normal case, since the voltage or current of the data input / output pad DQ0 is measured at the tester pin 571 as it is, the voltage value or the current value is not measured. However, when there is a short circuit with the power supply voltage Vdd, the measured voltage value or current value is much higher than the normal case since there is a current path through which current can flow.

Therefore, it is determined whether the measured voltage or the measured current is equal to or greater than a predetermined level (S470). If the predetermined level is greater than or equal to the predetermined level, the semiconductor device is determined to be defective (S480). Maintaining the voltage of DQ2) in the second logic state and determining whether the semiconductor device is defective through the same steps as described above.

When dividing into the plurality of groups, as shown in FIG. 5, it is preferable to divide a group so that at least one lead 515_1 belonging to another group is located between the lead 515_0 and the lead 515_2 belonging to the same group. By dividing the leads into groups as described above, the short between the wire bonds (Rs in FIG. 6) can also be checked. Therefore, although the leads to be tested may be tested in one group through the above steps, it is preferable to divide the leads into two or more groups.

According to an embodiment of the present invention, in order to maintain the voltage of the data input / output pad DQ in a first logic state or a second logic state, an output signal of an MRS generated in response to a mode resister set (MRS) in a semiconductor chip; ODT (On Die Termination) circuit is used. Referring to FIG. 5, the chip 510 removes the voltage of each data input / output pad DQ by using a plurality of On Die Termination (ODT) circuits in response to output signals of respective MRSs. And a voltage controller 520 capable of maintaining either one of the first logic state and the second logic state. For example, when the test starts, the MRS00 signal is enabled, and in response, the ODT circuit 521_0 is turned on to change the voltage of the data input / output pad DQ0 in the first logic state and the second logic state. Will be maintained as either. However, the method of using the MRS signal and the ODT circuit is only an embodiment, and as a result, the voltage of the data input / output pad may be maintained in either the first logic state or the second logic state as a result of using any other method. Test can be performed.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the case of testing by the semiconductor test method and the test system according to the present invention, the short of the chip may be shorted externally to allow the leads to be merged and the voltage of the data input / output pad DQ may be adjusted in the chip. It can be tested for more leads than the pins provided by the tester with the voltage control unit, and can be performed simultaneously without performing the open test and the short test separately. can do. Therefore, the number of semiconductor devices that can be inspected at one time is increased, and there is an advantage that the open test and the short test can be simultaneously performed.

Claims (14)

Dividing leads connected to the data input / output pads DQ into a plurality of groups; Shorting an external circuit chip to a tester such that leads divided into the groups are electrically merged into one node for each group; And And performing an open test and a short test for each group. The method of claim 1, wherein performing the open test and the short test comprises: Maintaining a voltage of one of the data input / output pads in the group in a first logic state and maintaining a voltage of the remaining data input / output pads in the group in a floating state; And And measuring one of a voltage and a current in the tester to determine whether there is a defect. And repeating the above steps for all the data input / output pads in the group. The method of claim 2, wherein performing the open test and the short test comprises: Maintaining a voltage of one of the data input / output pads in the group in a second logic state and maintaining a voltage of the remaining data input / output pads in the group in a floating state; And The tester further comprises the step of measuring any one of the voltage and current to determine whether or not, And repeating the above steps for all the data input / output pads in the group. The voltage of claim 2, wherein the voltage of the data input / output pad is And maintaining the first logic state by using an output signal of a mode register set (MRS) and an on die termination (ODT) circuit in the semiconductor chip. The method of claim 2, wherein performing the open test and the short test comprises: And when one of the measured voltage and the measured current of the tester is below a predetermined level when the voltage of the data input / output pad is in the first logic state, determining that the defect is bad. The method of claim 3, wherein the voltage of the data input and output pads, And a second logic state by using an output signal of a mode register set (MRS) and an on die termination (ODT) circuit in the semiconductor chip. The method of claim 3, wherein performing the open test and the short test comprises: And when one of the measured voltage and the measured current of the tester is higher than or equal to a predetermined level when the voltage of the data input / output pad is in the second logic state. The method of claim 1, wherein the dividing into a plurality of groups comprises: And dividing each lead belonging to the same group to include at least one lead belonging to another group. The semiconductor test method of claim 1, wherein the leads divided into groups are electrically merged into one node for each group by a socket or a board. A semiconductor chip having a voltage controller configured to maintain a voltage of any one of the data input / output pads DQ in one of a first logic state and a second logic state; A connection unit configured to divide the leads connected to the data input / output pads into a plurality of groups and to electrically merge the leads divided into the plurality of groups into one node for each group; And And a tester configured to connect a tester pin to the node to perform an open test and a short test. The method of claim 10, wherein the voltage control unit, The voltage of each data input / output pad DQ is maintained in one of a first logic state and a second logic state by using output signals of a mode register set (MRS) and on die termination (ODT) circuits in the semiconductor chip. A semiconductor test system, characterized in that. The method of claim 10, wherein the connection portion, And dividing the group into groups such that at least one lead belonging to another group is included among the leads belonging to the same group. The method of claim 10, wherein the tester, And when one of the measured voltage and the measured current of the tester is less than or equal to a predetermined level when the voltage of the data input / output pad is in the first logic state. The method of claim 10, wherein the tester, And when one of the measured voltage and the measured current of the tester is higher than or equal to a predetermined level when the voltage of the data input / output pad is in the second logic state, the semiconductor test system.

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