JP2006302993A - Method of evaluating probe card connection and apparatus therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and apparatus for evaluating a connection between terminals of a plurality of semiconductor devices and bumps of a probe card to remove difficulty in realizing wafer level burn-in. <P>SOLUTION: In evaluating a probe card connection, the bumps of the probe card are brought into contact with the terminals of the plurality of semiconductor devices which are arranged in a matrix form on a wafer, in such a manner that the probe card may be connected in parallel with each terminal arranged in the row direction and in the column direction of the matrix. A high-frequency signal is applied from one of the row direction and the column direction, and the high-frequency signal is measured with the other. By comparing each measured value with a reference value, a connection is evaluated between the terminals of the semiconductor devices and the bumps of the probe card. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for determining the quality of connection between terminals of a plurality of semiconductor devices and bumps of a probe card when performing a screening process by burn-in for the purpose of improving the reliability of a semiconductor in a wafer state.

  Conventionally, as a screening process to increase the reliability of semiconductors, a power supply voltage of a rated or slight overvoltage is applied to the semiconductor, and a signal close to actual operation is applied to each signal input terminal while maintaining a high temperature of about 125 ° C. Time to burn in is done. Conventionally, burn-in was carried out in the form of a semiconductor housed in a package, but the semiconductor housed in the package has a signal line lead-out terminal, and when burn-in is performed, it is inserted into a socket and connected. The burn-in process could be easily performed without confirming the above.

  On the other hand, for semiconductors such as recent bare chips and CSPs, batch burn-in in a wafer state has been proposed. In order to realize collective burn-in to a semiconductor in a wafer state, a signal line is connected to a bonding pad, which is a lead electrode of a plurality of semiconductor chips formed on the wafer, and a signal is applied. Usually 200 to 1000 semiconductor chips are formed on a wafer, and each semiconductor chip has about 20 to 50 bonding pads, which are micro-sized electrodes of 80 μm. It is necessary to accurately connect the signal lines with a total of 4000 to 50000 points. That is, in order to realize burn-in to a semiconductor chip in a wafer state, it is necessary to connect a large number of signal lines, and it is desired to perform burn-in after confirming that the signal line connection is correctly performed. A technique for performing batch connection to a wafer is described in Patent Document 1 and Patent Document 2.

  An overview of batch connection to a wafer and a method for confirming signal line connection will be described below. FIG. 7 shows the structure of the wafer. In FIG. 7, reference numeral 11 denotes a wafer, and semiconductor chips are arranged on the wafer corresponding to 21 to 30 columns and 31 to 38 rows as shown in the figure. Each semiconductor chip is provided with a large number of bonding pads as electrodes drawn out to the outside.

  Next, a probe card for making connections necessary for burn-in to the wafer 11 will be described with reference to FIG. In FIG. 8, a large number of semiconductor chips are formed in columns 21 to 30 and rows 31 to 38 on the wafer 11 as shown in FIG. Reference numeral 12 denotes a probe card, which is composed of bumps to be electrically connected corresponding to bonding pads of all the semiconductor chips formed on the wafer 11, and power lines, control lines, and signal lines drawn from the bumps. 11 is used under pressure. Although the connection method of the power supply line, the control line, and the signal line may be slightly different depending on the type of device such as a memory or a logic, an example of a memory device will be described here. The important point at this time is not to draw out the power supply line, the control line, and the signal line independently for each semiconductor chip on the wafer, but for each row of semiconductor chips arranged in a circle as shown in FIG. In general, power lines, control lines, and signal lines are connected and drawn in parallel to a plurality of semiconductor chips for each row. Specifically, 41 power / control lines for 21 columns, 42 power / control lines for 22 columns, 43 power / control lines for 23 columns, 44 power / control lines for 24 columns Lines, 45 power / control lines for 25 columns, 46 power / control lines for 26 columns, 47 power / control lines for 27 columns, 48 power / control lines for 28 columns, 49 power / control lines are formed on the probe card 12 for 29 columns and 50 power / control lines for 30 columns. Also, 51 signal lines for 31 rows, 52 signal lines for 32 rows, 53 signal lines for 33 rows, 54 signal lines for 34 rows, 55 signals for 35 rows The probe card 12 includes 56 signal lines for the 36 rows, 57 signal lines for the 37 rows, and 58 signal lines for the 38 rows.

  In this example, the power supply / control lines 41 to 50 include the power supply line and the read control line OE among the signal lines that drive the memory, and the signal lines 51 to 58 include the signal lines that drive the memory. Among them, address lines A0 to A7, data lines D0 to D3, and a write control line WE are included. With such a signal line configuration, writing is performed simultaneously on each semiconductor chip in each row such as 31 and 32, and at the time of reading, reading is performed sequentially on a chip-by-chip basis while controlling the read control line OE on the semiconductor chip on each row such as 31 and 32. Check the contents of the semiconductor chip.

  FIG. 9 shows a specific example. FIG. 9 shows connections to the semiconductor chips 61, 62, 63, 64 shown in FIG. 8, and is included in the power / control line 44, the power / control line 45, the power / control line 46, and the power / control line 47. This shows a connection method of the power supply line, the read control line OE, the address lines A0 to A7, the data lines D0 to D3, and the write control line WE included in the signal line 51. That is, the address lines A0 to A7, the data lines D0 to D3, and the write control line WE are drawn in parallel from the bonding pads of the semiconductor chips 61, 62, 63, and 64, and the power lines are connected to the power supply bonding pads of the semiconductor chip 61. The control line 44 of the read control line OE from the OE bonding pad, the power supply line from the power supply bonding pad of the semiconductor chip 62, the control line 45 of the read control line OE from the OE bonding pad, the power supply line from the power supply bonding pad of the semiconductor chip 63, The control line 46 of the read control line OE is drawn from the OE bonding pad, the power supply line is drawn from the power supply bonding pad of the semiconductor chip 64, and the control line 47 of the read control line OE is drawn from the OE bonding pad. When reading, first, the read control line OE of the control line 44 is turned on to read the contents of the semiconductor chip 61 using the signal line 51, and secondly, the read control line OE of the control line 45 is turned on to set the contents of the semiconductor chip 62 The contents of the semiconductor chip are sequentially confirmed by reading using the signal line 51.

  As a means for confirming the signal line connection between the wafer and the contactor, there is a method for confirming the state of the signal line in a DC manner as shown in FIG. As shown in FIG. 8, a large number of semiconductor chips are formed in columns 21 to 30 and rows 31 to 38 on the wafer 11, and the probe card 12 has power / control lines 41 to 50 and signal lines 51 to 58. Has been placed. Reference numeral 70 denotes a power source, which can generate DC currents having different positive and negative polarities of about 100 μA and apply them to signal lines or control lines. However, a limit circuit is built in that does not generate positive or negative voltage exceeding the limit voltage of about 5V so as not to destroy the semiconductor chip on the wafer. Reference numeral 71 denotes a digital vol, which is connected to the signal line or the control line and measures the DC voltage of the signal line or the control line.

  The control lines 41 to 50 and the signal lines 51 to 58 drawn out from the probe card as a means for confirming the connection of the signal line or the control line to the semiconductor chip are connected to the power supply 70 and the digital vol 71 through the switch 72, While sequentially switching the switch 72, the connection between the wafer 11 and the probe card 12 is confirmed.

  The details of the connection confirmation means are shown below using FIG. 11 as an example of the semiconductor chip 61, the semiconductor chip 62, the semiconductor chip 63, and the semiconductor chip 64 arranged in 31 rows in FIG.

  In FIG. 11, reference numeral 51 denotes a signal line provided on the probe card, which is drawn out of the probe card and connected to each bonding pad of the semiconductor chips 61, 62, 63, 64 formed on the wafer 11 through bumps. Has been. Reference numeral 70 denotes a power supply, which can generate DC currents having positive and negative polarities of about 100 μA and apply them to the signal line 51. However, a limit circuit is built in that does not generate positive or negative voltage exceeding the limit voltage of about 5V so as not to destroy the semiconductor chip on the wafer. Reference numeral 71 denotes a digital vol, which is connected to the signal line 51 and measures the DC voltage of the signal line 51.

  On the other hand, input protection diodes 81, 82, 83, and 84 are incorporated in the semiconductor chip corresponding to the bonding pads provided in the semiconductor chips 61, 62, 63, and 64, respectively.

  Details thereof will be described with reference to FIG. That is, in FIG. 12, reference numeral 61 denotes one semiconductor chip, which provides a terminal 85 for supplying an input signal for the address signal A1, a terminal 86 for supplying an input signal for the address signal A2, a terminal 87 for supplying an input signal for the control signal CS, and a power supply VCC. Terminals by bonding pads such as a terminal 88 and a terminal 89 for providing a ground VSS are arranged. A diode 93 is arranged between the input FET 90 and the power supply terminal 88 and a diode 96 is arranged between the ground terminal 89 and the terminal 85 corresponding to the input signal A1. A diode 94 is disposed between the input FET 91 and the power supply terminal 88 and a diode 97 is disposed between the ground terminal 89 and the terminal 86 that provides the input signal A2. A diode 95 is disposed between the input FET 92 and the power supply terminal 88 and a diode 98 is disposed between the ground terminal 89 and the terminal 87 for providing the input signal CS.

  The operation will be described below. As mentioned earlier, when a positive voltage is applied to the semiconductor chip terminal as measured from the outside, the input protection diode is reverse-biased, indicating a high resistance, and when a negative voltage is applied, a diode is formed by the input protection diode. Show the characteristics. Therefore, when a positive current of 100 μA is applied to the signal line 51 from the power supply 70, no current flows when the semiconductor chips 61, 62, 63, 64 are normally connected to the signal line. The position becomes a positive limit voltage, and the potential can be read by the Digibol 71. When one of the semiconductors 61, 62, 63, 64 is damaged or the contact is not performed normally and a short circuit occurs between adjacent bumps, current leakage occurs and a voltage lower than the limit voltage is observed. The

Next, when a negative current of 100 μA is applied to the signal line 51 from the power supply 70, when the semiconductor chips 61, 62, 63, 64 are normally connected to the signal line, the protection diodes built in the respective semiconductor chips are applied. A current flows, and the DC potential of the signal line 51 becomes a voltage of about −0.3 V, and the potential can be read by the Digibol 71. When one of the semiconductor chips 61, 62, 63, 64 is damaged or the contact is not performed normally and a short circuit occurs between adjacent bumps, current leakage occurs and a low voltage of less than -0.3V is generated. Observed. In addition, when contact is not performed normally and connection to all the bumps cannot be made, current does not flow, the DC potential of the signal line 51 becomes a negative limit voltage, and the potential can be read by the Digibol 71.
Patent No.2922486 Patent No. 2925964

  Since the signal line connection to the wafer is performed in parallel for a plurality of semiconductor chips for each column and for each row, the method for confirming the signal line state in a DC manner described in the background art described above is one of the probe card and the semiconductor chip. Even if the connection of the parts is incomplete, the problem is that it cannot be detected.

  In other words, when applying positive and negative DC currents, which is a conventional method, when one of the semiconductor chips 61, 62, 63, 64 is damaged or contact is not performed normally, a short circuit occurs between adjacent bumps. Or, when contact is not performed normally and all bumps of the semiconductor chips 61, 62, 63, 64 cannot be connected, an abnormality is found, but one of the semiconductor chips 61, 62, 63, 64 is open. When it becomes, abnormality is not found. That is, it is difficult to confirm the connection of all the semiconductor chips connected to the signal line by the confirmation by the direct current, which has hindered its practical use.

  The present invention provides a method and apparatus capable of determining whether or not the connection between the terminals of a plurality of semiconductor devices and the bumps of the probe card is to solve the obstacle in realizing burn-in in such a wafer state. With the goal.

  In order to achieve the above object, a probe card connection pass / fail determination method according to the present invention comprises contacting the bumps of a probe card with the terminals of a plurality of semiconductor devices arranged in a matrix on a wafer, and the row direction of the matrix and The semiconductor devices are connected in parallel in each of the column directions, a high frequency signal is applied from one of the row direction and the column direction, a high frequency signal is measured on the other side, and the measured value is compared with a reference value. It is characterized in that the quality of the connection between the terminal and the bump of the probe card is determined. In other words, the semiconductor device has a capacitance between the wirings (for example, between the power supply line / control line and each signal line), so that a high frequency signal applied to the power supply line / control line is signaled through this capacitance. Measure the high-frequency signal transmitted to the line. With such a configuration, it is possible to determine whether the connection between the terminal of the semiconductor device and the bump of the probe card is good or bad.

  Here, the reference value may be set by applying a high frequency signal from a predetermined terminal of the semiconductor device in advance and measuring the high frequency signal at another terminal. As a result, the high-frequency signal is measured for each semiconductor device, and when the measured value is not within a certain range from the reference value, it is understood that the semiconductor device is not normally connected.

  Further, the reference value may be set based on an average value of measured values measured for all semiconductor devices arranged on the wafer. As a result, the same connection confirmation as described above can be performed without setting a reference value in advance. That is, the high-frequency signal is measured for all the semiconductor devices, and it can be determined that the semiconductor devices that are not within a certain range from the average value of the measured values are not normally connected.

  The present invention can be realized not only as such a probe card connection quality determination method but also as a probe card connection quality determination device using characteristic steps included in such a probe card connection quality determination method. It can also be realized as.

  According to the probe card connection quality determination method of the present invention, it is possible to perform reliable burn-in after determining the quality of connection between the terminals of a plurality of semiconductor devices and the bumps of the probe card.

  FIG. 1 shows an embodiment according to the present invention. As shown in FIG. 8, a large number of semiconductor chips are formed in columns 21 to 30 and rows 31 to 38 on the wafer 11, and control lines 41 to 50 and signal lines 51 to 58 are arranged on the probe card 12. ing. Reference numeral 73 denotes a high-frequency signal generator that supplies a high-frequency signal necessary for measurement. Reference numeral 75 denotes a switch which can supply a high frequency signal output from the high frequency signal generator to the switching power source / control line 41, the power source / control line 42, and the like. 74 is a level meter, which can measure the high-frequency signal by switching and connecting the output of the signal line. A switch 76 can supply a high-frequency signal output from the signal line 51, the signal line 52, and the like to the switching level meter 74. Hereinafter, a device including the high-frequency signal generator 73, the switch 75, the level meter 74, and the switch 76 may be referred to as a connection confirmation device.

  The details of the connection confirmation means are shown below using FIG. 2 as an example of the semiconductor chip 61, the semiconductor chip 62, the semiconductor chip 63, and the semiconductor chip 64 arranged in 31 rows in FIG.

  In FIG. 2, 61, 62, 63 and 64 are semiconductor chips formed on the wafer 11. Reference numeral 73 denotes a high-frequency signal generator that supplies a high-frequency signal necessary for measurement. Reference numeral 75 denotes a switch, which can supply a high-frequency signal output from the high-frequency signal generator to the switching power source / control line. 74 is a level meter that can measure a high-frequency signal on a signal line. Now, one bonding pad which is a terminal of the semiconductor chips 61, 62, 63 and 64 in FIG. 2 will be described. 51 is a signal line provided in the probe card, and is connected to these bonding pads through bumps. It is pulled out of the card.

  Corresponding to these bonding pads provided on the semiconductor chips 61, 62, 63, 64, the capacitance between the power / control line and the signal line shown in 100, 101, 102, 103, and 104, 105, 106, respectively. , 107, the capacitance between the power / signal line and the ground is built in the semiconductor chip.

  Details thereof will be described with reference to FIG. As shown in FIG. 3, each of the semiconductor chips 61, 62, 63, 64 has a capacitance between the terminal of the power / control line and the terminal of the signal line. That is, in FIG. 3, signal line terminals 85, 86, 87 are connected to input FETs 90, 91, 92. At the same time, the signal line terminals 85, 86, and 87 are connected to the VCC terminal 88 and the VSS terminal 89 by protective diodes 93, 94, 95, 96, 97, and 98. Due to the presence of protective diodes 93, 94, 95, 96, 97, 98, the signal line terminals 85, 86 have capacitances 108, 109, 110, 111, 112, 113 with respect to the VCC terminal and VSS terminal, respectively. Yes. The signal line terminals 85 and 86 have capacitances 114 and 115, respectively, with respect to the control line terminal 87.

  FIG. 4 is a flowchart showing a connection confirmation operation according to the present invention. Hereinafter, the operation when a high-frequency signal is applied to the control line will be described with reference to FIGS.

  First, when the switch 75 is switched (S1) and a high frequency signal is applied to the control line 47 (S2), the high frequency signal is applied to the control bonding pad of each chip belonging to the column via the bump. Capacitance determined by the structure and wiring in the chip exists between the bonding pad for control of each chip and each signal such as address and data, and a high frequency signal is generated in the signal bonding pad through this capacitance 100. . This high frequency signal appears on the signal line 51 through a bump which is a connection point with the probe card from the bonding pad. On the other hand, when the bumps that are the connection points between the bonding pads and the probe card are not connected, the signal line 51 does not have a high frequency signal.

  That is, by measuring this high frequency signal (S3), the connection between each bonding pad and the bump can be confirmed. For example, when a high frequency signal of 1V is applied to the control line 47, if the measured value of the high frequency signal appearing on the signal line 51 is within a certain range from the reference value (for example, 10 mV), it is confirmed that the connection is normally made. It can be confirmed (Yes in S4 → S5), and conversely, if it is not within a certain range from the reference value, it can be confirmed that it is not normally connected (No → S6 in S4).

  The above operation is repeated up to the last column by switching the switch 75 (No in S7 → S1). When the connection confirmation for the final column is completed (Yes in S7), the switch 76 is switched to perform the same connection confirmation for the signal line 52 in the next row (No in S8 → S9 → S1). When the connection confirmation is completed for the last row (Yes in S9), the connection confirmation for the wafer 11 is terminated.

  FIG. 5 is a flowchart showing the setting operation of the reference value. That is, since the high frequency signal appearing on the signal line 51 depends on the capacitance determined by the structure and wiring in the semiconductor chip, the value to be adopted as the reference value also differs depending on the type of the wafer 11. Therefore, when checking the connection of another type of wafer 11, first, a semiconductor chip in which bonding pads and bumps are normally connected is selected (S11), and a measurement value of the high-frequency signal is obtained for the semiconductor chip ( S12), this measured value is set as a reference value (S13).

Of course, the reference value setting method is not limited to this.
FIG. 6 is a flowchart showing another setting operation of the reference value. That is, the measurement value of the high-frequency signal is obtained for all the semiconductor chips arranged on the wafer (S21 to S26), the average value of the measurement values is calculated (S27), and the calculated value may be used as the reference value. (S28). The average value here may be a value that occupies most of the values measured for all the semiconductor chips, and may not be an accurate average value.

  Thereby, it is determined that the semiconductor chip whose measured value of the high frequency signal appearing on the signal line 51 is within a certain range from the reference value (for example, 10 mV) is normally connected (Yes in S29 → S30), Conversely, it is possible to determine that a semiconductor chip that is not within a certain range from the reference value is not normally connected (No in S29 to S31). There are three cases that can be determined as not being normally connected. That is, (1) in the case where the probe card and the wafer are open and (2) in the case where there is an abnormality in the wiring open in the wafer, the measured value is much smaller than the reference value, and (3) In the case of causing a short circuit with the ground, the measured value is 0V.

  As described above, in the conventional method shown in FIG. 10, when any of the semiconductor chips 61, 62, 63, 64 is opened, no abnormality is found. On the other hand, in the method according to the present invention shown in FIG. 1, since the connection between the probe card and the bonding pad on the wafer can be independently confirmed, any one of the semiconductor chips 61, 62, 63, 64 is opened. Even when the error occurs, the abnormality can be detected, and the signal line connection can be easily and reliably confirmed. Since it is essential to connect a large number of bumps and bonding pads in order to burn-in in the wafer state, signal line connection confirmation technology is important, and the present invention can ensure the reliability of wafer connection. Thus, the feasibility of the burn-in apparatus in the wafer state can be improved.

  In addition, as shown in FIG. 2, the signal lines are arranged horizontally, but the power supply is arranged vertically independently for each column, and high frequency signals are sequentially applied to one vertical power supply. Therefore, it is possible to confirm only the connection of one chip in the horizontal direction.

  In addition, when measuring a high-frequency signal output to a signal line using a level meter, there are cases where the measurement is difficult because the high-frequency signal is weak. In such a case, a weaker high-frequency signal can be easily measured by selecting and measuring only the frequency component of the high-frequency signal generated by the high-frequency signal generator. Specifically, there are a method of applying a high frequency signal to the level meter 74 through a narrow band filter and a method of using a lock-in amplifier type level meter.

  In addition, the technology for confirming whether or not the measured value of the high-frequency signal appearing on the signal line 51 is within a certain range from the reference value is not mentioned here, but it is automated by incorporating software into the connection confirmation device. It is preferable to do this.

  Here, a high-frequency signal is applied to the control line 47 and the high-frequency signal output from the signal line 51 is measured, but the high-frequency signal application side and the measurement side may be reversed. That is, as long as the high frequency signal is applied to the wiring connected to one of the rows and columns of the matrix and the high frequency signal output from the other wiring is measured, the same effect as described above can be obtained. Can do.

  Although the semiconductor chip has been described as an example here, the form of the semiconductor is not limited to the chip form. That is, as long as it is a technique for determining the quality of connection between the terminals of a plurality of semiconductor devices arranged on a matrix on a wafer and the bumps of a probe card, it is included in the scope of application of the present invention.

  The probe card connection confirmation method according to the present invention can be applied to a burn-in apparatus or the like that needs to independently confirm the connection between the terminals of a plurality of semiconductor devices and the bumps of the probe card.

Connection confirmation diagram according to the present invention Detailed diagram of connection verification according to the present invention Diagram of semiconductor chip in connection confirmation according to the present invention The flowchart which shows the connection confirmation operation | movement by this invention Flow chart showing reference value setting operation Flow chart showing another setting operation of the reference value Diagram showing wafer structure Diagram showing connection between wafer and probe card Diagram showing how to draw signal lines DC connection confirmation diagram Detailed diagram of DC connection confirmation Diagram of semiconductor chip in connection confirmation by DC

Explanation of symbols

11 wafers
12 Probe card
21-30 wafer rows
31-38 wafer rows
41-50 power / control line
51-58 signal line
61-64 semiconductor chip
70 Power supply
71 Digibor
72 switch
73 high frequency signal generator
74 level meter
75 switch
76 switch
81 to 84 Input protection diode built in semiconductor chip
85 to 87 terminals
88 VCC pin
89 VSS pin
90-92 Input FET built in semiconductor chip
93 to 95 Input protection diode built in semiconductor chip
96-98 Input protection diode built in semiconductor chip
100 to 103 Capacitance between control line and signal line built in semiconductor chip
104 to 107 Capacitance between signal line built in semiconductor chip and ground
108-110 Capacitance between power line and signal line built in semiconductor chip
111 to 113 Capacitance between signal line and ground built in semiconductor chip
114-115 Capacitance between signal line and control line built in semiconductor chip

Claims (4)

  A bump of a probe card is brought into contact with terminals of a plurality of semiconductor devices arranged in a matrix on the wafer and connected in parallel in each of the row direction and the column direction of the matrix, and either the row direction or the column direction is connected. A high-frequency signal is applied from one side and a high-frequency signal is measured on the other side, and the measurement value is compared with a reference value to determine whether the connection between the terminal of the semiconductor device and the bump of the probe card is good or bad. To determine whether or not to connect a probe card.   2. The probe card connection quality determination method according to claim 1, wherein the reference value is set by applying a high-frequency signal from a predetermined terminal of the semiconductor device in advance and measuring the high-frequency signal at another terminal.   2. The probe card connection quality determination method according to claim 1, wherein the reference value is set based on an average value of measured values measured for all semiconductor devices arranged on the wafer.   A probe card that contacts bumps of the terminals of a plurality of semiconductor devices arranged in a matrix on the wafer and connects in parallel in each of the row direction and the column direction of the matrix, and either the row direction or the column direction A high-frequency signal applying means for applying a high-frequency signal from one side, a measuring means for measuring a high-frequency signal on the other side, comparing the measured value with a reference value, and connecting the terminals of the semiconductor device and the bumps of the probe card A probe card connection pass / fail judgment device comprising: judgment means for judging pass / fail.

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