JP2006210539A - Semiconductor device - Google Patents

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JP2006210539A
JP2006210539A JP2005019026A JP2005019026A JP2006210539A JP 2006210539 A JP2006210539 A JP 2006210539A JP 2005019026 A JP2005019026 A JP 2005019026A JP 2005019026 A JP2005019026 A JP 2005019026A JP 2006210539 A JP2006210539 A JP 2006210539A
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element region
electrode
semiconductor device
diode
semiconductor
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JP4959139B2 (en
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Masashi Yura
昌士 由良
Masahiro Iwamura
将弘 岩村
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Hitachi Ltd
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<P>PROBLEM TO BE SOLVED: To provide a reliable semiconductor device by surely checking the insulation property of a separation insulation film 3 of a semiconductor substrate 10 having the SOI structure, etc. <P>SOLUTION: The semiconductor substrate 10 contains an element region 1 and a non-element region 2 which are electrically separated by the separation insulation film 3. On the semiconductor substrate 10, an electrode 41 connected to the element region 1 and an electrode 42 connected to the non-element region 2 are arranged. Between these electrodes, diodes 7 and 8 are arranged. The diodes 7 and 8 are connected in antiparallel between the electrodes 41 and 42. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は誘電体分離半導体装置に係り、特に、信頼性の高い誘電体分離半導体装置に関する。   The present invention relates to a dielectric isolated semiconductor device, and more particularly to a highly reliable dielectric isolated semiconductor device.

ＳＯＩ（Silicon-On-Insulator）ウエハ等を用いた誘電体分離半導体装置では、底面および側面を分離絶縁膜で囲まれた島状の素子領域が複数存在し、各々の素子領域部の間には素子を有さない半導体領域（非素子領域部）が存在している。   In a dielectric isolation semiconductor device using an SOI (Silicon-On-Insulator) wafer or the like, there are a plurality of island-shaped element regions surrounded by an isolation insulating film on the bottom surface and side surfaces, and between each element region portion. There is a semiconductor region (non-element region portion) having no element.

このような誘電体分離半導体装置では、特に、各素子領域部を分離する絶縁膜の信頼性が重要である。分離絶縁膜が欠損（ピンホール等）していたり、薄かったりして、抵抗的あるいは容量的に結合されてしまうと、動作している素子領域部から発せられるノイズが、非素子領域部に乗り、間接的にあるいは直接的に他の素子領域部に悪影響を及ぼし、半導体装置が誤動作して最悪の場合、それを組んだシステムが破壊に至る危険性がある。   In such a dielectric isolation semiconductor device, in particular, the reliability of the insulating film that isolates each element region is important. If the isolation insulating film is deficient (pinholes, etc.) or is thin and is coupled resistively or capacitively, noise generated from the operating element region will be applied to the non-element region. If the semiconductor device malfunctions in the worst case because it adversely affects other element regions indirectly or directly, there is a risk that the system in which the semiconductor device is assembled will be destroyed.

分離絶縁膜の信頼性を向上させるには、プロセスのクリーン度の向上や絶縁膜厚の増加などが必要となる。プロセスのクリーン度向上は設備投資の増加，管理体制の強化が必要となり、製品の価格向上につながる。また、絶縁膜厚の増加は新たなプロセス開発が必要となり、開発には時間と費用を要する。   In order to improve the reliability of the isolation insulating film, it is necessary to improve the cleanliness of the process and increase the insulating film thickness. Increasing the cleanliness of the process requires an increase in capital investment and strengthening of the management system, leading to an increase in product prices. In addition, an increase in the insulation film thickness requires a new process development, which requires time and cost.

そのため半導体チップ完成段階における分離絶縁膜のチェックが重要であり、素子領域部に形成された電極と非素子領域部に形成された電極との間の電気特性のチェックにより十分な絶縁性を確認することが必要となる。このようにすると半導体チップを実装する際に、非素子領域部の電極の電位を何らかの電位に固定する必要が生ずる。非素子領域部の電極の電位を固定する具体的手段としては、例えばワイヤボンディングによって素子領域部の大地電位（ＧＮＤ）などの適当な電位に接続する方法がある。非素子領域は半導体装置の機能を分担していないため、仮にこのワイヤの接続が不良であっても機能試験等で発見し選別することは困難である。このように、非素子領域部の電位が製品完成段階にて確実に電位固定なされたかどうかのチェックは、半導体装置の電気特性チェックでは確認することができないため、独立のチェック項目を実施する必要がある。   Therefore, it is important to check the isolation insulating film at the completion stage of the semiconductor chip, and sufficient insulation is confirmed by checking the electrical characteristics between the electrode formed in the element region and the electrode formed in the non-element region. It will be necessary. If it does in this way, when mounting a semiconductor chip, it will be necessary to fix the potential of the electrode of a non-element field part to some potential. As a specific means for fixing the potential of the electrode in the non-element region, there is a method of connecting to an appropriate potential such as a ground potential (GND) in the element region by wire bonding, for example. Since the non-element region does not share the function of the semiconductor device, it is difficult to find and select it by a function test or the like even if this wire connection is poor. As described above, since it is not possible to check whether the potential of the non-element region portion is fixed at the product completion stage by checking the electrical characteristics of the semiconductor device, it is necessary to carry out independent check items. is there.

例えば、特開２００４−２４１５７１号公報には、素子領域部と非素子領域部とに電極を設けた構造が開示されている。しかし、非素子領域部の電位を固定する工夫をしないとＩＣが誤動作するおそれがある。また、非素子領域部の電位を固定するために、非素子領域部のＩＣ上パッドをワイヤボンディングなどによってＧＮＤ等のある固定電位となる電極に接続したとしても、製品完成段階にてその接続ワイヤに不具合がないかチェックすることは難しい。   For example, Japanese Patent Application Laid-Open No. 2004-241571 discloses a structure in which electrodes are provided in an element region portion and a non-element region portion. However, the IC may malfunction if the device for fixing the potential of the non-element region is not devised. Further, in order to fix the potential of the non-element region portion, even if the pad on the IC in the non-element region portion is connected to an electrode having a certain fixed potential such as GND by wire bonding or the like, the connection wire at the stage of product completion It is difficult to check if there are any defects.

特開２００４−３４９４２０号公報には、フッ酸系のエッチング液により形成された
ＳＯＩ層のエッチピットを観察することにより、ＳＯＩ層の欠陥評価を行う方法が開示されている。また、特開２００３−３４７５２８号公報には、フォトリソグラフィによって一部のＳＯＩ層をエッチング除去し、ＳＯＩ層を挟む上下の各半導体層に電極を形成（スパッタリング）したサンプルを作製し、電極間に電圧を印加してＳＯＩ層の耐圧を評価する方法が開示されている。しかし、いずれの技術も製品完成段階での評価ではない。ロット抜き取り検査となり、全数検査は不可能である。 Japanese Patent Application Laid-Open No. 2004-349420 discloses a method for evaluating defects in an SOI layer by observing etch pits in the SOI layer formed with a hydrofluoric acid-based etching solution. Japanese Patent Laid-Open No. 2003-347528 discloses a sample in which part of an SOI layer is removed by photolithography and electrodes are formed (sputtered) on upper and lower semiconductor layers sandwiching the SOI layer. A method for evaluating the withstand voltage of an SOI layer by applying a voltage is disclosed. However, neither technology is evaluated at the product completion stage. Lot sampling inspection is possible and 100% inspection is impossible.

特開２００４−２４１５７１号公報JP 2004-241571 A 特開２００４−３４９４２０号公報JP 2004-349420 A 特開２００３−３４７５２８号公報JP 2003-347528 A

ＳＯＩ構造等の誘電体分離型半導体基板を用いた場合において、分離絶縁膜の信頼性を確認するには、素子領域部と非素子領域部とに独立に電極を設け、その間の絶縁性を電気的に確認する。しかし、その後非素子領域部の電位が確実に固定されていないと、ノイズの影響による誤動作，破壊の危険性が高くなる。   In the case of using a dielectric-separated semiconductor substrate such as an SOI structure, in order to confirm the reliability of the isolation insulating film, electrodes are provided independently in the element region portion and the non-element region portion, and the insulation between them is electrically Confirm. However, if the potential of the non-element region is not securely fixed thereafter, the risk of malfunction and destruction due to the influence of noise increases.

上記課題を解決するため、本発明の代表的な半導体装置の一は、半導体素子が形成された素子領域と、素子領域とは電気的に絶縁された非素子領域と、素子領域と非素子領域とを電気的に絶縁する分離絶縁膜と、素子領域に接続される第１電極と、非素子領域に接続される第２電極と、第１電極と第２電極との間に互いに逆並列に接続された第１ダイオード及び第２ダイオードとを備えている。   In order to solve the above problems, a representative semiconductor device of the present invention includes an element region in which a semiconductor element is formed, a non-element region that is electrically insulated from the element region, and an element region and a non-element region. An isolation insulating film that electrically insulates the first electrode, the first electrode connected to the element region, the second electrode connected to the non-element region, and the first electrode and the second electrode in reverse parallel to each other A first diode and a second diode are connected.

また、本発明の他の代表的な半導体装置の一は、半導体素子が形成された素子領域と、素子領域とは電気的に絶縁された非素子領域と、素子領域と非素子領域とを電気的に絶縁する分離絶縁膜と、素子領域に接続される第１電極と、非素子領域に接続される第２電極と、第１電極と第２電極との間に互いに逆直列に接続された第１ダイオード及び第２ダイオードとを備えている。   In another exemplary semiconductor device of the present invention, an element region in which a semiconductor element is formed, a non-element region electrically insulated from the element region, and the element region and the non-element region are electrically connected. Isolation insulating film for electrically insulating, a first electrode connected to the element region, a second electrode connected to the non-element region, and the first electrode and the second electrode connected in reverse series with each other A first diode and a second diode are provided.

また、本発明の他の代表的な半導体装置の一は、半導体素子が形成された素子領域と、素子領域とは電気的に絶縁された非素子領域と、素子領域と非素子領域とを電気的に絶縁する分離絶縁膜と、素子領域に接続される第１電極と、非素子領域に接続される第２電極と、第１電極と第２電極との間に電気的に接続された抵抗を有する。   In another exemplary semiconductor device of the present invention, an element region in which a semiconductor element is formed, a non-element region electrically insulated from the element region, and the element region and the non-element region are electrically connected. Isolation insulating film for electrically insulating, a first electrode connected to the element region, a second electrode connected to the non-element region, and a resistor electrically connected between the first electrode and the second electrode Have

また、本発明の他の代表的な半導体装置の一は、半導体素子が形成された素子領域と、素子領域とは電気的に絶縁された非素子領域と、素子領域と非素子領域とを電気的に絶縁する分離絶縁膜と、素子領域に接続される第１電極と、非素子領域に接続される第２電極及び第３電極とを有し、第２電極は、第１電極と同電位になるように接続されている。   In another exemplary semiconductor device of the present invention, an element region in which a semiconductor element is formed, a non-element region electrically insulated from the element region, and the element region and the non-element region are electrically connected. And a first electrode connected to the element region, and a second electrode and a third electrode connected to the non-element region, and the second electrode has the same potential as the first electrode. Connected to be.

本発明によれば、非素子領域部の電位が確実に固定されていることを確認できるため、高信頼性を有する誘電体分離半導体装置を提供することができる。   According to the present invention, since it can be confirmed that the potential of the non-element region portion is fixed reliably, a highly reliable dielectric isolation semiconductor device can be provided.

以下、本発明を実施例毎に説明する。   Hereinafter, the present invention will be described for each example.

本発明の実施例１の回路構成図を図１に示す。半導体基板を構成するＳＯＩウエハ１０は、酸化膜(ＳｉＯ2) 等で形成された分離絶縁膜３を有する。分離絶縁膜３は、半導体領域を複数に分割して、それぞれの半導体領域間を電気的に絶縁するように機能する。この分割された半導体領域は、抵抗や容量，ＭＯＳＦＥＴやＩＧＢＴ等の半導体素子が形成される素子領域部１と、これらの素子を形成しない非素子領域部２とに分けられる。 FIG. 1 shows a circuit configuration diagram of Embodiment 1 of the present invention. An SOI wafer 10 constituting a semiconductor substrate has an isolation insulating film 3 formed of an oxide film (SiO 2 ) or the like. The isolation insulating film 3 functions to divide a semiconductor region into a plurality of parts and to electrically insulate between the respective semiconductor regions. This divided semiconductor region is divided into an element region portion 1 in which semiconductor elements such as resistors, capacitors, MOSFETs, and IGBTs are formed, and a non-element region portion 2 in which these elements are not formed.

また、半導体基板上には、素子領域部１に形成されている素子領域部の電極４１と、非素子領域部２に形成されている非素子領域部の電極４２が設けられている。素子領域部の電極４１は、実装基材上の電極５にワイヤボンディング等の接続配線６１により電気的に接続されている。また、非素子領域部の電極４２もまた、実装基材上の電極５にワイヤボンディング等の接続配線６２により電気的に接続されている。   On the semiconductor substrate, an electrode 41 in the element region formed in the element region 1 and an electrode 42 in the non-element region formed in the non-element region 2 are provided. The electrode 41 in the element region is electrically connected to the electrode 5 on the mounting substrate by connection wiring 61 such as wire bonding. In addition, the electrode 42 in the non-element region is also electrically connected to the electrode 5 on the mounting substrate by connection wiring 62 such as wire bonding.

半導体基板上には、ダイオード７及び８が設けられている。これらのダイオード７及び８は、素子領域部の電極４１に接続されているＡ点と非素子領域部の電極４２に接続されているＢ点との間において、ダイオード７及び８が並列に、また、ダイオード７及び８がそれぞれ逆極性になるように電気的に接続されている。   Diodes 7 and 8 are provided on the semiconductor substrate. These diodes 7 and 8 are arranged in parallel between the point A connected to the electrode 41 in the element region and the point B connected to the electrode 42 in the non-element region. The diodes 7 and 8 are electrically connected so as to have opposite polarities.

逆並列ダイオード７，８を構成するＡ−Ｂ間の電気特性（Ｉab−Ｖab）を図２に示す。ダイオードは、電圧を正方向に印加した場合に電流を流し、負方向に印加した場合には電流を流さないという性質を有する。また、正方向の印加電圧が０Ｖ〜０.７ Ｖ程度である場合には電流が流れない。このため、Ａ点に対してＢ点の電位を高くした場合には、ダイオード７にのみ電流は流れ、ダイオード８には電流は流れない。一方、Ａ点に対してＢ点の電位を低くした場合には、ダイオード８にのみ電流は流れ、ダイオード７には電流は流れない。 FIG. 2 shows the electrical characteristics (I ab −V ab ) between A and B constituting the antiparallel diodes 7 and 8. The diode has such a property that a current flows when a voltage is applied in the positive direction and a current does not flow when a voltage is applied in the negative direction. Further, when the applied voltage in the positive direction is about 0V to 0.7V, no current flows. For this reason, when the potential at point B is made higher than point A, current flows only through diode 7 and no current flows through diode 8. On the other hand, when the potential at point B is lower than point A, current flows only through diode 8 and no current flows through diode 7.

したがって、Ａ−Ｂ間の電気特性（Ｉab−Ｖab）は、図２に示すように、正負で点対称のグラフとなる。また、電圧が−０.７Ｖ〜＋０.７Ｖの間では電流は微小で極めて絶縁状態に近く、電圧が−０.７Ｖ以下または０.７Ｖ以上の場合には、電圧の絶対値が上昇するにつれて電流の絶対値は急激に大きくなる。 Therefore, the electrical characteristics between A and B (I ab −V ab ) are positive and negative and point-symmetric graphs as shown in FIG. In addition, the current is very small when the voltage is between -0.7 V and +0.7 V, and it is very close to an insulating state. When the voltage is -0.7 V or less or 0.7 V or more, the absolute value of the voltage increases. The absolute value of the current increases rapidly.

このようなダイオード７，８で構成される逆並列ダイオードの電気特性を利用することにより、分離絶縁膜３が絶縁性を確保しているか否かの絶縁状態を評価することができる。すなわち、−０.７Ｖ〜＋０.７Ｖの間では、Ａ−Ｂ間の逆並列ダイオードには電流は流れない。このため、分離絶縁膜３の絶縁性が確保されていれば、その間では絶縁状態に相当する。一方、分離絶縁膜３の絶縁性が十分に確保できていない場合には、分離絶縁膜３を通じて電流が流れる。したがって、−０.７Ｖ〜＋０.７Ｖの範囲の電圧を印加することにより、分離絶縁膜３の絶縁状態を評価することができる。   By utilizing the electrical characteristics of the antiparallel diode composed of the diodes 7 and 8, it is possible to evaluate the insulation state as to whether or not the isolation insulating film 3 has ensured insulation. That is, between −0.7V and + 0.7V, no current flows through the antiparallel diode between A and B. For this reason, if the insulation of the isolation insulating film 3 is ensured, it corresponds to an insulated state in the meantime. On the other hand, when the insulation of the isolation insulating film 3 is not sufficiently ensured, a current flows through the isolation insulating film 3. Therefore, the insulation state of the isolation insulating film 3 can be evaluated by applying a voltage in the range of −0.7 V to +0.7 V.

仮に、ワイヤボンディング等の非素子領域部の接続配線６２に不具合があり、非素子領域部の電極４２の電位を固定できない場合でも、Ａ−Ｂ間の逆並列ダイオードの存在により、非素子領域部の電極４２の電位は、素子領域部の電極４１の電位に対して±０.７ Ｖの電圧範囲内に制限されるため、ノイズの悪影響をも抑制することができる。   Even if there is a problem in the connection wiring 62 in the non-element region such as wire bonding and the potential of the electrode 42 in the non-element region cannot be fixed, the presence of the antiparallel diode between A and B causes the non-element region Since the potential of the electrode 42 is limited within a voltage range of ± 0.7 V with respect to the potential of the electrode 41 in the element region portion, it is possible to suppress adverse effects of noise.

本発明の実施例２の回路構成図を図３に示す。本実施例の説明において、実施例１と同じ部分の説明は省略する。   FIG. 3 shows a circuit configuration diagram of Embodiment 2 of the present invention. In the description of this embodiment, the description of the same parts as those in Embodiment 1 is omitted.

実施例２において、実施例１と異なる部分は、逆並列ダイオードを構成するダイオード７１及び８１をそれぞれ複数個直列に接続した点である。すなわち、ｎ２個のダイオード７１を同方向に直列接続し、ダイオード７１とは逆極性となるように、ｎ１個のダイオード８１を同方向に直列接続している。   The second embodiment is different from the first embodiment in that a plurality of diodes 71 and 81 constituting antiparallel diodes are connected in series. That is, n2 diodes 71 are connected in series in the same direction, and n1 diodes 81 are connected in series in the same direction so as to have a polarity opposite to that of the diode 71.

この接続状態における逆並列ダイオードのＡ−Ｂ間の電気特性（Ｉab−Ｖab）を図４に示す。Ａ点に対してＢ点の電位を高くした場合には、ダイオード７１にのみ電流は流れ、ダイオード８１には電流は流れない。一方、Ａ点に対してＢ点の電位を低くした場合には、ダイオード８１にのみ電流は流れ、ダイオード７１には電流は流れない。 FIG. 4 shows the electrical characteristics (I ab −V ab ) between A and B of the antiparallel diode in this connected state. When the potential at the point B is made higher than the point A, current flows only through the diode 71 and no current flows through the diode 81. On the other hand, when the potential at the point B is lowered with respect to the point A, current flows only through the diode 81 and no current flows through the diode 71.

したがって、Ａ−Ｂ間の電気特性は、図４に示すように、ダイオードの直列段数に応じて、−０.７Ｖ×ｎ２〜＋０.７Ｖ×ｎ１の電圧範囲にてほぼ絶縁状態となるため、その電圧範囲において分離絶縁膜３の絶縁状態の評価を行うことができる。   Therefore, as shown in FIG. 4, the electrical characteristics between A and B are almost in an insulated state in a voltage range of −0.7 V × n2 to +0.7 V × n1 depending on the number of series stages of diodes. The insulation state of the isolation insulating film 3 can be evaluated in the voltage range.

特に、半導体素子の性質によっては、例えば半導体チップが大きい場合、素子領域部の電極４１あるいは非素子領域部の電極４２から遠い位置の分離絶縁膜には、電圧降下により電極４１と電極４２との間に印加した電圧よりも低い電圧しか印加できないことが懸念され、−０.７Ｖ〜＋０.７Ｖの範囲で分離絶縁膜３の絶縁状態を十分に評価できない場合が考えられる。このような場合には、本実施例がより効果的である。   In particular, depending on the nature of the semiconductor element, for example, when the semiconductor chip is large, the isolation insulating film located far from the electrode 41 in the element region portion or the electrode 42 in the non-element region portion has a voltage drop between the electrode 41 and the electrode 42. There is a concern that only a voltage lower than the voltage applied between them can be applied, and there may be a case where the insulation state of the isolation insulating film 3 cannot be sufficiently evaluated in the range of −0.7V to + 0.7V. In such a case, the present embodiment is more effective.

本発明の実施例３の回路構成図を図５に示す。本実施例の説明において、他の実施例と同じ部分の説明は省略する。   FIG. 5 shows a circuit configuration diagram of Embodiment 3 of the present invention. In the description of this embodiment, the description of the same parts as in the other embodiments is omitted.

実施例３では、Ａ−Ｂ間に２個のダイオード７２及び８２を逆方向に直列接続した点が、他の実施例とは異なる点である。   The third embodiment is different from the other embodiments in that two diodes 72 and 82 are connected in series in the reverse direction between A and B.

２個のツェナーダイオード７２及び８２を逆方向に直列接続した場合におけるＡ−Ｂ間の電気特性（Ｉab−Ｖab）を図６に示す。ダイオード７２の耐圧をＶｄ７２、ダイオード８２の耐圧をＶｄ８２とすると、素子領域部の電極４１の電位は、非素子領域部の電極
４２の電位に対して−Ｖｄ８２から＋Ｖｄ７２の電圧範囲において絶縁状態となる。 FIG. 6 shows electric characteristics (I ab −V ab ) between A and B when two zener diodes 72 and 82 are connected in series in the reverse direction. When the withstand voltage of the diode 72 is Vd72 and the withstand voltage of the diode 82 is Vd82, the potential of the electrode 41 in the element region is in an insulating state in the voltage range of −Vd82 to + Vd72 with respect to the potential of the electrode 42 in the non-element region. .

本実施例は、実施例２の場合と同様に、−０.７〜＋０.７の範囲で分離絶縁膜３の絶縁状態を十分に評価できない半導体素子を用いた場合に、特に効果的である。   As in the case of the second embodiment, this embodiment is particularly effective when a semiconductor element that cannot sufficiently evaluate the insulating state of the isolation insulating film 3 in the range of −0.7 to +0.7 is used. .

本実施例の構成の場合には、ダイオード７２及び８２として、ツェナーダイオードを用いるのがより望ましい。ツェナーダイオードはｐｎ接合ダイオードに比べて耐圧が低いため、仮にワイヤボンディング等の非素子領域部の接続配線６２に不具合があり、非素子領域部の電極４２の電位を固定できない場合でも、Ａ−Ｂ間の逆直列ダイオードの存在により、非素子領域部の電極４２の電位に対する素子領域部の電極４１の電位は、ダイオード７２及び８２としてｐｎ接合ダイオードを用いた場合に比べて、−Ｖｄ８２から＋Ｖｄ72の狭い電圧範囲内に制限されるため、ノイズの悪影響を抑制することができる。   In the case of the configuration of this embodiment, it is more desirable to use Zener diodes as the diodes 72 and 82. Since the Zener diode has a lower withstand voltage than the pn junction diode, there is a problem in the connection wiring 62 in the non-element region such as wire bonding, and even if the potential of the electrode 42 in the non-element region cannot be fixed, AB The potential of the electrode 41 in the element region relative to the potential of the electrode 42 in the non-element region is between −Vd82 and + Vd72 as compared to the case where pn junction diodes are used as the diodes 72 and 82. Since it is limited within a narrow voltage range, the adverse effect of noise can be suppressed.

本発明の実施例２の回路構成図を図７に示す。本実施例の説明において、実施例３と同じ部分の説明は省略する。   FIG. 7 shows a circuit configuration diagram of Embodiment 2 of the present invention. In the description of this embodiment, the description of the same parts as those in Embodiment 3 is omitted.

実施例４において、実施例３と異なる部分は、逆直列ダイオードを構成するダイオード７３及び８３をそれぞれ複数個直列に接続した点である。すなわち、ｎ２個のダイオード７３を同方向に直列接続し、ダイオード７３とは逆極性となるように、ｎ１個のダイオード８３を同方向に直列接続している。   The fourth embodiment is different from the third embodiment in that a plurality of diodes 73 and 83 constituting anti-series diodes are connected in series. That is, n2 diodes 73 are connected in series in the same direction, and n1 diodes 83 are connected in series in the same direction so as to have a polarity opposite to that of the diode 73.

この接続状態における逆並列ダイオードのＡ−Ｂ間の電気特性（Ｉab−Ｖab）を図４に示す。Ａ点に対してＢ点の電位を高くした場合には、ダイオード７３にのみ電流は流れ、ダイオード８３には電流は流れない。一方、Ａ点に対してＢ点の電位を低くした場合には、ダイオード８３にのみ電流は流れ、ダイオード７３には電流は流れない。 FIG. 4 shows electric characteristics (I ab −V ab ) between A and B of the antiparallel diode in this connection state. When the potential at point B is made higher than point A, current flows only through diode 73 and no current flows through diode 83. On the other hand, when the potential at point B is lowered relative to point A, current flows only through diode 83, and no current flows through diode 73.

したがって、Ａ−Ｂ間の電気特性は、図８に示すように、ダイオードの直列段数に応じて、−Ｖｄ８２×ｎ２〜＋Ｖｄ７２×ｎ１の電圧範囲にてほぼ絶縁状態となるため、その電圧範囲において分離絶縁膜３の絶縁状態の評価を行うことができる。   Therefore, as shown in FIG. 8, the electrical characteristics between A and B are substantially insulative in the voltage range of −Vd82 × n2 to + Vd72 × n1 depending on the number of series stages of diodes. The insulation state of the isolation insulating film 3 can be evaluated.

特に、半導体素子の性質によっては、例えば半導体チップが大きい場合、素子領域部の電極４１あるいは非素子領域部の電極４２から遠い位置の分離絶縁膜には、電圧降下により電極４１と電極４２との間に印加した電圧よりも低い電圧しか印加できないことが懸念され、−Ｖｄ８２〜＋Ｖｄ７２の範囲で分離絶縁膜３の絶縁状態を十分に評価できない場合が考えられる。このような場合には、本実施例がより効果的である。   In particular, depending on the nature of the semiconductor element, for example, when the semiconductor chip is large, the isolation insulating film located far from the electrode 41 in the element region portion or the electrode 42 in the non-element region portion has a voltage drop between the electrode 41 and the electrode 42. There is concern that only a voltage lower than the voltage applied between them can be applied, and there may be a case where the insulation state of the isolation insulating film 3 cannot be sufficiently evaluated in the range of −Vd82 to + Vd72. In such a case, the present embodiment is more effective.

本発明の実施例５の回路構成図を図９に示す。本実施例の説明において、他の実施例と同じ部分の説明は省略する。   FIG. 9 shows a circuit configuration diagram of Embodiment 5 of the present invention. In the description of this embodiment, the description of the same parts as in the other embodiments is omitted.

本実施例は、他の実施例におけるダイオードに代えて、Ａ−Ｂ間に抵抗９を接続した構成となっている。   In this embodiment, a resistor 9 is connected between A and B instead of the diode in the other embodiments.

本実施例では、分離絶縁膜３に欠陥がない場合には、検査電圧を印加したときにＡ−Ｂ間に挿入された抵抗９の抵抗値を確認することができる。一方、分離絶縁膜３に欠陥が存在する場合には、検査電圧を印加したときに抵抗９の抵抗値よりも低い抵抗値が現れ、不良品を選別することが可能となる。   In the present embodiment, when the isolation insulating film 3 has no defect, the resistance value of the resistor 9 inserted between A and B when the inspection voltage is applied can be confirmed. On the other hand, when a defect exists in the isolation insulating film 3, a resistance value lower than the resistance value of the resistor 9 appears when an inspection voltage is applied, and defective products can be selected.

非素子領域部の電極４２の接続配線６２（ワイヤ）に、万一不具合が生じた場合でも、非素子領域部２には電流が流れないためＡ−Ｂ間の抵抗９における電圧降下はなく、Ａ−Ｂ間の抵抗９により、非素子領域部の電極４２の電位は素子領域部の電極４１の電位に固定される。   Even if a failure occurs in the connection wiring 62 (wire) of the electrode 42 in the non-element region portion, no current flows through the non-element region portion 2, so there is no voltage drop in the resistor 9 between A and B. The potential of the electrode 42 in the non-element region is fixed to the potential of the electrode 41 in the element region by the resistor 9 between A and B.

本発明の実施例６の回路構成図を図１０に示す。本実施例の説明において、他の実施例と同じ部分の説明は省略する。   FIG. 10 shows a circuit configuration diagram of Embodiment 6 of the present invention. In the description of this embodiment, the description of the same parts as in the other embodiments is omitted.

他の実施例においては、半導体基板上にＡ−Ｂ間に挿入される回路を配置しているが、この回路の挿入位置は半導体基板の内部のみに限られるものではない。   In another embodiment, a circuit to be inserted between A and B is arranged on the semiconductor substrate, but the insertion position of this circuit is not limited to the inside of the semiconductor substrate.

本実施例は、実施例１におけるダイオード７及び８を半導体基板上に設けるのではなく、半導体基板の外部で接続したものである。例えば、半導体基板を実装するリードフレームやインターポーザ等の実装基材上に挿入することができる。特に、インターポーザを利用する場合には、マルチチップモジュール（ＭＣＭ）構成となる。また、本半導体装置を実装するマザーボード上に挿入することもできる。   In the present embodiment, the diodes 7 and 8 in the first embodiment are not provided on the semiconductor substrate but are connected outside the semiconductor substrate. For example, it can be inserted on a mounting substrate such as a lead frame or an interposer for mounting a semiconductor substrate. In particular, when an interposer is used, a multi-chip module (MCM) configuration is used. It can also be inserted on a motherboard on which the semiconductor device is mounted.

本発明の実施例７の回路構成図を図１１に示す。本実施例の説明において、他の実施例と同じ部分の説明は省略する。   FIG. 11 shows a circuit configuration diagram of Embodiment 7 of the present invention. In the description of this embodiment, the description of the same parts as in the other embodiments is omitted.

本実施例では、非素子領域部２に接続される電極として、電極４２及び電極４３の２電極を設けた誘電体分離半導体基板を用いる。非素子領域部２の電極４２は、ワイヤボンディング等で素子領域部１の電極４１と同一電位の実装基材上の電極５１（パッド）に接続されている。一方、非素子領域部２の電極４３は、チェック用端子となる実装基材上の電極５３（パッド）にワイヤボンディング等で接続されている。   In this example, a dielectric isolation semiconductor substrate provided with two electrodes 42 and 43 is used as an electrode connected to the non-element region 2. The electrode 42 in the non-element region 2 is connected to an electrode 51 (pad) on the mounting substrate having the same potential as the electrode 41 in the element region 1 by wire bonding or the like. On the other hand, the electrode 43 in the non-element region portion 2 is connected to an electrode 53 (pad) on the mounting base material serving as a check terminal by wire bonding or the like.

本実施例では、実装基板上の電極５１と、チェック用端子となる実装基板上の電極５３との間の電気的チェックが行われる。これにより、ワイヤ等の接続配線６２の接続が確実になされていれば短絡状態が示され、接続配線６２に不具合があればオープン状態または何らかの抵抗値が示されるため、接続配線６２の電気的チェックを確実に行うことが可能となる。非素子領域部２の電位は、ワイヤ等の接続配線６２によって確実に素子領域部１の電位に固定され、不具合品が市場に流出することはなくなる。他の実施例と組み合わせた構成とすればさらに信頼性を向上させることができる。   In this embodiment, an electrical check is performed between the electrode 51 on the mounting board and the electrode 53 on the mounting board to be a check terminal. As a result, if the connection wiring 62 such as a wire is securely connected, a short-circuit state is indicated, and if there is a defect in the connection wiring 62, an open state or some resistance value is indicated. Can be reliably performed. The potential of the non-element region portion 2 is reliably fixed to the potential of the element region portion 1 by the connection wiring 62 such as a wire, so that a defective product does not flow out to the market. If the configuration is combined with other embodiments, the reliability can be further improved.

本発明の実施例８の回路構成図を図１２に示す。本実施例の説明において、他の実施例と同じ部分の説明は省略する。   FIG. 12 shows a circuit configuration diagram of Embodiment 8 of the present invention. In the description of this embodiment, the description of the same parts as in the other embodiments is omitted.

本実施例は、実施例３において、素子領域部の電極４１に接続される接続配線６１（ワイヤ）の本数を複数ｎ３本にしている。これによって素子領域部の電極４１側の寄生インダクタンスを低減することができ、実施例３の場合と比較して、ノイズマージンの低下を補うことができる。他の実施例と組み合わせた構成とすればさらに信頼性を向上させることができる。   In the third embodiment, the number of connection wirings 61 (wires) connected to the electrode 41 in the element region portion is set to a plurality of n3 in the third embodiment. As a result, the parasitic inductance on the electrode 41 side in the element region can be reduced, and a reduction in noise margin can be compensated for as compared with the third embodiment. If the configuration is combined with other embodiments, the reliability can be further improved.

本発明の実施例９の回路構成図を図１３に示す。本実施例の説明において、他の実施例と同じ部分の説明は省略する。   FIG. 13 shows a circuit configuration diagram of Embodiment 9 of the present invention. In the description of this embodiment, the description of the same parts as in the other embodiments is omitted.

本実施例は、他の実施例におけるＡ−Ｂ間には特にダイオードや抵抗を接続することなく、非素子領域部の電極４２に接続される接続配線６２（ワイヤ）の本数を複数ｎ４本にしている。これによって接続配線６２が完全断線する不良率は、１本の場合と比べて（１／ｎ４）乗に抑制することが可能となり、大幅に減少する。他の実施例と組み合わせた構成とすればさらに信頼性を向上させることができる。   In this embodiment, the number of connection wirings 62 (wires) connected to the electrode 42 in the non-element region portion is set to a plurality of n4 without particularly connecting a diode or a resistor between A and B in the other embodiments. ing. As a result, the defect rate at which the connection wiring 62 is completely disconnected can be suppressed to the (1 / n4) th power as compared with the case of a single wire, and is greatly reduced. If the configuration is combined with other embodiments, the reliability can be further improved.

実施例１の回路構成図。1 is a circuit configuration diagram of Embodiment 1. FIG. 実施例１のＡ−Ｂ間の電気特性。The electrical characteristic between AB of Example 1. FIG. 実施例２の回路構成図。FIG. 6 is a circuit configuration diagram of Embodiment 2. 実施例２のＡ−Ｂ間の電気特性。The electrical characteristic between AB of Example 2. FIG. 実施例３の回路構成図。FIG. 6 is a circuit configuration diagram of Embodiment 3. 実施例３のＡ−Ｂ間の電気特性。The electrical characteristic between AB of Example 3. FIG. 実施例４の回路構成図。FIG. 6 is a circuit configuration diagram of Embodiment 4. 実施例４のＡ−Ｂ間の電気特性。The electrical characteristic between AB of Example 4. FIG. 実施例５の回路構成図。FIG. 10 is a circuit configuration diagram of Embodiment 5. 実施例６の回路構成図。FIG. 10 is a circuit configuration diagram of Embodiment 6. 実施例７の回路構成図。FIG. 10 is a circuit configuration diagram of Embodiment 7. 実施例８の回路構成図。FIG. 10 is a circuit configuration diagram of an eighth embodiment. 実施例９の回路構成図。FIG. 10 is a circuit configuration diagram of Embodiment 9.

符号の説明Explanation of symbols

１…素子領域部、２…非素子領域部、３…分離絶縁膜、５…実装基材上の電極、７,８…ダイオード、９…抵抗、４１…素子領域部の電極、４２…非素子領域部の電極、５１…素子領域部の電極と接続される実装基材上の電極、５２…非素子領域部の電極と接続される実装基材上の電極、５３…接続確認用端子の実装基材上の電極、６１…素子領域部の接続配線、６２…非素子領域部の接続配線。   DESCRIPTION OF SYMBOLS 1 ... Element area | region part, 2 ... Non-element area | region, 3 ... Isolation insulating film, 5 ... Electrode on a mounting base material, 7, 8 ... Diode, 9 ... Resistance, 41 ... Electrode of an element area | region part, 42 ... Non-element Electrode in the region portion, 51... Electrode on the mounting substrate connected to the electrode in the element region portion, 52... Electrode on the mounting substrate connected to the electrode in the non-element region portion, 53. Electrodes on the substrate, 61... Connection wiring in the element region, 62... Connection wiring in the non-element region.

Claims (15)

半導体素子が形成された素子領域と、
前記素子領域とは電気的に絶縁された非素子領域と、
前記素子領域と前記非素子領域とを電気的に絶縁する分離絶縁膜と、
前記素子領域に接続される第１電極と、
前記非素子領域に接続される第２電極と、
前記第１電極と前記第２電極との間に互いに逆並列に接続された第１ダイオード及び第２ダイオードとを備えたことを特徴とする半導体装置。 An element region in which a semiconductor element is formed;
A non-element region electrically isolated from the element region;
An isolation insulating film that electrically insulates the element region and the non-element region;
A first electrode connected to the element region;
A second electrode connected to the non-element region;
A semiconductor device comprising: a first diode and a second diode connected in antiparallel to each other between the first electrode and the second electrode. 請求項１記載の半導体装置において、
前記半導体装置は、直列接続された複数の前記第１ダイオードと、直列接続された複数の前記第２ダイオードとを備えたことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device comprises a plurality of first diodes connected in series and a plurality of second diodes connected in series. 半導体素子が形成された素子領域と、
前記素子領域とは電気的に絶縁された非素子領域と、
前記素子領域と前記非素子領域とを電気的に絶縁する分離絶縁膜と、
前記素子領域に接続される第１電極と、
前記非素子領域に接続される第２電極と、
前記第１電極と前記第２電極との間に互いに逆直列に接続された第１ダイオード及び第２ダイオードとを備えたことを特徴とする半導体装置。 An element region in which a semiconductor element is formed;
A non-element region electrically isolated from the element region;
An isolation insulating film that electrically insulates the element region and the non-element region;
A first electrode connected to the element region;
A second electrode connected to the non-element region;
A semiconductor device comprising: a first diode and a second diode connected in reverse series with each other between the first electrode and the second electrode. 請求項３記載の半導体装置において、
前記第１ダイオード及び前記第２ダイオードは、ツェナーダイオードであることを特徴とする半導体装置。 The semiconductor device according to claim 3.
The semiconductor device, wherein the first diode and the second diode are Zener diodes. 請求項３または４記載の半導体装置において、
前記半導体装置は、直列接続された複数の前記第１ダイオードと、直列接続された複数の前記第２ダイオードとを備えたことを特徴とする半導体装置。 The semiconductor device according to claim 3 or 4,
The semiconductor device comprises a plurality of first diodes connected in series and a plurality of second diodes connected in series. 半導体素子が形成された素子領域と、
前記素子領域とは電気的に絶縁された非素子領域と、
前記素子領域と前記非素子領域とを電気的に絶縁する分離絶縁膜と、
前記素子領域に接続される第１電極と、
前記非素子領域に接続される第２電極と、
前記第１電極と前記第２電極との間に電気的に接続された抵抗を有することを特徴とする半導体装置。 An element region in which a semiconductor element is formed;
A non-element region electrically isolated from the element region;
An isolation insulating film that electrically insulates the element region and the non-element region;
A first electrode connected to the element region;
A second electrode connected to the non-element region;
A semiconductor device comprising a resistor electrically connected between the first electrode and the second electrode. 請求項１乃至５のいずれか一に記載の半導体装置において、
前記第１電極は、第１接続配線を用いて外部電極と電気的に接続され、
前記第２電極は、第２接続配線を用いて前記外部電極と電気的に接続されていることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 5,
The first electrode is electrically connected to an external electrode using a first connection wiring,
The semiconductor device, wherein the second electrode is electrically connected to the external electrode using a second connection wiring. 請求項１乃至５、または７のいずれか一に記載の半導体装置において、
前記第１ダイオード及び前記第２ダイオードは、半導体基板の外部に設けられていることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 5, or 7,
The semiconductor device, wherein the first diode and the second diode are provided outside a semiconductor substrate. 請求項６または７に記載の半導体装置において、
前記抵抗は、半導体基板の外部に設けられていることを特徴とする半導体装置。 The semiconductor device according to claim 6 or 7,
The semiconductor device is characterized in that the resistor is provided outside a semiconductor substrate. 半導体素子が形成された素子領域と、
前記素子領域とは電気的に絶縁された非素子領域と、
前記素子領域と前記非素子領域とを電気的に絶縁する分離絶縁膜と、
前記素子領域に接続される第１電極と、
前記非素子領域に接続される第２電極及び第３電極とを有していることを特徴とする半導体装置。 An element region in which a semiconductor element is formed;
A non-element region electrically isolated from the element region;
An isolation insulating film that electrically insulates the element region and the non-element region;
A first electrode connected to the element region;
A semiconductor device comprising a second electrode and a third electrode connected to the non-element region. 請求項１乃至６のいずれか一に記載の半導体装置において、
前記非素子領域に接続される第３電極を有していることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device comprising a third electrode connected to the non-element region. 請求項１０または１１記載の半導体装置において、
前記第１電極及び前記第２電極は、第１外部電極と電気的に接続され、
前記第３電極は、第２外部電極と電気的に接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 10 or 11,
The first electrode and the second electrode are electrically connected to a first external electrode,
The semiconductor device, wherein the third electrode is electrically connected to a second external electrode. 請求項７乃至９または１２のいずれか一に記載の半導体装置において、
前記半導体装置は、前記第１接続配線の本数が複数であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 7 to 9 or 12,
In the semiconductor device, the number of the first connection wirings is plural. 半導体素子が形成された素子領域と、
前記素子領域とは電気的に絶縁された非素子領域と、
前記素子領域と前記非素子領域とを電気的に絶縁する分離絶縁膜と、
前記素子領域に接続される第１電極と、
前記非素子領域に接続される第２電極と、
前記第１電極を外部電極に電気的に接続する第１接続配線と、
前記第２電極を外部電極に電気的に接続する複数の第２接続配線とを備えたことを特徴とする半導体装置。 An element region in which a semiconductor element is formed;
A non-element region electrically isolated from the element region;
An isolation insulating film that electrically insulates the element region and the non-element region;
A first electrode connected to the element region;
A second electrode connected to the non-element region;
A first connection wiring for electrically connecting the first electrode to an external electrode;
A semiconductor device comprising: a plurality of second connection wirings for electrically connecting the second electrode to an external electrode. 請求項７乃至９または１２または１３のいずれか一に記載の半導体装置において、
前記半導体装置は、前記第２接続配線の本数が複数であることを特徴とする半導体装置。
The semiconductor device according to any one of claims 7 to 9, 12 or 13,
In the semiconductor device, the number of the second connection wirings is plural.
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JP2011244002A (en) * 2011-08-01 2011-12-01 Hitachi Automotive Systems Ltd Semiconductor device

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JPH0883830A (en) * 1994-09-09 1996-03-26 Nippondenso Co Ltd Inspecting method of insulated-separated type semiconductor device, and insulated-separated type semiconductor device
JP2002343855A (en) * 2001-05-11 2002-11-29 Denso Corp Insulated isolation type semiconductor device and manufacturing method thereof
JP2004146440A (en) * 2002-10-22 2004-05-20 Nec Electronics Corp Electrostatic protective circuit and semiconductor device

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Publication number Priority date Publication date Assignee Title
JPH0883830A (en) * 1994-09-09 1996-03-26 Nippondenso Co Ltd Inspecting method of insulated-separated type semiconductor device, and insulated-separated type semiconductor device
JP2002343855A (en) * 2001-05-11 2002-11-29 Denso Corp Insulated isolation type semiconductor device and manufacturing method thereof
JP2004146440A (en) * 2002-10-22 2004-05-20 Nec Electronics Corp Electrostatic protective circuit and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011244002A (en) * 2011-08-01 2011-12-01 Hitachi Automotive Systems Ltd Semiconductor device

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