JP2002033436A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which avoids troubles due to the waveform of a specified chip to allow different power waveforms to be applied and the Iddq test to be conducted for the specified chip to improve the module quality. SOLUTION: A multi-chip module 1 mounts a plurality of chips having different functions and modules and packages them. It is composed of a flash memory 2, SRAM chip 3, microcomputer chip 4, etc., the flash memory 2 has a limit to the power start waveform, a power voltage of the same potential as that of the other chips 3, 4 is separated and connected to a power source pin Vcc1 (Vss1), and the SRAM and microcomputer chips 3, 4 have no limit to the power start waveform and are connected to a power source pin Vcc2 (Vss2).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on which a plurality of chips having different logic functions are mounted, and in particular, to avoid a problem caused by a power-on waveform of a specific chip and to facilitate testing. The present invention relates to a technology effective when applied to a possible multi-chip module.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, in a memory module which is an example of a semiconductor device having a plurality of chips mounted thereon, when a plurality of chips having the same function are mounted, a power supply pin is provided for each chip. , While the core power is commonly supplied to all chips,
A method of commonly supplying power to all chips separately from the O-buffer power supply is used.

In a multi-chip module having a plurality of chips having different functions, when a flash memory, an SRAM, a microcomputer (hereinafter abbreviated as a microcomputer) or the like is mounted, the module is designed to reduce power supply impedance and reduce noise. A method of shorting a power supply wiring in a substrate and supplying power to all chips having different functions in common is used.

[0004] As a technique relating to such a memory module, a multi-chip module, etc., for example, on May 31, 1993, Nikkei BP published “Practical Course VLSI Packaging Technology (Lower)” P213 to P2.
51 and the like.

[0005]

The inventors of the present invention have studied the techniques of the memory module and the multi-chip module as described above, and have found the following. This will be described with reference to FIGS. 12 and 13 showing an example of this type of memory module and FIG. 14 showing an example of a multi-chip module.

FIG. 12 shows a module corresponding to the above-described method, in which a plurality of memory chips 21 having the same function are mounted, and a power supply is separately connected to each of the memory chips 21. In this example, as the number of mounted memory chips 21 increases, the number of power supply pins increases, and the size of the module increases. Also, in the evaluation chip in the development stage, in a module having the same external shape and the same pin arrangement as the mass-produced chip, it is assumed that a power supply pin cannot be assigned to each memory chip 21 due to the restriction of the number of power supply pins.

FIG. 13 corresponds to the above method, and FIG.
Similarly to the above, a module in which a plurality of memory chips 22 having the same function are mounted is supplied with power for each function of the memory chip 22, and each power is supplied to all the memory chips 22 in common. In this example, it is not possible to control the power supply waveform for the memory chip 22 that is limited in the power supply startup waveform. In addition, the memory chip 2 having a large standby current
If 2 are connected to the same power supply pin, Iddq testing by current measurement may not be possible.

FIG. 14 shows a flash memory chip 2, an SRAM chip 3, and a microcomputer chip 4 having different functions.
And a power supply pin which has the same potential during operation is short-circuited by a power supply wiring in the module substrate. In this example, it is not possible to control the power supply waveform for the flash memory chip 2 that has a restriction on the power supply rising waveform. If the flash memory chip 2 or the SRAM chip 3 having a large standby current is connected to the same power supply pin, Iddq testing based on the current measurement of the microcomputer chip 4 may not be possible.

Accordingly, an object of the present invention is to provide a multi-chip module having a plurality of chips having different functions mounted thereon, thereby avoiding a problem caused by a power-up waveform of a specific chip and applying different power-supply waveforms. A semiconductor device is provided.

Another object of the present invention is to provide a semiconductor device capable of performing an Iddq test of a specific chip in a multi-chip module having a plurality of chips having different functions and improving the quality of the multi-chip module. Is provided.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a first semiconductor device according to the present invention is a multi-chip module including a chip which needs to control a rising waveform of a power supply.
In operation with an unrestricted chip, a power supply pin having the same potential is separated.

Further, a second semiconductor device according to the present invention comprises:
A power supply pin having the same potential as a chip whose power supply current decreases by stopping the clock during standby or operation and a chip whose power supply current does not decrease is assigned to different power supply terminals.
In this configuration, when the number of chips to be further reduced is plural and the sum of the currents of these chips is smaller than the sum of the currents of the other chips, the power supply pins of the same potential of these chips are connected to the same power supply terminal. It is intended to be assigned.

Further, the third semiconductor device according to the present invention includes a chip having a limited power supply rising waveform, a chip whose power supply current is reduced by stopping a clock during standby or operation, and a power supply startup. There is no limitation of the rising waveform,
When there is a chip whose power supply current does not decrease by stopping the clock during standby or operation, the power supply pins of the same potential of each chip are assigned to different power supply terminals.

According to the first and third semiconductor devices, different power supply waveforms can be obtained by separating power supply pins having the same potential from a chip having a limited power supply rising waveform and a chip having no restriction. Can be applied. As a result, one chip requiring a special power supply waveform
It can be packaged in one multi-chip module and operated normally.

Further, according to the second and third semiconductor devices, the power supply pins of the same electric potential of the chip whose power supply current is reduced by stopping the clock during standby or operation and the chip whose power supply current does not decrease are connected to different power supply pins. By allocating to the terminals, the former enables the Iddq test and improves the quality.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is a schematic functional configuration diagram showing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a waveform of a power supply voltage supplied to each chip in the semiconductor device according to the first embodiment. FIG. 3 is a perspective view showing the appearance of the semiconductor device, FIG. 4 is a partial sectional view showing the structure of the semiconductor device,
FIG. 5 is a plan view showing the substrate surface of the semiconductor device, and FIG. 6 is a plan view showing the substrate back surface.

First, the configuration of an example of the semiconductor device of the present embodiment will be described with reference to FIG. The semiconductor device according to the present embodiment is, for example, a multi-chip module 1 in which a plurality of chips having different functions are mounted, and the plurality of chips are modularized and packaged, and a flash memory chip 2, an SRAM chip 3, and a microcomputer It is composed of a chip 4 and the like.

The flash memory chip 2 is, for example, a chip having a limited rise waveform of the power supply. If the rise speed of the power supply becomes slow, the internal sequence cannot be properly initialized. Only the flash memory chip 2 is separated from the other SRAM chip 3 and the microcomputer chip 4 by a power supply voltage having the same potential at the time of operation.
(Vss1).

The SRAM chip 3 is, for example, a chip having no limitation on the power supply rising waveform, and is connected to a power supply pin Vcc2 (Vss2) different from the flash memory chip 2.

The microcomputer chip 4 is, for example, a chip having no limitation on the power supply rising waveform, like the SRAM chip 3, and has the same power supply pin Vcc2 as the SRAM chip 3.
(Vss2).

Next, the operation of this embodiment will be described with reference to FIG.
The operation of the multi-chip module 1 will be described below.
This multi-chip module 1 is supplied with the same potential power supply voltage (Vc) from outside through power supply pins Vcc1 and Vcc2.
c1) and the power supply voltage (Vcc2) are input. One power supply voltage (Vcc1) is supplied to the flash memory chip 2, and the other power supply voltage (Vcc2) is supplied to the SRAM chip 3 and the microcomputer chip 4, respectively.

In particular, since the power supply voltage (Vcc1) supplied to the flash memory chip 2 has a fast rising voltage as shown in FIG. 2, the flash memory chip 2 can operate normally. That is, in the flash memory chip 2 in which the rising waveform of the power supply is restricted, there is a problem that the operation does not operate if the rising waveform is delayed. However, it is possible to avoid this problem by making the rising waveform sharp. It becomes possible.

In addition, there is no limitation on the power supply rising waveform.
The RAM chip 3 and the microcomputer chip 4 have a power supply voltage (V
cc1), the power supply voltage (V
By supplying cc2), the SRAM chip 3 and the microcomputer chip 4 can operate normally.

Therefore, according to the multi-chip module 1 of the present embodiment, the power supply pins of the same potential as the flash memory chip 2 having the limited power supply rising waveform and the SRAM chip 3 and the microcomputer chip 4 having no restriction. Vcc1,
By separating Vcc2, different power supply waveforms can be applied, so that a chip requiring a special power supply waveform such as the flash memory chip 2 is packaged in one multi-chip module 1 and normally. It can be operated.

The multi-chip joule 1 according to the present embodiment is formed, for example, in a structure as shown in FIGS. As shown in FIGS. 3 to 6, the multi-chip module 1 includes a flash memory chip 2, an SRAM
A plurality of chips 3 having different functions of a chip 3 and a microcomputer chip 4 are mounted on a substrate 5 and molded by a resin 6 to form a QFP structure in which leads 7 extend in four directions. These figures show an example in which two SRAM chips 3 are mounted.

In this multi-chip module, as shown in FIG. 5, one microcomputer chip 4 is mounted on the surface of a substrate 5, and the electrode pads on the microcomputer chip 4 and the substrate 5
The upper wiring pad is bonded by a wire 8. A plurality of chip capacitors 9 and chip resistors 10 are mounted on the surface of the substrate 5.

As shown in FIG. 6, on the back surface of the substrate 5,
One flash memory chip 2 and two SRAM chips 3 are mounted, and these flash memory chips 2
The electrode pads on the SRAM chip 3 and the wiring pads on the substrate 5 are bonded by wires 8. In addition,
These flash memory chip 2 and SRAM chip 3
Are mounted in such a structure as to be accommodated in a concave portion 11 formed on the back surface of the substrate 5.

(Embodiment 2) FIG. 7 is a schematic functional configuration diagram showing a semiconductor device of Embodiment 2 of the present invention, and FIG. 8 is an explanatory diagram showing an Iddq test in the semiconductor device of this embodiment.

As in the first embodiment, the semiconductor device of the present embodiment includes, for example, a multi-chip module 1a in which a plurality of chips having different functions are mounted, and the plurality of chips are modularized and packaged. However, the difference from the first embodiment is to consider a chip in which the power supply current decreases in a standby state (standby state) or a clock stop in operation instead of a chip having a limited power supply rising waveform. It is a point that was made.

That is, the multi-chip module 1a of the present embodiment comprises a flash memory chip 2, an SRAM
The microcomputer chip 4 includes a chip 3, a microcomputer chip 4, and the like. The microcomputer chip 4 is a chip whose power supply current decreases when the clock is stopped during standby or operation, for example.
A power supply voltage having the same potential as that of the AM chip 3 is assigned to a different terminal and connected to a different power supply pin Vcc1 (Vss1).

The other flash memory chips 2, S
The RAM chip 3 is a chip whose power supply current does not decrease when the clock is stopped during standby or operation, for example, and has a power supply pin Vcc2 (V
ss2).

Next, as for the operation of the present embodiment, the operation of the multi-chip module 1 will be described. In a configuration such as the multi-chip module 1a, the power supply current of the microcomputer chip 4 is usually reduced to several μA to several tens μA by stopping the clock during standby or operation, while the flash memory chip A power supply current of about several hundred μA to several tens μA always flows through the SRAM chip 2 and the SRAM chip 3.

For example, in the power supply connection as shown in FIG. 14, even if an abnormally large current of about several hundred μA flows due to the failure of the microcomputer chip 4, the flash memory chip 2 or the SRAM chip 3 Only the entire power supply current, including, can be observed. Then, even if the current of the microcomputer chip 4 fluctuates due to the failure of the microcomputer chip 4, the sample variation of the current of the flash memory chip 2 or the SRAM chip 3 is larger and the abnormal current of the microcomputer chip 4 is relatively small. Too bad to detect a defect.

However, by using the power supply connection as in the present embodiment, it is possible to detect an abnormally large power supply current due to a failure of the microcomputer chip 4 that can perform at least the Iddq test. This Iddq test is a CMO
This method focuses on the leakage current peculiar to S and monitors and tests that an excessive current flows when there is a defect.
That is, the Iddq test is a method of finding a defect by checking the state of the circuit current passing through the power supply pin.

For example, FIG. 8 ((a): good product, (c):
PMOS transistor and NMOS as shown in Defective product)
In a CMOS circuit (inverter) including transistors, an inverted output voltage Vout is output from an output pin with respect to an input voltage Vin applied from an input pin, and the power supply current Idd at this time is non-defective. FIG.
As shown in (b), a pulse waveform appears at the rising edge and the falling edge of the input voltage. During this pulse waveform, the current (quiescent power supply current) Iddq is 0 [A].

On the other hand, when the NMOS transistor of the CMOS circuit has a failure as shown in FIG. 8C and the CMOS circuit is defective, the power supply current Idd rises as shown in FIG. The predetermined current Iddq is also provided between the pulse waveforms appearing at the edge and the falling edge, respectively.
Flows and does not become 0 [A]. By detecting this, a defective product can be found.

This Iddq test can detect a fault that cannot be expressed by the stuck-at fault model and a fault in the redundant circuit, such as a gate oxide film short circuit and a bridge fault, so that a fault detection rate is high and fault information inside the circuit is output to the output pin. Because there is no need to propagate, it is easy to generate test patterns,
Another feature is that there is almost no area overhead due to the test circuit.

Therefore, according to the multi-chip module 1a of this embodiment, the microcomputer chip 4 whose power supply current is reduced by stopping the clock during standby or operation.
By assigning the same potential power supply pins Vcc1 and Vcc2 of the flash memory chip 2 and the SRAM chip 3 which do not decrease to different terminals, the microcomputer chip 4
Since the ddq test can be performed, the quality of the multi-chip module 1a can be improved.

Third Embodiment FIG. 9 is a schematic functional configuration diagram showing a semiconductor device according to a third embodiment of the present invention.

As in the first and second embodiments, the semiconductor device of the present embodiment has a multi-chip module in which a plurality of chips having different functions are mounted, and these plurality of chips are modularized and packaged. 1
b, and the difference from the first and second embodiments is that, similar to the second embodiment, the number of chips whose power supply current decreases during standby (standby state) or when the clock is stopped during operation is reduced to one chip. Instead, a plurality is considered.

That is, the multi-chip module 1b of the present embodiment comprises a flash memory chip 2, an SRAM
Chip 3, two microcomputer chips (1) 4a, (2) 4
b and two microcomputer chips 4a and 4b
In common, a power supply voltage having the same potential as the other flash memory chip 2 and the SRAM chip 3 is allocated to different terminals and connected to different power supply pins Vcc1 (Vss1). The number of microcomputer chips is not limited to two.

As in the present embodiment, two microcomputer chips 4a and 4b for which the Iddq test is easy are mounted, and the sum of the currents of the two microcomputer chips 4a and 4b is equal to that of the other flash memory chip 2 and SRAM chip. In a case where the current is sufficiently smaller than the sum of the currents of the three currents, the power supplies of the microcomputer chips 4a and 4b capable of performing the Iddq test may be shared.

Therefore, according to the multi-chip module 1b of the present embodiment, the two microcomputer chips 4a and 4b whose power supply current is reduced by stopping the clock during standby or operation are replaced with the flash memory chip 2, SRA
By commonly allocating to the power supply pin Vcc1 different from the M chip 3, the two microcomputer chips 4a and 4b can perform the Iddq test as in the second embodiment, so that the quality of the multi-chip module 1b is reduced. It can be improved.

Fourth Embodiment FIG. 10 is a schematic functional configuration diagram showing a semiconductor device according to a fourth embodiment of the present invention.

As in the first to third embodiments, the semiconductor device of the present embodiment has a multi-chip module in which a plurality of chips having different functions are mounted, and the plurality of chips are modularized and packaged. 1c. The difference from the first to third embodiments is that similar to the first embodiment, the occurrence of latch-up which may occur to allow a potential difference of a power supply is applied to an interface signal line. The point is to avoid this by inserting a series resistor.

That is, the multi-chip module 1c of the present embodiment comprises a flash memory chip 2, an SRAM
In addition to the chip 3 and the microcomputer chip 4, a plurality of resistors 12
The plurality of resistors 12 are connected in series to an interface signal line between the flash memory chip 2 and the microcomputer chip 4, respectively.

Therefore, according to the multi-chip module 1c of the present embodiment, by inserting the resistor 12 in series with the interface signal line,
In such a case, since the potential difference between the power supply voltage Vcc1 and the power supply voltage Vcc2 is positively allowed, a large current may transiently flow through the terminal when the power is turned on, causing a risk of latch-up. Resistance 12
Can be avoided by connecting.

(Fifth Embodiment) FIG. 11 is a schematic functional configuration diagram showing a semiconductor device according to a fifth embodiment of the present invention.

As in the first to fourth embodiments, the semiconductor device according to the present embodiment has a multi-chip module in which a plurality of chips having different functions are mounted, and the plurality of chips are modularized and packaged. 1d, which is different from the first to fourth embodiments in consideration of a chip having a limited power supply rising waveform and a chip whose power supply current is reduced during standby (standby state) or when the clock is stopped during operation. The point is to do so.

That is, the multi-chip module 1d of the present embodiment comprises a flash memory chip 2, an SRAM
The flash memory chip 2 is composed of a chip 3, a microcomputer chip 4, and the like. The power supply voltage which is the same potential as the other SRAM chip 3 and the microcomputer chip 4 during operation is separated from the flash memory chip 2, and is connected to a different power supply pin Vcc1 (Vss1). ,
In the microcomputer chip 4, the power supply voltage having the same potential as that of the other flash memory chip 2 and the SRAM chip 3 is allocated to a different terminal, and different power supply pins Vcc2 (Vss) are used.
2) is connected.

Therefore, according to the multi-chip module 1d of the present embodiment, the power supply pin Vcc1 of the same potential of the flash memory chip 2 which has a limited power-on rising waveform.
And different power supply waveforms can be applied by allocating the same potential power supply pins Vcc2 of the microcomputer chip 4 whose power supply current decreases by stopping the clock during standby or operation to different terminals. Therefore, a chip requiring a special power supply waveform such as the flash memory chip 2 can be packaged and operated normally in one multi-chip module 1d, and the microcomputer chip 4 can perform the Iddq test. Therefore, the quality of the multi-chip module 1d can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, a multi-chip module including a flash memory chip, an SRAM chip, and a microcomputer chip has been described as an example.
It is not limited to these combinations, but DRA
Combination with other memory chips such as M is also possible, and in particular, the same potential is applied to a chip with a limited rise waveform of the power supply, or a chip whose power supply current is reduced by stopping the clock during standby or operation. The present invention can be widely applied to all multi-chip modules configured to separate power pins.

[0057]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) Different power supply waveforms can be applied by separating power supply pins of the same potential during operation of a chip with a limited power supply rising waveform and a chip with no restriction, so that special power supply waveforms can be applied. Packaging a chip that requires a complex power supply waveform into one multi-chip module,
And it can operate normally.

(2) The Iddq of the former chip is allocated by assigning power pins having the same potential to a chip whose power supply current is reduced by stopping the clock during standby or operation and a chip whose power supply current does not decrease to different power supply terminals. Since the test can be performed, the quality of the multi-chip module can be improved.

(3) A chip having a limited power-supply rising waveform, a chip whose power-supply current is reduced by stopping the clock during standby or operation, and a power-supply rising waveform without limitation. By assigning the same potential power pin to the chip that does not decrease by stopping the clock during standby or operation, to a different power terminal,
Chips requiring special power supply waveforms can be packaged in one multi-chip module and operated normally, and the quality of the multi-chip module can be improved.

(4) According to the above (1) and (3), a chip requiring power supply waveform control can be mounted on one multi-chip module, so that the mounting area of the multi-chip module can be reduced. .

(5) From the above (2) and (3), it is possible to easily test a chip capable of performing an Iddq test on a multi-chip module whose function is extremely complicated and difficult to test. . In particular, Idd
The q test is extremely effective for the present method because no fault propagation is required.

[Brief description of the drawings]

FIG. 1 is a schematic functional configuration diagram illustrating a semiconductor device according to a first embodiment of the present invention;

FIG. 2 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a characteristic diagram illustrating a waveform of a power supply voltage supplied to each chip.

FIG. 3 is a perspective view illustrating an appearance of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a partial cross-sectional view illustrating a structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a plan view showing a substrate surface of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a plan view showing the back surface of the substrate of the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a schematic functional configuration diagram illustrating a semiconductor device according to a second embodiment of the present invention;

FIGS. 8A to 8D are explanatory diagrams illustrating an Iddq test in the semiconductor device according to the second embodiment of the present invention; FIGS.

FIG. 9 is a schematic functional configuration diagram showing a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a schematic functional configuration diagram showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a schematic functional configuration diagram showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a schematic functional configuration diagram showing a memory module which is a premise of the present invention.

FIG. 13 is a schematic functional configuration diagram showing another memory module which is a premise of the present invention.

FIG. 14 is a schematic functional configuration diagram showing a multichip module as a premise of the present invention.

[Explanation of symbols]

 1, 1a, 1b, 1c, 1d Multi-chip module 2 Flash memory chip 3 SRAM chip 4 Microcomputer chip 5 Substrate 6 Resin 7 Lead 8 Wire 9 Chip capacitor 10 Chip resistor 11 Depression 12 Resistance

Claims (5)

[Claims] 1. A semiconductor device comprising a plurality of chips having different logic functions, a first chip having a limited power supply rising waveform, and a second chip having no limited power supply rising waveform. And a power supply pin having the same potential during operation of the first chip and the second chip. 2. A semiconductor device comprising a plurality of chips having different logic functions, wherein a first chip whose power supply current is reduced by a clock stop during standby or operation, and wherein the power supply current is during standby or operation. A second chip that does not decrease when the clock is stopped, wherein power pins of the same potential of the first chip and the second chip are assigned to different power terminals. 3. The semiconductor device according to claim 2, wherein said first chip comprises a plurality of first chips.
Wherein the total sum of the currents of the chips is smaller than the sum of the currents of the other chips, the power supply pins having the same potential of the plurality of first chips are assigned to the same power supply terminal. 4. A semiconductor device comprising a plurality of chips having different logic functions, wherein the first chip is limited in a power-on rising waveform, and a power supply current is reduced by a clock stop during standby or operation. A second chip and a third chip which has no limitation on a rising waveform of the power supply and whose power supply current does not decrease when a clock is stopped during standby or operation; A semiconductor device, wherein power supply pins of the same potential of the second chip and the third chip are assigned to different power supply terminals. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a multi-chip module in which a plurality of chips of a flash memory, a microcomputer, and a general-purpose memory are mounted on a substrate. A semiconductor device characterized by the above-mentioned.