JP2013213753A - Method of testing semiconductor integrated circuit and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an increase in the number of probings and suppress an increase in a circuit scale.SOLUTION: A method of testing a semiconductor integrated circuit 1 that includes input buffers 3a to 3c, which have an ESD protection element 31, and a logic circuit 7 connected to the input buffers 3a to 3c is performed as follows: a clock CLK and test data D0 and D1 for causing the logic circuit 7 to perform a test operation are input to input buffers 3a to 3c, the clock CLK and test data D0 and D1 are supplied to power supply terminals of the input buffers 3a to 3c via the ESD protection element 31, and in response to the supply to the power supply terminals of the input buffers 3a to 3c, signals based on the clock CLK and test data D0 and D1 are output from the input buffers 3a to 3c to the logic circuit 7.

Description

  The present invention relates to a method for testing a semiconductor integrated circuit and a method for manufacturing a semiconductor device, and can be suitably used for, for example, a method for testing a semiconductor integrated circuit having an electrostatic protection element and a method for manufacturing a semiconductor device.

  In a wafer test of a semiconductor device, the probe of the probe card is brought into contact with the pad of the semiconductor wafer (probing or also called a needle stand), so that the test is performed by electrically connecting the semiconductor device and the semiconductor tester. It has been broken.

  In recent years, as the semiconductor process is miniaturized and highly integrated, the pad spacing has become very narrow. Due to the narrow pitch of the pads, it has become difficult to bring the probe into contact with all adjacent pads.

  For example, Patent Document 1 is known as a conventional technique related to a wafer test.

JP 2007-227591 A

  In Patent Document 1, power is supplied through one pad, and a plurality of voltage power supplies are generated from the input power supply inside the semiconductor integrated circuit, thereby preventing an increase in the number of probing.

  However, Patent Document 1 requires a power supply circuit for generating and supplying a plurality of voltages inside the semiconductor integrated circuit.

  For this reason, the conventional technique such as Patent Document 1 has a problem that the circuit scale increases when the number of probing is reduced.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a test method for a semiconductor integrated circuit is a test method for a semiconductor integrated circuit comprising: an input buffer having an electrostatic protection element; and an internal circuit connected to the input buffer. A test operation signal for causing the circuit to perform a test operation is input to the input buffer, the test operation signal is supplied to the power supply terminal of the input buffer via the electrostatic protection element, and in response to supply to the power supply terminal of the input buffer Then, a signal based on the test operation signal is output from the input buffer to the internal circuit.

  According to an embodiment, a test method for a semiconductor integrated circuit is a test method for a semiconductor integrated circuit having a buffer circuit and an electrostatic protection element connected between an input terminal and a power supply terminal of the buffer circuit. A test operation signal for causing the semiconductor integrated circuit to perform a test operation is input to the input terminal of the buffer circuit, and the test operation signal is supplied to the power supply terminal of the buffer circuit via the electrostatic protection element. The buffer circuit is operated.

  According to one embodiment, a method for manufacturing a semiconductor device includes: forming a semiconductor integrated circuit having an input / output power pad, an internal circuit power pad, a signal input pad, and a signal output pad on a semiconductor wafer; The probe is not contacted with the power pad for writing output, the probe is brought into contact with each of the power pad for internal circuit, the signal input pad and the signal output pad, and power is supplied through the power pad for internal circuit. Then, a test operation signal for performing a test operation of an internal circuit of the semiconductor integrated circuit is input via the signal input pad, and the semiconductor integrated circuit inputs / outputs from the signal input pad via an electrostatic protection element. The test operation signal is supplied to the power supply terminal of the buffer, and the test of the internal circuit according to the test operation signal is performed via the signal output pad. Output a test result signal, compare the output test result signal with an expected value, determine whether the semiconductor integrated circuit is non-defective / defective, and package the semiconductor integrated circuit determined to be non-defective in a semiconductor device Then, a package test is performed on the packaged semiconductor device.

  According to the one embodiment, an increase in the number of probing can be suppressed and an increase in circuit scale can be suppressed.

3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. 1 is a diagram illustrating a configuration of a semiconductor wafer and a semiconductor integrated circuit according to a first embodiment. 1 is a diagram showing a configuration of a system for testing a semiconductor wafer according to a first embodiment. FIG. 3 is a diagram showing a connection relationship during probing of the semiconductor integrated circuit according to the first embodiment. 6 is a diagram showing a state of bonding pads during a wafer test according to the first embodiment. FIG. 6 is a diagram showing a state of bonding pads during a wafer test according to the first embodiment. FIG. 4 is a diagram showing a connection relationship after bonding of the semiconductor device according to the first embodiment. FIG. FIG. 3 is a diagram showing a state of a bonding pad after bonding according to the first embodiment. FIG. 3 is a diagram showing a state of a bonding pad after bonding according to the first embodiment. 3 is a diagram illustrating a premise example for explaining a circuit configuration of an input / output buffer of the semiconductor integrated circuit according to the first embodiment; FIG. 3 is a diagram showing a circuit configuration of an input buffer of the semiconductor integrated circuit according to the first embodiment. FIG. 3 is a diagram showing a circuit configuration of an output buffer of the semiconductor integrated circuit according to the first embodiment. FIG. 2 is a diagram showing a circuit configuration of an input / output buffer of the semiconductor integrated circuit according to the first embodiment. FIG. 4 is a timing chart showing a test operation of the semiconductor integrated circuit according to the first embodiment. 5 is a diagram showing a circuit configuration of an input / output buffer of a semiconductor integrated circuit according to a second embodiment. FIG. 6 is a timing chart showing a test operation of the semiconductor integrated circuit according to the second embodiment. FIG. 10 is a diagram showing a system configuration of a display system including a semiconductor device according to a third embodiment. FIG. 10 is a diagram showing a circuit configuration of an input / output buffer of a semiconductor device according to a third embodiment. 10 is a timing chart showing input / output operations of the semiconductor device according to the third embodiment.

(Embodiment 1)
The first embodiment will be described below with reference to the drawings. FIG. 1 shows a flow of a method for manufacturing a semiconductor device according to the first embodiment. A method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

  First, as a pre-stage of the wafer test, a semiconductor wafer to be subjected to the wafer test is created (S101 in FIG. 1). That is, a semiconductor wafer is prepared, and a semiconductor integrated circuit including desired circuit elements and pads is formed on the main surface of the semiconductor wafer.

  FIG. 2 shows the semiconductor wafer 100 and the semiconductor integrated circuit 1 to be created. As shown in FIG. 2, the main surface of the semiconductor wafer 100 is partitioned into a plurality of semiconductor chip regions 101. In each semiconductor chip region 101, the semiconductor integrated circuit 1 that becomes the semiconductor chip 10 after dicing is formed.

  The semiconductor integrated circuit 1 is a digital LSI, and includes a bonding pad 2, an input / output buffer 3, a VDD_IO wiring 4, a VDD_CORE wiring 5, a GND wiring 6, and a logic circuit 7 as main components. The configuration of the semiconductor integrated circuit 1 is an example, and the number and layout of each configuration are not limited to the configuration shown in FIG.

  In the peripheral region of the semiconductor integrated circuit 1, a plurality of input / output buffers 3 and bonding pads 2 are arranged along each side of the semiconductor integrated circuit 1. Further, in the peripheral region of the semiconductor integrated circuit 1, a VDD_IO wiring 4, a VDD_CORE wiring 5, and a GND wiring 6 extend so as to go around the peripheral region. Further, a logic circuit 7 is formed in the central region of the semiconductor integrated circuit 1.

  The bonding pad 2 is an external terminal of the semiconductor integrated circuit 1 and is in contact with the probe as a probing target during wafer testing, and a bonding wire is bonded as a bonding target during packaging.

  Here, as the power supply pads, the bonding pad 2 is a GND pad 2a for supplying GND, a VDD_CORE pad 2b for supplying VDD_CORE (internal circuit power, core power), and VDD_IO ( A VDD_IO pad 2c for supplying input / output power) is included. VDD_CORE is a power source for operating an internal circuit such as the logic circuit 7. VDD_IO is a power source for operating the input / output buffer 3 to input / output signals to / from the outside. For example, VDD_IO is 3.3V and VDD_CORE is 1.2V.

  The bonding pad 2 includes a CLK pad 2d for supplying a clock CLK, a D_IN pad 2e for inputting test data, and a D_OUT pad (signal for outputting a test result) as test pads. Output pad) 2f is included. The clock CLK is a signal related to the operation timing of the internal circuit of the semiconductor integrated circuit, and the test data (test signal) is a signal related to the test result (output value) of the internal circuit. A signal for performing a test operation on the internal circuit of the semiconductor integrated circuit including the clock CLK and test data (test signal) is referred to as a test operation signal. The CLK pad 2d and the D_IN pad 2e are signal input pads for inputting a test operation signal. Note that these pads can be used not only during testing but also during normal operation.

  The input / output buffer 3 is connected to the bonding pad 2 and also to the internal logic circuit 7, and performs input / output of signals between the external device of the semiconductor integrated circuit 1 and the internal logic circuit 7. . In particular, since signal input / output VDD_IO and logic circuit VDD_CORE are different, signal level conversion is performed in accordance with the power supply voltage.

  The VDD_IO wiring 4 is connected to the VDD_IO pad 2 c and supplies VDD_IO supplied from the outside to the input / output buffer 3. As will be described later, in this embodiment, the VDD_IO wiring 4 supplies VDD_IO in accordance with a signal input to the input / output buffer 3.

  The VDD_CORE wiring 5 is connected to the VDD_CORE pad 2 b and supplies VDD_IO supplied from the outside to the logic circuit 7 and the input / output buffer 3. The GND wiring 6 is connected to the GND pad 2 a and supplies an external GND potential to the logic circuit 7 and the input / output buffer 3.

  The logic circuit (internal circuit) 7 is a digital circuit inside the semiconductor integrated circuit 1 and includes a plurality of logic circuits in order to realize the function of the semiconductor integrated circuit. The logic circuit 7 operates at the timing of the clock CLK input via the input / output buffer 3, performs a logical operation on the data input via the input / output buffer 3, and outputs the result via the input / output buffer 3 to the outside. Output to.

  After the semiconductor wafer 100 including the semiconductor integrated circuit 1 is created in this manner, subsequently, a wafer test is performed on the semiconductor wafer 100 in order to determine whether the wafer is good or defective (S102 in FIG. 1). In the wafer test, generally, a DC test for testing DC characteristics of an input / output buffer or the like and a function test for testing a functional operation of a logic circuit or the like are performed. In the present embodiment, only the function test is performed in the wafer test, and the DC test is performed in the package test. Thereby, the test time can be shortened.

  FIG. 3 shows a system configuration for carrying out this wafer test. As shown in FIG. 3, the test system for performing a wafer test performs a test by inputting / outputting test signals and the like via a plurality of probes 111 and a plurality of probes 111 that are in contact with the semiconductor wafer 100. A semiconductor tester (logic tester) 120 is provided.

  That is, in the wafer test, the probe card 110 is moved, and the probe 111 is brought into contact with the bonding pad 2 formed on the semiconductor integrated circuit 1 of the semiconductor wafer 100. Then, the semiconductor tester 120 supplies power and a clock to the semiconductor integrated circuit 1 of the semiconductor wafer 100 via the probe 111 and inputs test data, and further outputs a test result output from the semiconductor integrated circuit 1. Measurement is performed to determine whether the function of the semiconductor integrated circuit 1 is normal.

  In this embodiment, probing is performed as shown in FIG. That is, the probe 111 is brought into contact with the GND pad 2a, the VDD_CORE pad 2b, the CLK pad 2d, the D_IN pad 2e, and the D_OUT pad 2f, and the probe 111 is not brought into contact with the VDD_IO pad 2c. Conduct a test. In this embodiment, as described later, the input / output buffer 3 is operated by a signal input from the CLK pad 2d and the D_IN pad 2e, thereby making it unnecessary to supply VDD_IO from the VDD_IO pad 2c. As a result, the number of contact (number of needle holders) between the power supply channel and the probe of the semiconductor tester 120 can be reduced, and more semiconductor integrated circuits 1 can be tested at a time.

  5 and 6 show the state of the bonding pad 2 during the wafer test. 5 shows a cross-sectional view (FIG. 5A) and a plan view (FIG. 5B) of the VDD_CORE pad 2b for probing, and FIG. 6 shows a cross-section of the VDD_IO pad 2c for which probing is not performed. The figure (Fig.6 (a)) and the top view (FIG.6 (b)) are shown.

  As shown in FIG. 5, in the VDD_CORE pad 2b, since the tip of the probe 111 contacts by probing in the probing region 21, the probing scratch 21a is formed on the pad surface. The probe 111 is brought into contact with the VDD_CORE pad 2b, and the tip of the probe 111 presses (or slides or rubs) the pad surface. For this reason, the pad surface for the VDD_CORE 2b has the pad surface scraped by the tip of the probe 111 to form a recess 21b, and the pad surface rises adjacent to the recess 21b to form a protrusion 21c.

  On the other hand, as shown in FIG. 6, since the VDD_IO pad 2 c does not perform probing, no probing scratch 21 a is formed in the probing region 21. Therefore, the VDD_IO pad 2c has a planar shape with no scratches or irregularities on the surface, and is flush with the surface. Details of other wafer tests will be described later.

  When the wafer test is performed as described above, the result of the wafer test is determined (S103 in FIG. 1), the semiconductor integrated circuit 1 determined to be defective is excluded, and the semiconductor integrated circuit 1 determined to be non-defective is hereinafter described. The process is performed. That is, in S102, a function test is performed, and the test result output from the semiconductor integrated circuit 1 is compared with the expected value against the input test data. If the test result matches the expected value, it is determined as a non-defective product. If they do not match, it is judged as a defective product.

  Subsequently, the semiconductor integrated circuit 1 that has become non-defective in the wafer test is packaged to produce the semiconductor device 11 (S104 in FIG. 1). That is, by dicing, the semiconductor wafer 100 is cut into the semiconductor chip regions 101 and fragmented into the semiconductor chips 10. Next, the semiconductor chip 10 is bonded and fixed to the wiring board (die pad) by die bonding. Next, the pads 2 of the semiconductor chip 10 and the external terminals (lead frames) of the wiring substrate are electrically connected via bonding wires by wire bonding. Furthermore, the semiconductor device 11 is produced by resin-sealing the semiconductor chip 10 and the wiring board.

  FIG. 7 shows the connection relationship of bonding wires in the formed semiconductor device 11. As shown in FIG. 7, the bonding pads 2 of the semiconductor chip 10 are connected to external terminals 130 for connection to the outside of the semiconductor device 11 via bonding wires 131. That is, the GND pad 2a, the VDD_CORE pad 2b, the VDD_IO pad 2c, the CLK pad 2d, the D_IN pad 2e, and the D_OUT pad 2f are all bonded and connected to the external terminal 130 by the bonding wire 131. Here, the VDD_IO pad 2c not probed in the wafer test is also bonded.

  8 and 9 show the state of the bonding pad 2 after wire bonding. FIG. 8 shows a cross-sectional view (FIG. 8A) and a plan view (FIG. 8B) of the VDD_CORE pad 2b that was the probing target, and FIG. 9 shows the VDD_IO pad 2c that was not the probing target. A sectional view (FIG. 9A) and a plan view (FIG. 9B) are shown.

  As shown in FIG. 8, in the VDD_CORE pad 2b, the probing scratch 21a is formed in the probing region 21 as described in FIG. In the VDD_CORE pad 2b, the bonding wire 131 is bonded to the bonding region 22 where the probing scratch 21a is not formed. A bonding ball 131 a of the bonding wire 131 is bonded to the pad surface of the bonding region 22 by thermocompression bonding. That is, the VDD_CORE pad 2b has a probing area 21 where a probing scratch 21a is formed by probing during a wafer test, and a bonding area 22 where a bonding wire 131 is bonded.

  On the other hand, as shown in FIG. 9, the VDD_IO pad 2c has no probing scratches 21a formed in the probing region 21 as described in FIG. The bonding wire 131 is bonded to the bonding region 22 of the VDD_IO pad 2c. A bonding ball 131 a of the bonding wire 131 is bonded to the pad surface of the bonding region 22 by thermocompression bonding. That is, the VDD_IO pad 2c has a planar probing region 21 that is not probed during a wafer test and a bonding region 22 to which the bonding wire 131 is bonded. Since the probing scratch is not formed in the VDD_IO pad 2c, bonding may be performed to an arbitrary region on the pad surface.

  After the semiconductor device 11 on which the semiconductor chip 10 (semiconductor integrated circuit 1) is mounted as described above, a package test is subsequently performed on the packaged semiconductor device 11 (S105 in FIG. 1). A DC test that is not performed in the wafer test is performed. That is, the external terminal 130 of the semiconductor device 11 is connected to the semiconductor tester, and the final test of the semiconductor device 11 is performed. The semiconductor tester supplies power and a clock to the semiconductor device 11 and inputs a test signal to measure the level of an output value output from the semiconductor device 11. Here, it is necessary to supply a driving voltage sufficient for performing the DC test, and VDD_CORE is supplied from the external terminal 130 through the VDD_CORE pad 2b and VDD_IO is supplied through the CLK pad 2d.

  When the package test is performed as described above, the result of the package test is determined (S106 in FIG. 1), the semiconductor device determined to be defective is excluded, and the semiconductor device determined to be non-defective is the final product. The manufacturing process is completed.

  Next, the wafer test of the semiconductor integrated circuit according to the present embodiment will be further described with reference to FIGS.

  FIG. 10 shows a configuration of a premise example for explaining the present embodiment. The circuit configuration in the semiconductor integrated circuit of FIG. 10 is the same as that of the present embodiment, that is, the configuration of the input / output buffer 3 of the semiconductor integrated circuit 1 of FIG.

  As shown in FIG. 10, in the semiconductor integrated circuit 1, the GND pad 2 a is connected to the GND wiring 6, the VDD_CORE pad 2 b is connected to the VDD_CORE wiring 5, and the VDD_IO pad 2 c is connected to the VDD_IO wiring 4. . The semiconductor integrated circuit 1 includes a plurality of input / output buffers 3, and illustrates input buffers 3a to 3c and an output buffer 3d (any one of the input buffer and the output buffer is referred to as an input / output buffer). The VDD_IO wiring 4, the VDD_CORE wiring 5, and the GND wiring 6 are commonly connected to the input buffers 3a to 3c and the output buffer 3d, and are supplied with power.

  The input / output buffer 3 includes ESD (Electro Static Discharge) protection elements 31 and 32 and a buffer circuit 33. The buffer circuit 33 is a level shifter that is supplied with VDD_IO and VDD_CORE and performs level conversion (level shift) between a VDD_IO level signal and a VDD_CORE level signal.

  The input buffers 3 a to 3 c convert a signal input at the VDD_IO level from the semiconductor tester 120 during the wafer test into a signal at the VDD_CORE level and output it to the logic circuit 7. The clock CLK is supplied to the logic circuit 7 through the input buffer 3a, and the test data D0 and D1 are input to the logic circuit 7 through the input buffers 3b and 3c. Note that a plurality of test signals necessary for testing the logic circuit 7 are input as test data. Here, as an example, two test data D0 and D1 are input. The input buffers 3a to 3c are buffers for inputting a test operation signal including a clock CLK and test data.

  Further, the output buffer 3d converts the signal input at the VDD_CORE level from the logic circuit 7 into a signal at the VDD_IO level and outputs the signal to the semiconductor tester 120. The test result is output from the logic circuit 7 to the semiconductor tester 120 through the output buffer 3d by the input of the clock CLK and the test data D0 and D1.

  FIG. 11 shows a circuit configuration of the input buffer 3a. Since the input buffers 3a to 3c have the same circuit configuration, the input buffer 3a will be described.

  The input buffer 3a is connected in order of ESD protection elements 31 and 32 and a buffer circuit 33 from the input side to the output side. The ESD protection elements 31 and 32 are diodes for ESD protection and prevent the buffer circuit 33 from being destroyed by an overvoltage signal input from the outside.

  The ESD protection elements 31 and 32 are connected in series between VDD_IO and GND. The cathode of the ESD protection element 31 is connected to VDD_IO, the anode of the ESD protection element 31 and the cathode of the ESD protection element 31 are connected to each other, and the anode of the ESD protection element 32 is connected to GND. A node 30 between the anode of the ESD protection element 31 and the cathode of the ESD protection element 32 is an input terminal of the input buffer 3a.

  When a signal having a voltage higher than VDD_IO is input, a current flows from the node 30 to the VDD_IO wiring 4 through the ESD protection element 31. Further, when a signal having a voltage higher than the clamp voltage is input, the ESD protection element 32 becomes conductive due to the avalanche effect, and a current flows from the node 30 to the GND wiring 6. This prevents an overvoltage from being input to the buffer circuit 33.

  In the input buffer 3a, the node 30 is connected to the CLK pad 2d. In the input buffer 3b, the node 30 is connected to the D_IN pad 2e to which the test data D0 is input. In the input buffer 3c, the node 30 is connected to the D_IN pad 2e to which the test data D1 is input. Yes.

  The buffer circuit 33 is a CMOS buffer composed of a CMOS inverter. The buffer circuit 33 is configured by connecting an inverter circuit 34 and an inverter circuit 35 in series between an input terminal and an output terminal in this order.

  The inverter circuit 34 includes a PMOS transistor 34P and an NMOS transistor 34N connected in series between VDD_IO and GND. That is, the inverter circuit 34 operates by supplying power from the VDD_IO wiring 4 and inputs / outputs a VDD_IO level signal. The inverter circuit 35 includes a PMOS transistor 35P and an NMOS transistor 35N connected in series between VDD_CORE and GND. That is, the inverter circuit 35 operates by supplying power from the VDD_CORE wiring 5 and inputs / outputs a signal at the VDD_CORE level.

  A node between the gate of the PMOS transistor 34P and the gate of the NMOS transistor 34N serves as an input terminal of the buffer circuit 33 and is connected to the node 30. A node between the drain of the PMOS transistor 34P and the source of the NMOS transistor 34N is connected to a node between the gate of the PMOS transistor 35P and the gate of the NMOS transistor 35N. A node between the drain of the PMOS transistor 35P and the source of the NMOS transistor 35N serves as an output terminal of the buffer circuit 33 and the input buffer 3a and is connected to the logic circuit 7. A power supply terminal for operating the inverter circuit 34 is a source of the PMOS transistor 34P to which VDD_IO is supplied. A power supply terminal for operating the inverter circuit 35 is a source of the PMOS transistor 35P to which VDD_CORE is supplied.

  That is, the buffer circuit 33 in FIG. 11 converts (shifts) an input signal at the VDD_IO level into a signal at the VDD_CORE level by serially connecting the inverter circuit 34 operating at the VDD_IO level and the inverter circuit 35 operating at the VDD_CORE level. doing.

  FIG. 12 shows a circuit configuration of the output buffer 3d. In the output buffer 3d, the connection order of the buffer circuit and the ESD protection element is reversed compared to the input buffer 3a, and the buffer circuit 33 and the ESD protection elements 31 and 32 are connected in this order from the input side to the output side. .

  The ESD protection elements 31 and 32 are connected in series between VDD_IO and GND, and prevent the buffer circuit 33 from being destroyed by the input of an overvoltage signal from the outside. A node 30 between the anode of the ESD protection element 31 and the cathode of the ESD protection element 32 is an output terminal of the output buffer 3d, and is connected to the D_OUT pad 2f.

  The buffer circuit 33 has a reverse connection order of the inverter circuit compared to the input buffer 3a, and is configured by connecting the inverter circuit 35 and the inverter circuit 35 in series in this order from the input terminal to the output terminal.

  Similar to the input buffer 3a, the inverter circuit 34 includes a PMOS transistor 34P and an NMOS transistor 34N connected in series between VDD_IO and GND, and the inverter circuit 35 is connected in series between VDD_CORE and GND. A PMOS transistor 35P and an NMOS transistor 35N are provided.

  A node between the gate of the PMOS transistor 35P and the gate of the NMOS transistor 35N serves as an input terminal of the buffer circuit 33 and the output buffer 3d and is connected to the logic circuit 7. A node between the drain of the PMOS transistor 35P and the source of the NMOS transistor 35N is connected to a node between the gate of the PMOS transistor 34P and the gate of the NMOS transistor 34N. A node between the drain of the PMOS transistor 34P and the source of the NMOS transistor 34N serves as an output terminal and is connected to the node 30. A power supply terminal for operating the inverter circuit 35 is a source of the PMOS transistor 35P to which VDD_CORE is supplied. A power supply terminal for operating the inverter circuit 34 is a source of the PMOS transistor 34P to which VDD_IO is supplied.

  That is, the buffer circuit 33 in FIG. 12 converts (shifts) an input signal at the VDD_CORE level into a signal at the VDD_IO level by connecting an inverter circuit 35 operating at the VDD_CORE level and an inverter circuit 34 operating at the VDD_IO level in series. doing.

  In the semiconductor integrated circuit 1 including these input / output buffers, the probes 111 are brought into contact with all the bonding pads 2 and connected to the semiconductor tester 120 in the premise example of FIG. That is, the semiconductor tester 120 supplies VDD_CORE to the VDD_CORE pad 2b, supplies VDD_IO to the VDD_IO pad 2c, supplies the clock CLK to the CLK pad 2d, and supplies test data D0 and D1 to the D_IN pad 2e. To do. The semiconductor tester 120 performs a test by comparing the test result Q output from the D_OUT pad 2f with an expected value.

  In this example, since all the pads 2a to 2f are probed, there is a problem that probing is difficult when the pad pitch is narrow.

  In addition, since two types of power supplies VDD_IO and VDD_CORE are supplied from the semiconductor tester 120, two power supply channels of the semiconductor tester 120 are used. For example, if the power source channel of the semiconductor tester 120 is 16 channels, in the premise example, since 2 channels are used for each semiconductor integrated circuit, the number of semiconductor integrated circuits that can be tested simultaneously is 8. That is, in the premise example, since two types of power supplies are supplied, there is a problem that the number of semiconductor integrated circuits that can be tested in parallel is reduced.

  Therefore, in the present embodiment, as shown in FIG. 4, only VDD_CORE is supplied and a test is performed. FIG. 13 shows the connection relationship during the wafer test of the semiconductor integrated circuit according to the present embodiment. The configuration of the semiconductor integrated circuit 1 in FIG. 13 is the same as that in FIGS.

  In the present embodiment in FIG. 13, the VDD_IO pad 2 c is not probed and opened, and VDD_IO is not supplied from the semiconductor tester 120 to the semiconductor integrated circuit 1 as compared with the premise example in FIG. 10. That is, the semiconductor tester 120 supplies VDD_CORE to the VDD_CORE pad 2b, supplies the clock CLK to the CLK pad 2d, and supplies test data D0 and D1 to the D_IN pad 2e. The semiconductor tester 120 performs a test by comparing the test result Q output from the D_OUT pad 2f with an expected value. As a result, the number of probing can be reduced because no probing is performed on the VDD_IO pad 2c, and only one type of power supply of VDD_CORE can be supplied, so that power supply channels used in the semiconductor tester can be reduced.

  The test operation of the semiconductor integrated circuit according to the present embodiment shown in FIG. 13 will be described with reference to FIG. First, as shown in FIG. 13, 1.2V VDD_CORE is supplied from the semiconductor tester 120 to the semiconductor integrated circuit 1, and VDD_IO is not supplied (OPEN).

  As shown in FIG. 14, in the state ST1, since the clock CLK and the test data D0 and D1 are all at the low level, the high level is not applied to the VDD_IO. Since VDD_IO is at Low level, VDD_IO is not supplied to the inverter circuit 34 of the buffer circuit 33, and the input buffers 3a to 3c and the output buffer 3d do not operate.

  Subsequently, a clock CLK and test data D 0 and D 1 are supplied from the semiconductor tester 120 to the semiconductor integrated circuit 1. The clock CLK and the test data D0 and D1 are signals having a high level of 3.3V. Here, in order to set one of these input signals to the high level, the clock CLK and the test data D0 and D1 are negative logic RZ (Return to Zero) signals, and the test data D0 and D1 At the signal change point, the clock CLK is set to the high level. The RZ signal (Active logic RZ signal) is a digital signal in which “0” is at a low level and “1” is at a high level. A signal that immediately returns to the Low level. The negative logic RZ signal is a digital signal in which “0” is a low level and “1” is a high level. The high level is used as a reference, and when it is “0”, it immediately goes to a low level and immediately goes to a high level. A return signal.

  Because of such a signal, in the states ST2 and ST3, either the clock CLK or the test data D0 and D1 is always at the high level. When any one of the clock CLK and the test data D0 and D1 becomes the high level, the high level is applied to the VDD_IO via the ESD protection element 31 in the input buffers 3a to 3c, respectively. Then, VDD_IO also becomes 3.3V. Therefore, since VDD_IO is supplied to the inverter circuit 34 of the buffer circuit 33, the input buffers 3a to 3c and the output buffer 3d operate normally. In other words, the test operation signal including the clock CLK and the test data is input to the input buffer, the test operation signal is supplied to the power supply terminal of the input buffer via the ESD protection element, and the test operation signal is supplied to the power supply terminal. The input buffer outputs a signal based on the test operation signal.

  That is, by supplying VDD_IO via the ESD protection element 31, the test data D0 is propagated to the logic circuit 7 via the input buffer 3b, the test data D1 is propagated to the logic circuit 7 via the input buffer 3c, Further, the clock CLK is propagated to the logic circuit 7 through the input buffer 3a. The test result Q from the logic circuit 7 is output to the semiconductor tester 120 via the output buffer 3d.

  At this time, the state of the logic circuit 7 is determined at the rising timing of the clock CLK, and the value of the test result Q is also determined. For this reason, the timings T1 and T2 at which the clock CLK is at a high level immediately after the rising of the clock CLK are set as strobe points. That is, the semiconductor tester 120 observes the test result Q at the timings T1 and T2, and performs a test by comparing with the expected value.

  When the clock CLK and the test data D0 and D1 are all at the low level as in the state ST4, the voltage application from the ESD protection element 31 to VDD_IO may stop. Then, a leak current flows from VDD_IO to GND via the ESD protection elements 31 and 32 and the inverter circuit 34 as in the leak current paths A and B shown in FIGS. Then, VDD_IO decreases by this leakage current.

  In the case of the general CMOS inverter shown in FIGS. 11 and 12, for example, even if VDD_IO decreases in a time of 1 uS or less, it does not fall below the threshold voltage of the next stage circuit. In the input buffers 3a to 3c, even if VDD_IO to the inverter circuit 34 decreases, the output of the input buffers 3a to 3c is not affected because it does not fall below the threshold value of the inverter circuit 35 at the next stage. Therefore, even in this case, the clock CLK and the test data D0 and D1 can be accurately propagated to the logic circuit 7.

  Further, in the output buffer 3d, when VDD_IO to the inverter circuit 34 decreases, the output test result Q may become unstable. Since the threshold voltage of the test result Q depends on the determination criterion of the semiconductor tester 120, the timing T3 at which the logic of the test result Q is fixed and VDD_IO is stabilized after the rising of the clock CLK is set as a strobe point. Therefore, even in this case, it is possible to accurately propagate the test result Q from the output buffer 3d and determine the expected value.

  As described above, in the present embodiment, in the function test in the wafer test, only the VDD_CORE is supplied from the semiconductor tester to the semiconductor integrated circuit without supplying the VDD_IO via the pad, thereby enabling the test. Thereby, the number of probing can be reduced, and even when the pad pitch is narrow, probing can be performed with high accuracy. Further, since the number of power supply channels used in the semiconductor tester can be reduced, the number of semiconductor integrated circuits that can be tested in parallel can be increased, and the test can be performed efficiently.

  In the function test, it is only necessary to recognize that the test result is “0” or “1”. Therefore, unlike the DC test in which accurate current / voltage is measured, sufficient drive current and speed are required. Absent. Therefore, according to this embodiment, the function test can be effectively performed without supplying VDD_IO from the semiconductor tester.

  Further, in this embodiment, in a configuration in which there is an input buffer having an ESD protection element connected to the VDD_IO side, an input signal from the semiconductor tester is supplied to the semiconductor integrated circuit through the ESD protection element, so that VDD_IO Test signals can be input and output without requiring a dedicated power supply. As a result, it is not necessary to newly add a circuit for supplying VDD_IO, so that an increase in circuit scale can be prevented.

  In addition, when inputting the clock signal and the test signal to the input buffer, VDD_IO can be supplied via the ESD protection element by inputting either the clock signal or the test signal so as to be at a high level. The buffer can be operated.

  In particular, the clock signal or the like is the negative logic RZ signal, the clock signal is set to the high level at the change point of the test signal, and the timing at which the clock signal is at the high level is set to the strobe point (expected value determination point). Test can be realized.

  When no high level is input to the clock CLK and the test data D0 and D1, the test result Q, which is the internal output and the external output of the logic circuit 7 in the initial state, has an incorrect logic of high level or low level. May be output. However, since a general CMOS buffer structure is used, if a high level is input to VDD_IO even once from the initial state, if the signal does not change, the current path to GND is only the leak current path, and therefore, for a certain time (buffer Although it depends on the structure / ambient conditions, it is usually several uS or higher), and can maintain a high level that is equal to or higher than the threshold voltage of the circuit in the next stage. Therefore, as described above, the clock signal or the like is the negative logic RZ signal, the clock signal is set to the high level at the change point of the test signal, and the timing at which the clock signal is at the high level is set as the strobe point. Since the VDD_IO always becomes a high level at the change point of the external input / external output signal through which the current flows, and the voltage drop of the VDD_IO due to the leakage current can be prevented, the test can be performed accurately.

(Embodiment 2)
The second embodiment will be described below with reference to the drawings. In the first embodiment, the test by supplying only VDD_CORE can be realized by inputting any one of the clock CLK and the test data D0 and D1 to the high level. In the present embodiment, one of the plurality of clocks CLK is input so as to be at a high level.

  FIG. 15 shows the configuration of the semiconductor integrated circuit according to the present embodiment during the wafer test. In FIG. 15, as an example of testing by inputting a plurality of clocks CLK, a test result Q11 is output according to the clock CLK11 and the test data D11, and a test result Q12 is output according to the clock CLK12 and the test data D12. Is shown. The circuit configuration of the input / output buffer and the like is the same as that shown in FIGS.

  As shown in FIG. 15, in the semiconductor integrated circuit 1, the GND pad 2 a is connected to the GND wiring 6, the VDD_CORE pad 2 b is connected to the VDD_CORE wiring 5, and the VDD_IO pad 2 c is connected to the VDD_IO wiring 4. . The semiconductor integrated circuit 1 includes a plurality of input / output buffers 3. The input buffers 3a-1, 3b-1, the output buffer 3d-1, the input buffers 3a-2, 3b-2, and the output buffer 3d-2 are illustrated. Show. The VDD_IO wiring 4, the VDD_CORE wiring 5, and the GND wiring 6 are commonly connected to the input buffers 3a-1, 3b-1, the output buffer 3d-1, the input buffers 3a-2, 3b-2, and the output buffer 3d-2. Each is supplied with power.

  The input buffer 3 a-1 is connected to the CLK pad 2 d-1, and the clock CLK 11 is input via the CLK pad 2 d-1, level-shifted, and output to the logic circuit 7. The input buffer 3 b-1 is connected to the D_IN pad 2 e-1, and the test data D 11 is input via the D_IN pad 2 e-1, level-shifted and output to the logic circuit 7. The output buffer 3d-1 is connected to the D_OUT pad 2f-1, shifts the level of the test result Q11 input from the logic circuit 7, and outputs the result to the semiconductor tester 120 via the D_OUT pad 2f-1.

  Similarly, the input buffer 3 a-2 is connected to the CLK pad 2 d-2, and the clock CLK 12 is input via the CLK pad 2 d-2, level-shifted and output to the logic circuit 7. The input buffer 3b-2 is connected to the D_IN pad 2e-2, and the test data D12 is input through the D_IN pad 2e-2, and the level is shifted and output to the logic circuit 7. The output buffer 3d-2 is connected to the D_OUT pad 2f-2, level-shifts the test result Q12 input from the logic circuit 7, and outputs the result to the semiconductor tester 120 via the D_OUT pad 2f-2.

  In FIG. 15, as in FIG. 13, the VDD_IO pad 2 c is not probed and is opened, and VDD_IO is not supplied from the semiconductor tester 120 to the semiconductor integrated circuit 1.

  That is, the semiconductor tester 120 supplies VDD_CORE to the VDD_CORE pad 2b, supplies the clock CLK11 to the CLK pad 2d-1, and supplies test data D11 to the D_IN pad 2e-1. Then, the semiconductor tester 120 performs a test by comparing the test result Q11 output from the D_OUT pad 2f-1 with an expected value.

  The semiconductor tester 120 supplies the clock CLK12 to the CLK pad 2d-2 and supplies the test data D12 to the D_IN pad 2e-2. Then, the semiconductor tester 120 performs a test by comparing the test result Q12 output from the D_OUT pad 2f-2 with the expected value.

  The test operation of the semiconductor integrated circuit according to the present embodiment shown in FIG. 15 will be described with reference to FIG. First, as shown in FIG. 15, 1.2V VDD_CORE is supplied from the semiconductor tester 120 to the semiconductor integrated circuit 1, and VDD_IO is not supplied (OPEN).

  As shown in FIG. 16, in the state ST1, since the clocks CLK11 and CLK12 and the test data D11 and D12 are all at the low level, the high level is not applied to VDD_IO. Since VDD_IO is at the low level, the input buffers 3a-1, 3b-1, the output buffer 3d-1, the input buffers 3a-2, 3b-2, and the output buffer 3d-2 do not operate.

  Subsequently, clocks CLK11 and CLK12 and test data D11 and D12 are supplied from the semiconductor tester 120 to the semiconductor integrated circuit 1. The clocks CLK11 and CLK12 and the test data D11 and D12 are signals having a high level of 3.3V. Here, in order to set one of these input signals to the high level, in this embodiment, the clocks CLK11 and CLK12 are exclusively set to the high level. For example, the clock CLK11 may be a negative RZ signal and the clock CLK11 may be an active RZ signal.

  Since such a signal is used, in the states ST2 to ST4, one of the clocks CLK11 and CLK12 is always at a high level. When either of the clocks CLK11 and CLK12 becomes High level, each of the input buffer 3a-1, 3b-1, the output buffer 3d-1, the input buffer 3a-1, 3b-1, and the output buffer 3d-1, A high level is applied to VDD_IO via 31. Then, VDD_IO also becomes 3.3V. Therefore, the input buffers 3a to 3c and the output buffer 3d operate normally.

  That is, by supplying VDD_IO via the ESD protection element 31, the test data D11 is propagated to the logic circuit 7 via the input buffer 3b-1, and the clock CLK11 is further transmitted to the logic circuit via the input buffer 3a-1. 7 is propagated. The test result Q11 from the logic circuit 7 is output to the semiconductor tester 120 via the output buffer 3d-1.

  At this time, the state of the logic circuit 7 is determined at the rising timing of the clock CLK11, and the value of the test result Q11 is also determined. Therefore, timings T11, T12, and T13 immediately after the rising edge of the clock CLK11 are set as strobe points. In this embodiment, since either of the clocks CLK11 and CLK12 is at a high level, an arbitrary timing immediately after the rising of the clock CLK11 can be set as a strobe point.

  Further, when VDD_IO is supplied via the ESD protection element 31, the test data D12 is propagated to the logic circuit 7 via the input buffer 3b-2, and the clock CLK12 is further transmitted to the logic circuit via the input buffer 3a-2. 7 is propagated. The test result Q12 from the logic circuit 7 is output to the semiconductor tester 120 via the output buffer 3d-2.

  At this time, the state of the logic circuit 7 is determined at the rising timing of the clock CLK12, and the value of the test result Q12 is also determined. Therefore, timings T21, T22, and T23 immediately after the rising edge of the clock CLK12 are set as strobe points. In this embodiment, since either of the clocks CLK11 and CLK12 is at a high level, an arbitrary timing immediately after the rising of the clock CLK12 can be set as a strobe point.

  In FIG. 14 of the first embodiment, when the clock CLK and the test data D0 and D1 are at the low level, VDD_IO is reduced by the amount of the leakage current. In this embodiment, since any one of the clocks CLK11 and CLK12 is always at a high level, there is no possibility that VDD_IO decreases as in the first embodiment. In the first embodiment, it is necessary to set the clock CLK to the high level at the change point of the test data. However, in this embodiment, it is not necessary to consider such a restriction.

  As described above, in this embodiment, as in the first embodiment, only VDD_CORE is supplied from the semiconductor tester, and VDD_IO is supplied via the ESD protection by the input signal, thereby enabling the test to be performed. The number of probing can be reduced, the number of channels used by the semiconductor tester can be reduced, and the increase in circuit scale can be prevented.

  In the present embodiment, the clock signal is exclusively set to the high level in the configuration in which a plurality of clock signals are input. Accordingly, since any one of the clock signals is always at a high level, VDD_IO can be stably supplied, and the test can be reliably performed.

(Embodiment 3)
The third embodiment will be described below with reference to the drawings. In the first and second embodiments, examples relating to input / output of signals between the semiconductor integrated circuit and the semiconductor tester during the wafer test have been mainly described. In this embodiment, an example of input / output of signals between semiconductor devices during normal operation will be described.

  FIG. 17 shows a configuration of the display system according to the present embodiment. As shown in FIG. 17, the display system 200 includes a CPU 210, a display controller 220, and a display panel 230.

  The CPU 210 is an example of a one-chip semiconductor device, generates display data by executing a program, and outputs the generated display data to the display controller 220. The CPU 210 and the display controller 220 are connected via an LVDS interface 241 and an SPI interface 242. The LDVS interface 241 is a high-speed differential interface, and inputs and outputs large display data at high speed. The SPI interface 242 is a low-speed serial interface, and inputs / outputs a small size command or the like at a low speed.

  The display controller 220 is an example of a one-chip semiconductor device, and receives display data from the CPU 210 and outputs a drive signal corresponding to the display data. The display controller 220 and the display panel 230 are connected via an LDVS interface 243. The LDVS interface 243 is a high-speed differential interface, and inputs and outputs drive signals at high speed.

  The display panel 230 drives the display pixels according to the drive signal supplied from the display controller 220 to perform a desired display. The display panel 230 is, for example, a liquid crystal display panel, a plasma display panel, an organic EL display panel, or the like.

  The internal configuration of the CPU 210 and the display controller 220 will be described. The CPU 210 includes a logic circuit 211, an LVDS input / output circuit 212, an SPI input / output circuit 213, and a regulator circuit 214.

  The logic circuit 211 is a core part of the CPU, and includes a plurality of logic circuits in order to realize the function of the CPU 210. The LVDS input / output circuit 212 is an input / output buffer for inputting / outputting data via the LVDS interface 241. The SPI input / output circuit 213 is an input / output buffer for inputting / outputting data via the SPI interface 242. Based on the power supplied from the power supply circuit 215, the regulator circuit 214 generates VDD_CORE for operating the logic circuit 211 and VDD_IO for operating the LVDS input / output circuit 212 and the SPI input / output circuit 213. Supply to the circuit.

  The display controller 220 includes a logic circuit 221, an LVDS input / output circuit 222, an SPI input / output circuit 223, a regulator circuit 224, and an LVDS input / output circuit 225.

  The logic circuit 221 is a core unit of the display controller, and includes a plurality of logic circuits in order to realize the function of the display controller 220. The LVDS input / output circuit 222 is an input / output buffer for inputting / outputting data via the LVDS interface 241. The LVDS input / output circuit 225 is an input / output buffer for inputting / outputting data via the LVDS interface 243. The SPI input / output circuit 223 is an input / output buffer for inputting / outputting data via the SPI interface 242. Based on the power supplied from the power supply circuit 215, the regulator circuit 224 is configured to operate VDD_CORE for operating the logic circuit 221 and for operating the LVDS input / output circuit 222, the LVDS input / output circuit 225, and the SPI input / output circuit 223. VDD_IO is generated and supplied to each circuit.

  FIG. 18 shows a specific example of the SPI input / output circuit 223 of the display controller 220. The circuit configuration of the input / output buffer and the like is the same as that shown in FIGS. Further, the SPI input / output circuit 213 of the CPU 210 may be similarly configured.

  As shown in FIG. 18, in the display controller 220, the GND external terminal 226 a is connected to the GND wiring 6. The GND external terminal 226 a is connected to the power supply circuit 215. In addition, you may connect not only to the power supply circuit 215 but to a power plane.

  The VDD_CORE external terminal 226 b is connected to the input of the regulator circuit 224, and the VDD_CORE wiring 5 is connected to the output of the regulator circuit 224. Further, the VDD_CORE external terminal 226 b is connected to the power supply circuit 215. In addition, you may connect not only to the power supply circuit 215 but to a power plane. For example, a voltage of 5V is supplied from the power supply circuit 215, the regulator circuit 224 generates a voltage of 1.2V, and supplies VDD_CORE of 1.2V to the VDD_CORE wiring 5.

  The SPI input / output circuit 223 includes a plurality of input / output buffers 3 and illustrates input buffers 3a and 3b and an output buffer 3d. The VDD_IO wiring 4, the VDD_CORE wiring 5, and the GND wiring 6 are commonly connected to the input buffers 3a, 3b, and the output buffer 3d, and are supplied with power.

  The input buffer 3a is connected to the CLK external terminal 226d. The clock CLK is input from the CPU 210 via the SPI interface 242 and the CLK external terminal 226d, and the level is shifted and output to the logic circuit 221. The input buffer 3b is connected to the D_IN external terminal 226e. Input data DATA_IN is input from the CPU 210 via the SPI interface 242 and the D_IN external terminal 226e, and the level is shifted and output to the logic circuit 221. The output buffer 3d is connected to the D_OUT external terminal 226f, shifts the level of the output data DATA_OUT input from the logic circuit 221, and outputs it to the CPU 210 via the D_OUT external terminal 226f and the SPI interface 242.

  In the present embodiment, the supply of VDD_IO from the outside is unnecessary as in the first and second embodiments. Here, the VDD_IO wiring 4 is not connected to any external terminal. That is, the power supply circuit 215 and the regulator circuit 224 supply VDD_CORE to the VDD_CORE wiring 5, and the CPU 210 supplies the clock CLK to the CLK external terminal 226d and supplies the input data DATA_IN to the D_IN external terminal 226e. The display controller 220 receives DATA_IN, and the CPU 210 further receives output data_IN output from the D_OUT external terminal 226f.

  The input / output operation of the SPI input / output circuit 223 according to the present embodiment shown in FIG. 18 will be described with reference to FIG. First, as shown in FIG. 18, 5V power is supplied from the power supply circuit 215 to the regulator circuit 224, 1.2V VDD_CORE is supplied from the regulator circuit 224, and VDD_IO is not supplied.

  As shown in FIG. 19, in the state ST1, since the clock CLK and the input data DATA_IN are all at the low level, the high level is not applied to the VDD_IO. Since VDD_IO is at the low level, the input buffers 3a to 3b and the output buffer 3d do not operate.

  Subsequently, the clock CLK and the input data DATA_IN are input from the CPU 210 to the display controller 220. The clock CLK and the input data DATA_IN are signals having a high level of 3.3V.

  In the states ST2 to ST4, when either the clock CLK or the input data DATA_IN becomes a high level, the high level is applied to the VDD_IO in the input buffers 3a to 3b via the ESD protection elements 31, respectively. Then, VDD_IO also becomes 3.3V. Therefore, the input buffers 3a to 3b and the output buffer 3d operate normally.

  That is, when VDD_IO is supplied via the ESD protection element 31, the input data DATA_IN is propagated to the logic circuit 221 via the input buffer 3b, and further, the clock CLK is propagated to the logic circuit 221 via the input buffer 3a. The Further, the output data DATA_OUT from the logic circuit 221 is output to the CPU 210 via the output buffer 3d.

  In general, in an SPI interface receiver, data is input at the falling timing of the clock CLK, and the data is taken into an internal circuit at the rising timing of the clock CLK. Similarly, in this embodiment, DATA0 to DATA2 are input at the falling timing of the clock CLK in the states ST2 to ST4. Then, at the timings T31 to T33 when the clock CLK rises, the logic circuit 221 takes in DATA0 to DATA2 and processes the data. If the clock CLK is at a high level, the input buffers 3a to 3b operate, so that data can be accurately taken in at timings T31 to T33.

  Depending on the data, the low level of the input data DATA_IN may continue. In this case, voltage application from the ESD protection element 31 to VDD_IO stops. However, as in FIG. 14, VDD_IO can accurately propagate the input data DATA_IN to the logic circuit 221 because only the voltage drop due to the leakage current occurs.

  As described above, in the present embodiment, the principles of the first and second embodiments are applied to the communication interface between semiconductor devices. Also in the communication interface, only VDD_COR is supplied, and VDD_IO is supplied via ESD protection by an input signal, thereby enabling signal input. In this embodiment, since the power supply operates by connecting only VDD_CORE and GND from the mounting substrate, it is possible to reduce the wiring area of the mounting substrate pattern and to reduce the package pins.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Bonding pad 2a GND pad 2b VDD_CORE pad 2c VDD_IO pad 2d CLK pad 2e D_IN pad 2f D_OUT pad 3 Input / output buffer 3a-3c Input buffer 3d Output buffer 4 VDD_IO wiring 5 VDD_CORE wiring 6 GND wiring 7 Logic circuit 10 Semiconductor chip 11 Semiconductor device 21 Probing area 21a Probing scratch 21b Recess 21c Projection 22 Bonding area 30 Node (input terminal)
31, 32 ESD protection element 33 Buffer circuit 34, 35 Inverter circuit 34N, 35N NMOS transistor 34P, 35P PMOS transistor 100 Semiconductor wafer 101 Semiconductor chip region 110 Probe card 111 Probe 120 Semiconductor tester 130 External terminal 131 Bonding wire 131a Crimp ball 200 Display System 210 CPU
211 Logic circuit 212 LVDS input / output circuit 213 SPI input / output circuit 214 Regulator circuit 215 Power supply circuit 220 Display controller 221 Logic circuit 222, 225 LVDS input / output circuit 223 SPI input / output circuit 224 Regulator circuit 226a GND external terminal 226b VDD_CORE external terminal 226d CLK external terminal 226e D_IN external terminal 226f D_OUT external terminal 230 Display panels 241, 243 LVDS interface 242 SPI interface

Claims (19)

A test method for a semiconductor integrated circuit comprising an input buffer having an electrostatic protection element and an internal circuit connected to the input buffer,
A test operation signal for performing a test operation of the internal circuit is input to the input buffer,
Supplying the test operation signal to the power supply terminal of the input buffer via the electrostatic protection element;
In response to supply to the power supply terminal of the input buffer, a signal based on the test operation signal is output from the input buffer to the internal circuit.
A method for testing a semiconductor integrated circuit. The test operation signal includes a clock signal related to an operation timing of the internal circuit and a test signal related to an output value of the internal circuit.
The method for testing a semiconductor integrated circuit according to claim 1. The input buffer operates in response to either the clock signal or the test signal being supplied to a power supply terminal of the input buffer.
The method for testing a semiconductor integrated circuit according to claim 2. The clock signal is a negative zero return zero signal.
4. The method for testing a semiconductor integrated circuit according to claim 2 or 3. The clock signal is a signal that becomes a high level at a timing when the level of the test signal changes.
The method for testing a semiconductor integrated circuit according to claim 2. The semiconductor integrated circuit has an output buffer connected to the internal circuit,
Supplying the test operation signal to the power supply terminal of the output buffer via the electrostatic protection element;
In response to supply to the power supply terminal of the output buffer, a signal based on the output signal of the internal circuit is output,
Determining the output value of the output buffer at a timing when the test operation signal is at a high level;
6. A method for testing a semiconductor integrated circuit according to claim 1. The semiconductor integrated circuit has an output buffer connected to the internal circuit,
Supplying the test operation signal to the power supply terminal of the output buffer via the electrostatic protection element;
In response to supply to the power supply terminal of the output buffer, a signal based on the output signal of the internal circuit is output,
Determining the output value of the output buffer at a timing when the clock signal is at a high level;
6. The method for testing a semiconductor integrated circuit according to claim 2. The semiconductor integrated circuit has an input / output power line and an internal circuit power line,
The test operation signal is supplied to the power supply terminal of the input buffer via the input / output power supply line.
The method for testing a semiconductor integrated circuit according to claim 1. The electrostatic protection element is a diode connected between an input terminal of the input buffer and the input / output power line;
The method for testing a semiconductor integrated circuit according to claim 8. The input buffer includes a level shifter connected to the input / output power line and the internal circuit power line.
10. The method for testing a semiconductor integrated circuit according to claim 8 or 9. The level shifter includes a first inverter circuit to which power is supplied from the input / output power line, and a second inverter circuit to which power is supplied from the internal circuit power line.
The method for testing a semiconductor integrated circuit according to claim 10. The semiconductor integrated circuit has an input / output power line and an internal circuit power line,
The output buffer includes a level shifter connected to the input / output power line and the internal circuit power line.
The method for testing a semiconductor integrated circuit according to claim 6. The level shifter includes a first inverter circuit to which power is supplied from the input / output power line, and a second inverter circuit to which power is supplied from the internal circuit power line.
The method for testing a semiconductor integrated circuit according to claim 12. A test method for a semiconductor integrated circuit comprising: a buffer circuit; and an electrostatic protection element connected between an input terminal and a power supply terminal of the buffer circuit,
A test operation signal for causing the semiconductor integrated circuit to perform a test operation is input to an input terminal of the buffer circuit,
Operating the buffer circuit according to the voltage of the test operation signal supplied to the power supply terminal of the buffer circuit via the electrostatic protection element;
A method for testing a semiconductor integrated circuit. A semiconductor integrated circuit having an input / output power pad, an internal circuit power pad, a signal input pad and a signal output pad is formed on a semiconductor wafer;
Non-contacting the probe to the input / output power pad, contacting the probe to each of the internal circuit power pad, the signal input pad and the signal output pad,
Supply power through the internal circuit power pad,
A test operation signal for performing a test operation of the internal circuit of the semiconductor integrated circuit is input via the signal input pad,
The semiconductor integrated circuit supplies the test operation signal from the signal input pad to a power supply terminal of an input / output buffer via an electrostatic protection element,
Via the signal output pad, output a test result signal of the internal circuit according to the test operation signal,
Comparing the output test result signal with an expected value to determine whether the semiconductor integrated circuit is good or defective,
Packaging the semiconductor integrated circuit determined to be non-defective into a semiconductor device;
A package test is performed on the packaged semiconductor device.
A method for manufacturing a semiconductor device. In the packaging, bonding wires for connecting to external terminals of the semiconductor device are bonded to the input / output power pads, the internal circuit power pads, the signal input pads, and the signal output pads,
The method for manufacturing a semiconductor device according to claim 15. In the internal circuit power supply pad, the signal input pad, and the signal output pad, the bonding wire is bonded to a region where the probing scratch formed by contact with the probe is removed,
In the input / output power supply pad that does not have the probing scratch, the bonding wire is bonded to an arbitrary region.
The method for manufacturing a semiconductor device according to claim 16. Determining whether the semiconductor integrated circuit is non-defective or defective is a function test for testing the functional operation of the semiconductor integrated circuit.
18. A method for manufacturing a semiconductor device according to claim 16 or 17. In the package test, a DC test for testing a DC characteristic of the semiconductor integrated circuit is performed.
The method for manufacturing a semiconductor device according to claim 16.

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