JPH11121564A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To see to it that a specified voltage is not applied at a burn-in inspection, to a semiconductor integrated circuit device where the DC defect has become apparent before the burn-in inspection, when the inspection of the semiconductor integrated circuit device on wafer level is performed. SOLUTION: A power voltage adjusting circuit 10 is composed of a first resistor element R1 and a second resistor element R2 , which are connected in series by a common connection 3 between an external power terminal 1 and a ground terminal 2 where external power voltage is applied, a third resistor element R3 whose one end is connected to the external power terminal 1 and whose other end is connected to the common connection 3 via a fuse element 4 for adjustment, and a buffer 5, where a stepped-down voltage Vint produced from the external power voltage stepped down at the common connection 3 is inputted. An internal power voltage generating circuit 20 receives the stepped-down voltage Vint, which serves as the standard for the internal power voltage, being the output voltage from the buffer 5 of the power voltage adjusting circuit 10, and generates the internal power voltage and outputs the potential to an output terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of coping with defective integrated circuits, particularly DC defects, when simultaneously inspecting a plurality of integrated circuits of chips formed on a semiconductor wafer in a wafer state. .

[0002]

2. Description of the Related Art In recent years, there has been remarkable progress in miniaturization and price reduction of electronic equipment equipped with a semiconductor integrated circuit device, and accordingly, demands for miniaturization and price reduction of the semiconductor integrated circuit device have increased. ing.

Normally, in a semiconductor integrated circuit device, after a semiconductor chip and a lead frame are electrically connected by bonding wires, the semiconductor chip is supplied in a state of being sealed with resin or ceramics, and is mounted on a printed circuit board. You. However, due to a demand for miniaturization of electronic equipment, a method of directly mounting a semiconductor integrated circuit device in a state of being cut out from a semiconductor (hereinafter, the semiconductor integrated circuit device in this state is referred to as a bare chip or simply a chip) on a circuit board. It has been desired to supply bare chips with guaranteed quality at a low price.

In order to guarantee the quality of bare chips, it is necessary to burn in the semiconductor integrated circuit device in a wafer state.

[0005] However, burn-in performed collectively in a semiconductor wafer state (hereinafter, referred to as wafer burn-in) is very complicated in handling semiconductor wafers, and cannot meet the demand for cost reduction. In addition, since it takes a lot of time to burn-in by dividing a plurality of bare chips formed on one semiconductor wafer one by one or several times many times, it is not possible in terms of time and cost. Therefore, it is required that all bare chips be simultaneously burned in a wafer state at the same time.

Here, a burn-in device capable of performing a wafer burn-in disclosed in Japanese Patent Application Laid-Open No. Hei 8-5666 will be described.

FIG. 6 shows an overview of a conventional wafer burn-in apparatus. As shown in FIG. 6, a wafer burn-in apparatus 100 includes a rack 110 capable of storing a plurality of wafer cassettes 103 in which a wafer tray 101 and a probe card 102 are decompressed and pressure-bonded to each other, and a vacuum for maintaining a decompressed state of the wafer cassette 103. It comprises a pump 111 and a drive circuit 112 for electrically driving a plurality of semiconductor integrated circuit devices formed on semiconductor wafers held in the wafer cassette 103, respectively.

[0008]

However, in the above-mentioned conventional wafer burn-in apparatus, since power is supplied to a plurality of semiconductor integrated circuit devices at once, a plurality of semiconductor integrated circuit devices are not subjected to a burn-in test. In the case where a DC failure occurs in any one of the semiconductor integrated circuit devices, a large current flows to another semiconductor integrated circuit device, and there is a problem that the inspection cannot be continued.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. When a semiconductor integrated circuit device is inspected at a wafer level, a semiconductor integrated circuit device in which a DC failure is found before a burn-in inspection is subjected to a predetermined time during a burn-in inspection. The first object is to prevent the application of the voltage of the semiconductor integrated circuit device when the DC failure occurs during the burn-in test. And

[0010]

In order to achieve the first object, a first semiconductor integrated circuit device according to the present invention comprises:
A power supply voltage adjustment circuit that steps down an external power supply voltage input from the outside to a predetermined voltage; and an internal power supply voltage generation circuit that generates an internal power supply voltage based on the predetermined voltage. An output switching unit that outputs one of the voltage values equal to or less than half the predetermined voltage;

According to the first semiconductor integrated circuit device, the power supply voltage adjusting circuit for stepping down the external power supply voltage inputted from the outside to the predetermined voltage includes the power supply voltage adjusting circuit for controlling the predetermined voltage and the voltage equal to or less than half of the predetermined voltage. Since it has an output switching unit that outputs one of the voltage values, for example, it is determined that a DC failure has occurred in a pre-probe inspection process before a burn-in inspection among a plurality of semiconductor integrated circuit devices. In the burn-in inspection process, the output switching unit can be set in advance so that the semiconductor integrated circuit device outputs a voltage value that is equal to or less than half the predetermined voltage.

In the first semiconductor integrated circuit device, it is preferable that the output switching section comprises a fuse element.

In order to achieve the second object, a second semiconductor integrated circuit device according to the present invention outputs a good product identification signal indicating that the product is good when a predetermined voltage value or current value is satisfied. On the other hand, when a predetermined voltage value or current value is not satisfied, a detection circuit that outputs a defective product identification signal indicating a defective product, and a mode identification signal indicating a normal operation mode or an inspection mode are received. In some cases, a signal switching circuit for outputting a good product identification signal or a defective product identification signal is provided.

According to the second semiconductor integrated circuit device of the present invention, when the detection circuit satisfies the predetermined voltage value or current value, the detection circuit outputs the non-defective product identification signal indicating that the product is non-defective, while the predetermined voltage value Or, when the current value is not satisfied, a defective product identification signal indicating a defective product is output, and
The signal switching circuit receives a mode identification signal indicating a normal operation mode or an inspection mode, and outputs a non-defective product identification signal or a defective product identification signal in the inspection mode. Since the semiconductor integrated circuit device in which the DC failure has occurred outputs a defective product identification signal indicating the occurrence of the DC failure, the external device can detect the defective product identification signal.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1A shows a circuit configuration of a power supply voltage adjusting circuit and an internal power supply voltage generating circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention. The semiconductor integrated circuit device according to the present embodiment is an integrated circuit device having an internal power supply voltage generation circuit for generating an internal power supply voltage by stepping down an external power supply in order to achieve low power consumption and high speed operation like a memory element Is assumed.

As shown in FIG. 1A, a power supply voltage adjusting circuit 10 is provided at a common connection portion 3 between an external power supply terminal 1 to which an external power supply voltage is applied and a ground terminal 2 at an external power supply terminal 1 side. A first resistance element R ₁ and a second resistance element R ₂ connected in series in this order, and one end connected to the external power supply terminal 1, and the other end connected to the adjustment fuse element 4 serving as an output switching unit.
The third resistance element R ₃ connected to the common connection unit 3 through
And a buffer 5 composed of a voltage follower circuit to which a step-down voltage V _int obtained by stepping down the external power supply voltage in the common connection unit 3 is input.

The internal power supply voltage generation circuit 20 is a step-down voltage V which is an output voltage from the buffer 5 of the power supply voltage adjustment circuit 10 and is a reference for the internal power supply voltage of the semiconductor integrated circuit device.
Receiving _int , it generates the internal power supply voltage and outputs the potential to output terminal 6.

Hereinafter, an inspection method when performing burn-in of the semiconductor integrated circuit device configured as described above will be described.

First, in the burn-in inspection of the semiconductor integrated circuit device, a pre-probe inspection for inspecting a plurality of semiconductor integrated circuit devices on a semiconductor wafer in advance for a defective product is performed in a high-temperature atmosphere and at a normal operation. Generally, three steps are performed: a burn-in inspection performed while applying a high voltage, and a post-probe inspection for determining whether each semiconductor integrated circuit device is good or defective after the burn-in.

In the present embodiment, in a pre-probe inspection process, a semiconductor integrated circuit device in which some abnormality is found out of a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer and determined to be defective is determined. As shown in FIG. 1B, the adjusting fuse element 4 of the power supply voltage adjusting circuit 10 is blown by using a laser beam or the like.
So that current does not flow to the third resistance element R ₃ which has been connected in parallel a first and a resistance element R _1. Thereby, the first
Since the resistance value of the resistance element R ₁ becomes relatively larger by a third amount that the parallel resistance component of the resistance element R ₃ has run out of which are connected in parallel with the resistor element R ₁ of the first common connection The voltage drop of the unit 3 increases and the voltage value V decreases. Here, the first resistance element R ₁ , the second resistance element R _2,
The resistance value of the resistance element R ₃ is changed to the voltage value V of the common connection 3.
Is optimized so as to be equal to or less than half of the predetermined step-down voltage V _int , the current flowing through the defective semiconductor integrated circuit device can be remarkably suppressed.

In a conventional burn-in test in which a semiconductor integrated circuit device is divided into chips, it is impossible to perform burn-in on a defective chip found in a pre-probe test. When performing burn-in, unless measures are taken to prevent current from flowing to the defective semiconductor integrated circuit device, a latch-up phenomenon or the like in which abnormal current continues to flow occurs, and the remaining normal semiconductor integrated circuit device A situation may occur in which inspection cannot be continued even for the device.

However, according to the present embodiment, since the power supply voltage adjusting circuit is provided with the adjusting fuse element for switching so as to output a voltage value equal to or less than a half of the predetermined step-down voltage V _int . If the adjusting fuse element of the semiconductor integrated circuit device determined to be defective is trimmed in advance before the burn-in inspection process, the fuse is generated by the internal power supply voltage generation circuit of the semiconductor integrated circuit device determined to be defective. Since the internal power supply voltage is reduced to a voltage value equal to or less than half of the predetermined value, burn-in inspection of the remaining semiconductor integrated circuit device can be performed without causing DC failure.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows the configuration of a wafer cassette used when performing burn-in on a semiconductor integrated circuit device according to a second embodiment of the present invention. The burn-in device used here is assumed to be a device capable of performing wafer burn-in as shown in the conventional example. As shown in FIG. 2, a probe card 11 made of a glass substrate and having a multilayer wiring layer on its main surface has a semiconductor wafer 12 on its main surface.
A plurality of bumps serving as probe terminals provided at positions corresponding to the respective electrodes for inspection of the integrated circuit device above are formed, and these bumps are provided on external terminals provided on a peripheral portion of the probe card 11. Are electrically connected to one another through one of the multilayer wiring layers.

Using the probe card 11, a wafer
In order to perform burn-in, it is necessary to completely contact each bump of the probe card 11 with each electrode of the integrated circuit device formed on the semiconductor wafer 12. As a jig for this purpose, a wafer tray 13 made of metal such as aluminum and holding the semiconductor wafer 12 is provided.

On the periphery of the surface (= main surface) of the wafer tray 13 facing the main surface of the probe card 11, silicon rubber or the like for forming a closed space together with the main surface of the probe card 11 and the main surface of the wafer tray 13. The vacuum valve 1 is provided with a seal ring 14 made of
5 are provided.

FIG. 3 shows a schematic plan configuration of the probe card 11 and the semiconductor wafer 12. As shown in FIG. 3, a plurality of semiconductor integrated circuit devices 21 are formed in a matrix on the main surface of the semiconductor wafer 12, and the semiconductor integrated circuit device 21 has an external power supply for burn-in from a burn-in device. Burn-in power supply pad 2 to which voltage is applied
2 and an output pad 23 for outputting the operation result and the like of each element in the chip.

At the periphery of the probe card 11 which is pressed against the main surface of the semiconductor wafer 12 by atmospheric pressure, a burn-in power supply pad 22 of the semiconductor integrated circuit device 21 is electrically connected via a bump to a burn-in external device. Power input terminal 32 and output pad 23 of semiconductor integrated circuit device 21
Data output terminal 3 electrically connected to and via bumps
3 are formed respectively. Each of these terminals is electrically connected to a predetermined signal line in the burn-in device by being supplied to the burn-in device.

FIG. 4 shows functional blocks of a semiconductor integrated circuit device according to a second embodiment of the present invention. As shown in FIG. 4, in the semiconductor integrated circuit device formed on the semiconductor wafer, at the time of burn-in, a power supply voltage higher than that at the time of normal operation is applied to burn-in power supply pad 41, and ground potential is applied to ground pad 42. Is applied to drive the internal circuit 44. Between the burn-in power supply pad 41 and the internal circuit 44, a resistor Rm and a normal power supply pad to which a power supply voltage is applied during normal operation other than burn-in inspection (including probe inspection and final product inspection). Are provided. The resistance value of this resistor Rm is
The internal circuit 44 is set to a value such that a predetermined voltage drop occurs when the power supply current abnormally increases, and a large voltage drop does not occur at a power supply current value of a good product. The internal circuit 44 transmits the operation result and the like to the output circuit 49 via the data bus 45 and the signal switching circuit 46, and the output circuit 49 outputs the transmitted operation result as output data to an external burn-in device via the output pad 50. .
A voltage detection circuit 47 as a detection circuit connected in parallel with the internal circuit 44 is provided between the normal power supply pad 43 and the signal switching circuit 46.
7 outputs an identification signal 48 for identifying a non-defective or defective product.

Hereinafter, the operation of the voltage detection circuit of the semiconductor integrated circuit device configured as described above will be described with reference to FIG.

FIG. 5 shows a circuit configuration of a voltage detection circuit of the semiconductor integrated circuit device according to the present embodiment. As shown in FIG. 5, the voltage detection circuit 47 has an input terminal A provided on the power supply pad for normal use and an output terminal B provided on the signal switching circuit side. Further, the first P-type load transistor 52A and the second P-type load transistor 52B whose source electrodes are connected to a power supply terminal 51 to which a power supply voltage is applied and whose gate electrodes are connected to each other.
And a gate electrode connected to the input terminal A, a drain electrode connected to the common gate electrode and drain electrode of the first P-type load transistor 52A, and a source electrode grounded through the N-type load transistor 53. One N-type drive transistor 54A, the gate electrode is connected to the downstream side of the current source 55, the drain electrode is connected to the drain electrode of the second P-type load transistor 52B, and the source electrode is connected via the N-type load transistor 53. And a second N-type drive transistor 54B grounded. Further, a resistor element 56 for determining a step-down reference potential _Vref having one end connected to the downstream side of the current source 55 and the other end grounded is provided, and the second P-type load transistor 52B and the second N
An inverter 57 for inverting the potential of the drain electrode is connected between the common drain electrode of the pattern drive transistor 54B and the output terminal B, and the output signal of the inverter 57 is output to the output terminal B.

Hereinafter, the operation of the semiconductor integrated circuit device configured as described above will be described.

First, in the wafer cassette as described above,
After storing a semiconductor wafer on which a plurality of semiconductor integrated circuit devices to be tested are formed, a pre-probe test is performed on the plurality of semiconductor integrated circuit devices in a wafer state. Here, the semiconductor integrated circuit device in which the defect is found includes:
The input pad of the integrated circuit device is insulated, and, for example, when the fuse element shown in the first embodiment is provided, the fuse element is trimmed to suppress the occurrence of DC failure. I do.

Next, the wafer cassette is put into a burn-in device, heated to a predetermined temperature, and burn-in is performed by applying a burn-in power supply voltage higher than that during normal operation. Here, as shown in FIG. 4, the mode identification signal is set to the normal operation mode during the inspection, and the external device monitors the operation state such as the operation result from the internal circuit 44. At a predetermined timing, for example, every 30 minutes, the mode identification signal is changed to the voltage inspection mode, and the output of the signal switching circuit 46 is switched to the voltage detection circuit 47 to monitor the voltage abnormality.

At this time, in the voltage detection circuit 47 shown in FIG. 5, the voltage applied to the input terminal A is changed to the reference potential V _ref.
Higher than the first N-type drive transistor 54.
Since the potential of the gate electrode of A becomes higher than the potential of the gate electrode of the second N-type drive transistor 54B, the first N-type drive transistor 54A is more activated.
The potential of the drain electrode of the first N-type drive transistor 54A approaches the ground potential. Thus, the second P-type load transistor 52 commonly connected to the drain electrode
B is activated and the second P-type load transistor 52B is activated.
Since the potential of the drain electrode approaches the power supply potential, the high potential is inverted by the inverter 57 and low data is output to the output terminal B as a good product identification signal. This state is called a non-defective state.

On the other hand, when the voltage applied to the input terminal A is lower than the reference potential _Vref , the potential of the gate electrode of the first N-type drive transistor 54A changes to the gate of the second N-type drive transistor 54B. Since the potential is lower than the potential of the electrode, the second N-type drive transistor 54B is more activated, and the potential of the drain electrode of the second N-type drive transistor 54B approaches the ground potential. Thereby, the second
Of the N-type load transistor 54B of the inverter 57B approaches the ground potential.
And the output terminal B outputs high data as a defective product identification signal. This state is called a defective state.

As described above, according to the present embodiment, during the burn-in inspection, the abnormality of each power supply voltage can be detected for a plurality of semiconductor integrated circuit devices, so that a selection list of non-defective products and defective products can be created. In addition, the post-probe inspection of the semiconductor integrated circuit device determined to be defective can be omitted.

In FIG. 5, the resistance element 56 that determines the reference potential _Vref includes a voltage applied to the output terminal A, electrical characteristics such as threshold voltages of the P-type and N-type transistors, and an inverter. In view of the electrical characteristics of the DUT 57, it is sufficient to provide a resistance value for outputting a desired good or defective identification signal.

In this embodiment, the voltage detection circuit 47 is used as the detection circuit.
A current detection circuit that outputs a non-defective or defective product identification signal using the reference current may be used.

Further, the probe card to be put into the burn-in apparatus of the present embodiment uses a wafer cassette having bumps and the bumps being decompressed and pressed against the semiconductor wafer. However, the present invention is not limited to this. Any probe card that can be inspected may be used.

[0042]

According to the first semiconductor integrated circuit device of the present invention, among the plurality of semiconductor integrated circuit devices, the semiconductor device determined to have a DC failure in the pre-probe inspection process before the burn-in inspection. In the burn-in inspection process, a half of a predetermined voltage is applied to the integrated circuit device.
Since the output switching unit can be set in advance so as to output the following voltage values, DC failure can be prevented beforehand, so that burn-in inspection of another semiconductor integrated circuit element in which no abnormality has occurred can be performed. Can do it. Thus, wafer burn-in performed collectively in a wafer state can be reliably realized.

In the first semiconductor integrated circuit device, if the output switching section comprises a fuse element, the fuse element can be reliably switched to a voltage lower than a predetermined voltage by blowing the fuse element using a laser beam or the like.

According to the second semiconductor integrated circuit device of the present invention, during the inspection, D of the plurality of semiconductor integrated circuit devices is
A defective product identification signal indicating the occurrence of a DC defect is output from the semiconductor integrated circuit device in which the C defect has occurred, so that the defective device identification signal can be detected by an external device. as a result,
The post-probe inspection process of the semiconductor integrated circuit device determined to be defective can be omitted.

[Brief description of the drawings]

FIG. 1 shows a power supply voltage adjustment circuit and an internal power supply voltage generation circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 1A is a circuit diagram before a fuse element for adjustment is blown. And (b) is a circuit diagram after the fuse element for adjustment is blown.

FIG. 2 is a configuration diagram showing a wafer cassette used when performing burn-in on a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a schematic plan view of a probe card and a semiconductor wafer according to a second embodiment of the present invention.

FIG. 4 is a functional block diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a voltage detection circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a schematic view showing a conventional wafer burn-in apparatus.

[Description of Signs] 1 External power supply terminal 2 Ground terminal 3 Common connection unit 4 Adjustment fuse element (output switching unit) 5 Buffer 6 Output terminal 10 Power supply voltage adjustment circuit 20 Internal power supply voltage generation circuit 11 Probe card 12 Semiconductor wafer 13 Wafer tray Reference Signs List 14 seal ring 15 vacuum valve 21 semiconductor integrated circuit device 22 burn-in power pad 23 output pad 32 burn-in external power input terminal 33 data output terminal 41 burn-in power pad 42 ground pad 43 normal power pad 44 internal circuit 45 data bus 46 signal switching circuit 47 voltage detection circuit (detection circuit) 48 identification signal (defective product identification signal / defective product identification signal) 49 output circuit 50 output pad 51 power supply terminal 52A first P-type load transistor 52B second P-type load transistor 53 N type Load transistor 54A First N-type drive transistor 54B Second N-type drive transistor 55 Current source 56 Resistive element 57 Inverter A Input terminal B Output terminal

Claims (3)

[Claims] A power supply voltage adjusting circuit for reducing an external power supply voltage input from the outside to a predetermined voltage; and an internal power supply voltage generating circuit generating an internal power supply voltage based on the predetermined voltage. The semiconductor integrated circuit device, wherein the adjustment circuit includes an output switching unit that outputs one of the predetermined voltage and a voltage value equal to or less than a half of the predetermined voltage. 2. The semiconductor integrated circuit device according to claim 1, wherein said output switching section comprises a fuse element. 3. When a predetermined voltage value or current value is satisfied, a non-defective product identification signal indicating a non-defective product is output.
When the predetermined voltage value or current value is not satisfied, a detection circuit that outputs a defective product identification signal indicating a defective product, and receives a mode identification signal indicating a normal operation mode or an inspection mode, and in the inspection mode, And a signal switching circuit for outputting the non-defective product identification signal or the defective product identification signal.