JPS6387736A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a shape of a semiconductor chip to be inspected quickly and exactly, by forming a resistor with electrode pads on both its ends in the periphery of the semiconductor chip. CONSTITUTION:A diffusion resistor 17, whose distances from scribing conductors 11-1 and 11-2 are identical with each other, is formed on the periphery of a semiconductor chip so as to surround an element, region 18 of the chip. On both ends of a resistor consisting this diffusion resistor 17, contact windows 15 are formed and electrode pads 19-1 and 19-2 made of Al are disposed. A resistance value of a shape checking resistor is measured instead of appearance inspection of a cutting part. Hence, improvement of inspection efficiency, prevention of inspection failure and prevention of unevenness in quality, caused by individual difference or the like of inspectors, can be performed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a function of efficiently sorting out defects around chips that occur in the process of dividing a semiconductor wafer into chips. Regarding.

[Conventional technology]

A conventional visual inspection method in the process of dividing a semiconductor wafer into chips will be described.

Generally, in the manufacturing of semiconductor devices, a large number of identical semiconductor elements are simultaneously formed on a semiconductor substrate (wafer), and then these semiconductor elements are divided into individual chips and assembled into a predetermined package to form the semiconductor device. Ta. For this reason, regions, ie, scribe lines, are provided on the semiconductor substrate for dividing into individual semiconductor elements.

Furthermore, the distance between the scribe line and the part where circuit elements such as transistors constituting the semiconductor element are formed is several tens of μm.
A machine such as a dicer or scriber that is generated in the process of dividing an area into each chip by creating an area with a width of approximately 300 yen (m) in parallel with the scribe line without any circuit elements (hereinafter referred to as the area without circuit elements as the chip outer periphery). This prevents the semiconductor device from becoming defective due to misalignment and defects around the chip that occur when the chip is divided.

In other words, if it were possible to completely eliminate misalignment of the dicer and scriber and defects around the chip, it would be possible to improve the yield and quality of semiconductor device manufacturing, but this is currently not possible, and for this reason, it is usually not possible to Currently, after dividing the product into parts, an appearance inspection is performed, and the good and defective products are visually sorted based on the degree of cracking and chipping.

FIG. 8 is a plan view of the main part of a semiconductor wafer, which is a semi-finished product of a conventional semiconductor device. 1-1.1-2 is a region for dividing into chips as described above with scribe lines, and before division, semiconductor elements A, B, and
It is considered to be the boundary between C and D.

2A, 2B, 2C, and 2D are semiconductor elements A and B.

The insulating regions 2A, 2B are the insulating regions around the circuit elements 4A, 4B, 4C, 4D that constitute C, D.

The area inside 2C and 2D is called the element area of the chip.

Moreover, there are no circuit elements provided outside the insulating regions 2A, 2B, 2C, and 2D, that is, on the scribe line side, and the area is several tens of μm.
Chip outer peripheries 3A, 3B, 3C, and 3D are provided with a width of approximately 100 mm, thereby preventing damage to the element region of the chip due to defects in the chip periphery that occur during the process of dividing into chips.

5A, 5B, and 5D are contact windows that connect wirings 6A, 6'B, and 6D to circuit elements 4A, 4B, and 4D, respectively.

When such a conventional # conductor wafer is divided into chips along the scribe line, defects X may occur in the divided chips as shown in a plan view of FIG. 9. For this reason, the chip outer periphery 3A is provided to prevent the circuit element 4A from becoming defective even if a defect X occurs, but increasing the width of the chip outer periphery 3A directly increases the chip size. Therefore, the width cannot be increased unnecessarily, and for this reason, the defect X may exceed the insulating region 2A.In order to remove semiconductor elements with such defects, a visual inspection of the chip is performed.

As mentioned above, visual inspection is a visual judgment performed by an operator based on certain criteria.

For example, if this criterion is based on the chip outer periphery 3A, that is, the half between the scribe line and the part containing the circuit element, the operator visually inspects each chi knob with a microscope, and If less than half of 3A is missing, it is a good product.
If it is more than half, it is considered defective.

The above is the conventional visual inspection method.

[Problem that the invention seeks to solve]

For example, if the criterion is that a defect up to 1/2 of the width of the chip's outer periphery is a good product, and anything beyond that is a defective product, look at the extent of the defect and determine if it exceeds 1/2 of the width of the chip's outer periphery. You have to decide if there is. Normally, visual inspection is performed in a field of view where the entire chip can be seen, so
It is not easy to judge whether or not the degree of defect occurring on the outer periphery of a chip with a width of approximately 1/2 is greater than 1/2 of that width, and this can lead to decreased inspection efficiency, oversight of inspection, and individual differences among inspectors. This tends to cause unevenness in the quality of semiconductor devices due to such factors.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of quickly and accurately inspecting the external shape of a semiconductor chip.

[Means for solving problems]

The semiconductor device of the present invention has a configuration in which a resistor having electrode pads at both ends is arranged on the outer periphery of the semiconductor chip.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of the main part of a semiconductor wafer for explaining a first embodiment of the present invention.

In this embodiment, a diffused resistor 17 equidistant from the scribe lines 11-1 and 11-2 is provided on the outer periphery of the chip so as to surround an element region 18 of the semiconductor chip, and a resistor consisting of the diffused resistor 17 is connected to both ends of the resistor. A contact window 15 is provided in each A.
Electrode pads 19-1 and 19-2 consisting of e are arranged.

FIG. 2 is a detailed view of the vicinity of the electrode pad in FIG. 1. 11
-1.11-2 is an area for dividing into each chip by a scribe line. 12 is a circuit element 1 constituting a semiconductor device
This is the insulation area of 4.

That is, it is a region surrounding the element region, which is the region in which the integrated circuit operates.

15' is a contact window of the circuit element 14 for making ohmic contact with the wiring 16.

Reference numeral 17 denotes a diffused resistor formed parallel to and equidistant from the scribe line, and in an integrated circuit composed of a P-type semiconductor substrate and an N-type epitaxial layer, it is made of a P-swelled diffusion layer. Hereinafter, this diffused resistor will be referred to as an outer shape check resistor, and the outer shape check resistor is set at the outer periphery of the chip so as to substantially surround the chip. 19-1.19-2 is At? with an area on which the probe can be placed. These electrode pads are located at both ends of the external shape check resistor. Below, this electrode pad 19-1
．． Sow 19-2 with a pad for checking the external shape.

Next, a method for testing a semiconductor device of the present invention will be explained.

The inspection method is based on the degree of damage to the outer shape check resistor.

3(a) to 3(c) are respectively plan views of semiconductor chips with defects, and FIGS. 4(a> and 4(b) are respectively FIG.
It is a sectional view taken on the line AA' of (a) and (b).

In the case of a semiconductor chip with a defect of the degree shown in FIGS. 3(a) and 4(a), the defect 1.19 When a voltage is applied to 2m, a current determined by the original resistance value of the external shape check resistor flows.

Next, in the case of a semiconductor chip with defects of the degree shown in Fig. 3(b) and Fig. 4(b), when the semiconductor substrate is divided into chips, the defect X in the chip becomes large enough to exceed the external shape check resistance. When a voltage is applied between the electrode pads 19-1 and 19-2, the defect X cuts the outer shape check resistor, so no current flows and the circuit is in an open state.

Next, in the case of a semiconductor chip with defects as shown in FIG. Since it is not, current flows. However, since the outer shape check resistor is thinner in the defective part, the impedance is expected to be higher.

FIG. 5 is a voltage-current characteristic diagram of the external shape check resistor.

1, n, I[[ are shown in FIGS. 3(a) and (b), respectively.

This is a curve for the semiconductor chip shown in (c).

The shape check resistor does not have to be a diffused resistor, but from the viewpoint of reproducibility, a diffused resistor is preferable.The voltage-current characteristics change depending on the resistivity and shape of the shape check resistor, so the type of resistor should be selected depending on the type of IC. It may be selected as appropriate.

As described above, whether or not the external shape check resistor is disconnected can be determined based on the current value, so the external appearance check can be replaced with current measurement.

In addition, the spacing between the electrode pads provided on the external shape check resistor can be checked by simply setting up a probe without bonding, so the spacing between the pads only needs to be a few tens of micrometers at most, and the spacing between the pads can be made sufficiently narrow to prevent defects between the pads. The percentage of cases occurring is extremely small, and the risk of missed tests is considered to be extremely small.

FIG. 6 is a plan view of the main part of a semiconductor wafer for explaining a second embodiment of the present invention.

In this embodiment, the electrode pads 29-1.29-2 are provided at the corners of the semiconductor chip.
9-2 are connected to the diffused resistor 27 at the contact window 25-1, 25-2 by AJ7 wiring 45-1, 45-2, respectively. The distance between the electrode pads is large, making it easier to place the probe.

FIG. 7 is a plan view of the main part of a semiconductor wafer for explaining a third embodiment of the present invention.

In this embodiment, the electrode pads 39-1 and 39-2 are placed closer to the element region 38, which can further reduce inspection omissions. By providing three electrode pads-3 that are in contact with the selectively provided N+ type region contact window 35-3, a voltage is applied thereto to reverse bias the P-type diffusion layer and insulate it. The purpose is to improve the accuracy of current measurement. In this case, it is also possible to check whether the PN junction is destroyed at the defective location when the chip is divided.

In the above explanation, an N-type epitaxial layer is formed on a P-type semiconductor substrate, and an appearance check resistor is formed with a P-type diffusion layer on the epitaxial layer. It can be applied when forming a resistor, or when forming an appearance check resistor using an N-type diffusion layer on a P-type semiconductor substrate.

〔Effect of the invention〕

In conventional semiconductor devices, the visual inspection process involves dividing the semiconductor substrate into chips, arranging the divided chips at equal intervals (hereinafter referred to as sheet expansion), and inspecting the outer periphery of each chip. The degree of chip damage occurring in the area was determined by observing it under a microscope.

After a visual inspection, chips that were found to be of good quality were sucked up by a collet, transported to a predetermined position, mounted on a stem, and sealed in a case to produce a product.

In the semiconductor device of the present invention, first, as an example, the semiconductor substrate is divided into chips, the chips are attached to the stem by a collet, and the chips are sealed in a case. When the product is completed, the external shape is inspected by checking. The visual inspection process, which was previously described in the conventional example and was performed by an operator using a microscope for each chip, can be omitted.

It is also possible to inspect the chips at the stage where they are divided into chips, that is, before transporting them to the stem, and to assemble only good products. Furthermore, the divided chips are inspected while being suctioned by a collet with a probe, and if they are good, they can be carried as is to the stem and attached to the stem, and if they are defective, they can be discarded.

As described above, the semiconductor device of the present invention shows the appearance of the defective part.

Since it is sufficient to measure the resistance value of the external shape check resistor instead of the inspection, it is very useful for improving inspection efficiency, preventing inspection omissions, and preventing non-uniformity in quality due to individual differences among inspectors.

In other words, it has the effect of reducing man-hours and improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the main part of a semiconductor wafer for explaining the first embodiment of the present invention, FIG. 2 is a detailed view of the vicinity of the electrode pad in FIG. 1, and FIGS. 3(a) to (c) ) are respectively plan views of semiconductor chips with defects, Figures 4(a) and (b) are cross-sectional views taken along the line A-A' of Figures 3(a) and (b), respectively, and Figure 5 is an outline check resistor. Voltage-current characteristic diagram, Fig. 6,
FIG. 7 shows the second embodiment of the present invention. A plan view of the main part of a semiconductor wafer for explaining the third embodiment, FIG. 8 is a plan view of the main part of the semiconductor wafer for explaining a conventional semiconductor device, and FIG. 9 is a plan view of the main part of the semiconductor wafer for explaining the conventional semiconductor device. FIG. 2 is a plan view of a semiconductor chip. 1-1.1-2. ．． 11-1.11-2.21-1.2
1-2.31-1.31-2...Scribe line, 2A
~2D, 12... Insulating area, 3A~3D, 13.23
．． 33...Chip outer area, 4A to 4D, 14.24.
34...Circuit element, 5A to 5D, 15.25-1.
25-2.35-1. 35-2...Contact window,
6A to 6D, 16... Wiring, 17.27.37...
Diffused resistance, 18.28.38...Element region, 19-1
．． 19-2.29-1.29-2.39-1.39-2
... Electrode pad, 40 ... P-type silicon substrate, 41
...P+ type isolation region, 42...N type epitaxial layer, 43...P type diffusion layer, 44...silicon oxide film, A to D... semiconductor element. 1st prisoner 8Z flash 3rd figure 5th figure 45-f, 4 ter 2 Yuotokyo 3'? -f, zuq-2, wo 9-3 7 figures f-f, f-'2. Suflife line jA, I3
0 Contact ZA~zp
6A~6p and C o-hi 3A~31) 4-pu 7° outside M1ξomi A-J) Mountain winter +A~4.91!1
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Claims (2)

[Claims] (1) A semiconductor device characterized in that a resistor having electrode pads at both ends is arranged on the outer periphery of a semiconductor chip. (2) The semiconductor device according to claim (1), wherein the resistor substantially surrounds an element region of the semiconductor chip.