JPH01225138A - Short-circuit monitor for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To electrically perform a short-circuit inspection of a plurality of chips by performing an inspection only once by providing a monitor pattern for inspecting the short-circuit of a metal layer pattern in each chip, and connecting the pattern of the plurality of chips by utilizing a diffused layer line of a dicing line. CONSTITUTION:Monitor patterns 2 are respectively formed in chips 1-1-1-4, and a pair of metal layer patterns and pads 3-1, 3-2 to be connected to the respective layer patterns are formed on the pattern 3. A P<+> type diffused layer or a pair of diffused layer lines 4-1, 4-2 by the P<+> type diffused layer are formed on a dicing line 6, and the lines 4-1, 4-2 are connected to the pads 3-1, 3-2 of the chips 1-1-1-4 through diffused layer lines 5-1, 5-2. Thus, a plurality of chips are simultaneously electrically detected at its short-circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a short circuit monitor formed in a wafer together with a semiconductor integrated circuit device in order to detect short circuits between metal layer patterns in a semiconductor integrated circuit device.

(Prior Art) In a semiconductor integrated circuit device using a polysilicon layer pattern, an interlayer insulating film is formed on the polysilicon layer pattern, and a metal layer pattern is formed thereon.

If the metal layer pattern crosses the polysilicon layer pattern, the metal layer may not be etched sufficiently at the edges of the polysilicon layer pattern, leaving the metal layer and causing a short circuit between adjacent metal layer patterns. .

Inspection of metal layer patterns for short circuits is performed visually. Therefore, it is time-consuming and often difficult to judge. In particular, short circuits in the metal layer pattern at the stepped portions of the edges of the polysilicon layer pattern cannot be seen without a SEM (scanning electron microscope), making it difficult to analyze failures. it takes time.

(Purpose) The present invention forms a short circuit monitor that detects short circuits in a metal layer pattern in the process of manufacturing a semiconductor integrated circuit device in each chip, and uses the short circuit monitor to electrically detect short circuits in multiple chips at the same time. The purpose is to enable detection.

(Structure) The short circuit monitor of the present invention is formed in each chip when manufacturing a semiconductor integrated circuit device, and includes a polysilicon layer pattern,
A monitor pattern consisting of an interlayer insulating film thereon and a pair of metal layer patterns formed at appropriate intervals across the polysilicon layer pattern on the interlayer insulating film, and a plurality of chips via a dicing line. and a diffusion layer line connecting the monitor pattern.

The reason why the diffusion layer line is formed in the dicing line to connect the monitor patterns of a plurality of chips is to eliminate any inconvenience in the dicing process. This is because if a metal line were provided on the dicing line to connect the chip monitor pattern, there would be adverse effects such as metal adhering to the dicing blade.

When a short circuit in a metal layer pattern is inspected using a monitor pattern within one chip, short circuits can be electrically inspected for a plurality of chips connected by a diffusion layer line of a dicing line.

Examples will be specifically described below.

FIG. 1 shows one shot of a wafer of a semiconductor integrated circuit device formed using a reticle on which a pattern of a four-chip semiconductor integrated circuit device is formed.

1-1 to 1-4 each represent a chip area of a semiconductor integrated circuit device, and each chip 1-1 to 1-4 contains 1
Monitor patterns 2 are formed one by one. The position of the monitor pattern 2 is designed to be the same for each of the chips 1-1 to 1-4. Although original semiconductor integrated circuit devices other than the monitor pattern 2 are formed in each of the chips 1-1 to 1-4, illustration thereof is omitted.

The chips 1-1 to 1-4 are surrounded by a dicing line 6 so that the chips 1-1 to 1-4 can be separated later.

As will be described in detail later, the monitor pattern 2 includes a pair of metal layer patterns for inspecting short circuits and pads 3-1, 3-2 connected to each metal layer pattern.

A pair of diffusion layer lines 4-1 and 4-2 are formed on the dicing line 6 by a P+ diffusion layer or an N+ diffusion layer, and these diffusion layer lines 4-1 and 4-2 are connected to each chip 1.
-1 to 1-4 pads 3-1, 3-2 are diffusion layers 5-1.
5-2.

FIGS. 2 and 3 show the monitor pattern 2 in enlarged detail.

20 is an N-type silicon substrate, 10.10 is a field oxide film, and 5-1.5-2 is a P expansion diffusion layer.

Polysilicon layer patterns 11.11 are formed on the field oxide films 10.10, respectively.

The glabella insulating film 2 except for some areas of the diffusion layer 5-1 and 5-2
1 and metal layer pattern 3-1.3- from above.
2.12-1.12-2 is formed.

The metal layer pattern is diffusion W! A first comb-shaped pattern 12-1 connected to the pad 3-1 and formed across the polysilicon layer pattern 11.11, Layer 5-2
pad 3-2 formed to be connected to pad 3-2;
-2 and a second comb-like pattern 12-2 formed to extend across the polysilicon layer pattern 11.11. The metal layer patterns 12-1 and 12-2 are covered with an insulating film 21.

The first metal layer pattern 12-1 and the second metal layer pattern 12-2 are formed parallel to each other and at equal intervals. The width and spacing of the metal layer patterns 12-1 and 12-2 are set to be approximately the same size as the metal layer pattern in the semiconductor integrated circuit device, in accordance with the design rules when forming the metal layer pattern of the semiconductor integrated circuit device. It is preferable to do so.

As shown in FIG. Connected to pattern 2.

In this embodiment, if a metal layer as indicated by A remains as shown in FIG. 2, a short circuit will occur between metal layer patterns 12-1 and 12-2, and pad 5-1
．． A short circuit can be detected by continuity between 5 and 2.

Further, by applying a voltage to a pair of pads 3-1, 3-2, short circuits between metal layer patterns 12-1, 12-2 can be simultaneously inspected for four chips 1-1 to 1-4. is possible and efficient.

A method of forming a monitor pattern according to an embodiment will be explained with reference to FIGS. 4(A) to 4(D).

(A) In the process of manufacturing a semiconductor integrated circuit device, a field oxide film of 10° lO and a P+ diffusion layer 5-1, 5-2 are formed on an N-type silicon substrate 20.

(B) Deposit a polysilicon layer and form polysilicon layer patterns 11.11 on field oxide films 10.10 by photolithography and etching, respectively.

(C) An oxide film to be used as an interlayer insulating film 21 is deposited thereon, and the interlayer insulating film 21 in a region to be connected to a pad later on the diffusion layer 5-1, 5-2 is removed.

A metal layer is deposited thereon, and metal layer patterns 12-1.12-2 and pads 3-1.3- are formed across the polysilicon layer patterns 11 and 11 by photolithography and etching.
form 2.

(D) An oxide film 22 serving as a protective film is deposited thereon, and the oxide film 22 on the pads 3-1 and 3-2 is removed.

(Effects) In the present invention, since a monitor pattern for inspecting short circuits in the metal layer pattern is provided in each chip, short circuits in the metal layer pattern can be electrically inspected, and the effort of visual inspection can be saved. .

Since the monitor patterns of a plurality of chips are connected using the diffusion layer line of the dicing line, a short circuit test of a plurality of chips can be performed in one test, and the test efficiency is high.

[Brief explanation of the drawing]

Fig. 1 is a schematic plan view showing one embodiment, Fig. 2 is a plan view showing an enlarged monitor pattern of one embodiment, and Fig. 3 is a plan view showing a second embodiment.
A cross-sectional view taken along line X-X in the figure, from Figure 4 (A) to Figure 4 (
D) is a cross-sectional view showing the process of forming a monitor pattern in one embodiment. 1-1 to 1-4... Chip area. 2...Monitor pattern. 3-1.3-2... Pad, 4-1.4-2... Diffusion layer line, 5-1.5
-2... Diffusion layer, 6... Dicing line. 1O...Field oxide film, 11...Polysilicon layer pattern. 12-1.12-2...Metal layer pattern, 2
1...Interlayer insulating film.

Claims (1)

[Claims] (1) Formed within each chip when manufacturing a semiconductor integrated circuit device, formed at appropriate intervals across a polysilicon layer pattern, an interlayer insulating film on the polysilicon layer pattern, and an interlayer insulating film on the interlayer insulating film. A short circuit monitor comprising a monitor pattern consisting of a pair of metal layer patterns, and a diffusion layer line connecting the monitor patterns of a plurality of chips via a dicing line.