JPH11297584A - Method and apparatus for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Problem] To provide a technique capable of realizing a semiconductor integrated circuit device having a highly accurate fine pattern. SOLUTION: After collecting dimension data of a resist pattern formed on a semiconductor wafer, a dimension correction map of a resist pattern in a semiconductor wafer surface is created from the dimension data, and the dimension correction map is drawn by an electron beam direct writing apparatus. Enter Next, after a correction map of the irradiation amount of each shot of the electron beam is created from the dimension correction map, the electron beam is registered at the optimum irradiation amount for each shot based on the correction map of the irradiation amount of each shot of the electron beam. Irradiation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a semiconductor integrated circuit device formed by using an electron beam direct drawing technology.

[0002]

2. Description of the Related Art The electron beam direct writing technique is a technique in which a resist film sensitive to an electron beam is applied to the surface of a semiconductor substrate, and the electron beam narrowed down on the semiconductor substrate is subjected to design data of a semiconductor integrated circuit device. This is a technique of drawing a pattern on the resist by operating based on the above, developing the pattern, and forming a pattern of the resist directly on the semiconductor substrate. Therefore, the electron beam direct writing technique has a resolution capable of writing a fine pattern and can draw a pattern with high accuracy.

[0003] However, with the miniaturization of semiconductor integrated circuit devices, the demand for high resolution is becoming increasingly severe.
Therefore, in the electron beam direct writing technique, the resolution is improved by drawing a pattern on a resist applied on the semiconductor substrate and then performing PEB (Post Exposure Bake) processing on the semiconductor substrate. That is, PE
By performing the B treatment, the photo-decomposed photosensitive agent in the resist is diffused, and the concentration distribution of the photosensitive agent is made uniform in the thickness direction of the resist, thereby improving the resolution of the resist.

[0004] For the PEB process, for example,
"Ultrafine processing technology" published by Ohmsha, published on February 25, 1997, edited by Wei Tokuyama, p. 59.

[0005]

However, the present inventor has found that in the electron beam direct writing technique employing the PEB processing, the problem that the dimensional variation of the resist pattern in the semiconductor wafer surface becomes as large as 20 to 30 nm. I found it.

That is, in the baking furnace for performing the PEB process, it is difficult to uniformly control the baking temperature over the entire surface of the semiconductor wafer, and the baking temperature varies.
The variation in the baking temperature is a major factor in the dimensional variation of the resist pattern.

An object of the present invention is to provide a technique capable of realizing a semiconductor integrated circuit device having a high-precision fine pattern.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, when a resist pattern is formed on a semiconductor wafer by using an electron beam direct drawing technique, first, a first resist is applied onto the semiconductor wafer. A pattern is drawn on the first resist with a substantially constant irradiation amount using an electron beam direct drawing apparatus. Next, after performing a first PEB process on the semiconductor wafer, the first
To form a first resist pattern on the semiconductor wafer, and then measure the dimensions of the first resist pattern formed on the semiconductor wafer.
Next, after collecting the dimensional data of the first resist pattern in the semiconductor wafer surface, a dimensional correction map of the first resist pattern in the semiconductor wafer surface is created from the dimensional data of the first resist pattern, First
Is input to the electron beam direct drawing apparatus. Next, after creating a correction map of the irradiation amount for each shot of the electron beam in the semiconductor wafer plane from the dimension correction map of the first resist pattern, the first resist pattern is removed, and then the second resist pattern is formed on the semiconductor wafer. 2
Is applied. Next, using a direct electron beam drawing apparatus, a pattern is drawn on the second resist with the irradiation amount specified from the correction map of the irradiation amount for each shot of the electron beam, and then a second PEB process is performed on the semiconductor wafer. And then
A second resist pattern is formed on the semiconductor wafer by performing a second development process on the semiconductor wafer.

(2) An apparatus for manufacturing a semiconductor integrated circuit device according to the present invention is an electron beam direct writing apparatus for forming a resist pattern on a semiconductor wafer by using an electron beam direct writing technique. From the dimension correction map of the resist pattern in the above, a correction map of the irradiation amount for each shot of the electron beam was created, and the irradiation amount specified on the correction map of the irradiation amount for each shot of the electron beam was applied onto the semiconductor wafer. A pattern is drawn on a resist.

According to the above-described means, the dimensional variation of the resist pattern in the semiconductor wafer surface can be suppressed by correcting the irradiation amount of each shot of the electron beam in the electron beam direct writing apparatus. A highly accurate resist pattern with small variations can be formed, and the dimensional accuracy of the fine pattern in the semiconductor wafer surface is improved.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) Steps 100 to 110 shown in FIG. 1 and a resist pattern in a semiconductor wafer surface shown in FIG. 2 to FIG. This will be described with reference to a dimension correction map of a resist pattern and a correction map of an irradiation amount for each shot of an electron beam.

First, after removing foreign matter on the front or back surface of the semiconductor wafer, a positive or negative resist is uniformly applied to the front surface of the semiconductor wafer by a spin coating method (step 100). In this method, a semiconductor wafer is placed on a spin chuck, and the resist is scattered by centrifugal force to form a resist having a uniform thickness on the surface of the semiconductor wafer.

Next, after setting the semiconductor wafer in the electron beam direct writing apparatus, the semiconductor wafer is irradiated with an electron beam at a substantially constant dose based on the design data, and is formed by the electrons incident on the polymer constituting the resist. Cross-linking or collapse of the molecule occurs (step 101). That is, when the resist is irradiated with electrons, a difference is caused between the molecular weight of the irradiated portion and the molecular weight of the non-irradiated portion due to decomposition due to breaking of the main chain of the molecule or polymerization due to bonding between the main chains.

Next, the semiconductor wafer is subjected to a PEB process at a temperature of, for example, 95 ° C. for about 2 minutes using a PEB furnace (step 102).

Next, the semiconductor wafer is subjected to a cooling process at a temperature of, for example, 22 ° C. for about 1 minute (step 10).
3).

Next, a developing solution is dropped on the surface of the semiconductor wafer and applied using surface tension, and after a developing process for a predetermined time, rinsing with pure water and rotary drying are continuously performed. Then, the low molecular weight region of the resist on the semiconductor wafer is dissolved, and a resist pattern is formed while leaving the high molecular weight region (step 104).

Next, the dimensions of the resist pattern are measured (step 105), and dimension data of the resist pattern in the semiconductor wafer surface as shown in FIG. 2 is collected (step 10).
6). Although FIG. 2 only shows the dimensions of one resist pattern in each semiconductor chip, the dimensions of a plurality of resist patterns at three to five locations are measured in each semiconductor chip. If the size of the resist pattern is within the standard of 0.220 ± 0.005 μm, the resist pattern is inspected for alignment (Step 10).
7), proceed to the next step.

On the other hand, if the dimensional data of the resist pattern is out of the standard, the dimensional data of the resist pattern in the semiconductor wafer surface shown in FIG. After creating the dimension correction map (Step 108), the dimension correction map is input to the electron beam direct drawing apparatus (Step 109).

Next, a correction map of the irradiation amount for each shot of the electron beam shown in FIG. 4 is created from the size correction map of the resist pattern in the semiconductor wafer surface shown in FIG. 3 (Step 110). Thereafter, a resist having a uniform thickness is again applied to the surface of the semiconductor wafer (step 100), and then, based on the correction map of the irradiation amount of each shot of the electron beam shown in FIG. The resist is irradiated with an electron beam at an appropriate dose (step 101).

Next, the PEB treatment in step 102, step 10
After performing the cooling process 3 and the development process in step 104 on the semiconductor wafer, the dimensions of the formed resist pattern are measured (step 105).

FIG. 5 shows the dimensions of the resist pattern in the semiconductor wafer surface obtained by irradiating the electron beam based on the correction map of the irradiation amount for each shot of the electron beam shown in FIG. The dimensional variation of the resist pattern formed without correcting the irradiation amount of the electron beam is 20 to 30 nm or more as shown in FIG. 2, but is formed by correcting the irradiation amount of each electron beam shot. The dimensional variation of the resist pattern becomes 5 nm or less.

Next, a bipolar transistor having a wiring layer formed by applying the method for correcting the size of a resist pattern according to the first embodiment will be described with reference to a cross section of a main part of a semiconductor substrate showing the bipolar transistor shown in FIG. This will be described with reference to the drawings.

First, the cross-sectional structure of the main part of the bipolar transistor will be briefly described. The bipolar transistor mainly includes a p-type semiconductor substrate 1a made of single crystal silicon. On the main surface of the semiconductor substrate 1a, n
The epitaxial layer 2 is stacked, and an active region (element formation region) is provided on the main surface of the semiconductor substrate 1a. The back surface of the semiconductor substrate 1a is composed of a silicon oxide film 1b and a support substrate 1c.

In the active region, a buried n-type semiconductor region 3 is formed between the semiconductor substrate 1a and the n-type epitaxial layer 2. The active region is electrically separated from other surrounding active regions by an element isolation region.
The element isolation region is mainly composed of an element isolation insulating film, for example, silicon oxide films 4 and 5.

A bipolar transistor is formed in the active region. This bipolar transistor has a vertical structure in which an n-type collector region, a p-type base region, and an n-type emitter region are sequentially arranged.

The n-type collector region comprises an n-type epitaxial layer 2, a buried n-type semiconductor region 3, and an n-type semiconductor region 6 for raising the collector potential. The p-type base region is a p-type semiconductor region 7 which is a graft base region.
And a p-type semiconductor region 8 which is an intrinsic base region. The n-type emitter region is constituted by an n-type semiconductor region 9.

A tungsten wiring (hereinafter abbreviated as W wiring) 10a is connected to the collector potential raising n-type semiconductor region 6 through a collector opening 4a.

A p-type semiconductor region 7, which is a p-type base region, has a base lead-out electrode 1 through a base opening 4b.
1 is connected to one end. Base lead-out electrode 11
At the other end, a W wiring 10b is formed through a connection hole 13 formed in the insulating films 12a and 12b.

N-type semiconductor region 9 which is an N-type emitter region
Is connected to the emitter lead-out electrode 14 through the emitter opening 4c. Emitter extraction electrode 1
4 is electrically connected to the W wiring 10c through a connection hole 15 formed in the insulating film 12a. The emitter lead-out electrode 14 is an n-type impurity, for example, arsenic (As).
Alternatively, it is composed of a polycrystalline silicon film into which phosphorus (P) is introduced.

The W wiring 10a, which constitutes the first layer wiring,
10 b and 10 c are covered with first interlayer insulating films 16, 17 and 18 composed of a silicon oxide film.

On the first interlayer insulating films 16, 17, 18, a tungsten / aluminum / tungsten laminated film (hereinafter abbreviated as W / Al / W laminated wiring) 19 constituting a second layer wiring is formed. And the first interlayer insulating film 1
The wirings are connected to W wirings 10a, 10b, and 10c, which are wirings of the first layer, through connection holes 20 formed in the wirings 6 and 18.

In order to mount a semiconductor element such as a bipolar transistor on a semiconductor chip with high integration, the W
The / Al / W laminated wiring 19 needs to have a wiring width of 1.0 μm and a space of 1.0 μm or less, and requires a high-precision wiring layer processing technique. Therefore, the W / Al / W laminated wiring 19 is formed by using the resist pattern dimension correcting method of the first embodiment.

Next, a method for forming the W / Al / W laminated wiring 19 will be described.

First, the sputtering method and the CVD (Chemic
al Vapor Deposition) method to form a lower tungsten film by continuous processing. This lower tungsten film
It has good adhesion to the underlying first interlayer insulating films 16 and 18 and good coverage to the connection holes 20.

Next, an intermediate aluminum film and an upper tungsten film are sequentially deposited on the lower tungsten film. This aluminum film is an aluminum single layer film, or silicon (Si), copper (Cu), or Si and Cu
This is an aluminum alloy film containing both of them, and is used to lower the resistance of the wiring. The concentration of Cu in the aluminum alloy film is 3.0% or less, and Cu has an effect of reducing electromigration of wiring.

The lower tungsten film constituting the W / Al / W laminated wiring 19 is, for example, a tungsten film having a thickness of about 0.05 μm formed by a sputtering method and a tungsten film having a thickness of about 0.2 μm deposited by a CVD method. The thickness of the intermediate aluminum layer is, for example, about 0.6.
μm, and the thickness of the upper tungsten film is, for example, about 0.05
μm.

Next, a resist pattern for processing the W / Al / W laminated film is formed on the surface of the upper tungsten film by using the method for correcting the dimension of the resist pattern.

That is, first, as shown in FIG.
After applying a resist on the upper tungsten film (Step 100), the resist is irradiated with an electron beam (Step 10).
1) Then, a PEB process (the step 102), a cooling process (the step 103), and a developing process (the step 10)
4) is sequentially applied to the semiconductor wafer to form a resist pattern. Next, if the dimension of the resist pattern measured in the development dimension inspection after the development processing (the above-mentioned step 105) is within the standard (the above-mentioned step 106), the alignment of the resist pattern is inspected (the above-mentioned step 107). And proceed to the next step.

However, if the dimension of the resist pattern is out of the standard, a dimension correction map of the resist pattern in the semiconductor wafer surface is created from the dimension data of the resist pattern (Step 108), and this dimension correction map is electronically converted. Input to the line direct drawing apparatus (step 109),
A correction map of the irradiation amount for each shot is created from the dimension correction map (Step 110).

Thereafter, the resist pattern on the semiconductor wafer is removed, a resist is applied again on the upper tungsten film (Step 100), and then, for each shot, based on the correction map of the irradiation amount for each shot. Irradiating the resist with an electron beam at an optimal dose (see step 10 above)
1). Next, a PEB process (the process 102), a cooling process (the process 103), and a development process (the process 10).
4) is sequentially applied to a semiconductor wafer to form a resist pattern.

Next, by etching the W / Al / W laminated film using the resist pattern as a mask,
The W / Al / W stacked wiring 19 constituting the wiring of the second layer is formed.

The W / Al / W laminated wiring 19 constituting the wiring of the second layer is covered with the second interlayer insulating films 21, 22 and 23. Further, the second interlayer insulating films 21, 22, 23
A W / Al / W laminated wiring 24 constituting a third-layer wiring is formed on the upper surface, and the W / Al / W laminated wiring 24 is formed.
Is W / Al, which is the wiring of the second layer through the connection hole 25.
/ W laminated wiring 19.

The W / Al / W laminated wiring 24 forming the third layer wiring is covered with third interlayer insulating films 26, 27 and 28. Further, third interlayer insulating films 26, 27, 28
A W / Al / W laminated wiring 29 constituting a fourth-layer wiring is formed thereon, and the W / Al / W laminated wiring 29 is formed.
Is W / Al, which is the third layer wiring through the connection hole 30.
/ W laminated wiring 24.

The W / Al / W laminated wiring 29 constituting the wiring of the fourth layer is covered with fourth interlayer insulating films 31, 32 and 33. Further, the fourth interlayer insulating films 31, 32, 33
A W / Al / W laminated wiring 34 constituting a fifth layer wiring is formed on the upper surface, and the W / Al / W laminated wiring 34 is formed.
Is W / Al which is a fourth-layer wiring through the connection hole 35.
/ W laminated wiring 29.

The W / Al / W laminated wiring 34 constituting the fifth layer wiring is covered with fifth interlayer insulating films 36, 37 and 38. Further, fifth interlayer insulating films 36, 37, 38
An aluminum wiring (hereinafter abbreviated as Al wiring) 39 constituting the wiring of the sixth layer is formed thereon, and the Al wiring 39 passes through the connection hole 40 to form the wiring W of the fifth layer.
/ Al / W laminated wiring 34. Note that a Cu wiring may be used as the sixth wiring.

The final passivation films 41 and 42 are formed on the Al wiring 39 constituting the wiring of the sixth layer. The final passivation film 41 is made of, for example, a silicon nitride film, and the final passivation film 42 is made of, for example, a silicon oxide film.

Final passivation films 41 and 42
On the top, BLM (Ball
Limiting Metallurgy) film 43 is formed and BL
The connection between the M film 43 and the Al wiring 39 as the sixth-layer wiring is made through the connection hole 45. The BLM film 43
It has a structure in which chromium (Cr), Cu and gold (Au) are sequentially laminated, and external terminals (bonding pads) 44 are formed on the BLM film 43.

In the first embodiment, a correction map of the irradiation amount for each shot of the electron beam is created from the size correction map of the resist pattern in the semiconductor wafer surface, and based on this, the optimum irradiation for each shot is determined. Although the resist was irradiated with the electron beam in the amount, the shot size correction map for each shot of the electron beam was created from the dimension correction map of the resist pattern in the semiconductor wafer surface, and based on this, the optimum shot was determined for each shot. The resist may be irradiated with an electron beam in size.

As described above, according to the first embodiment, when forming a fine pattern such as a wiring layer of a bipolar transistor, the irradiation amount of each shot of the electron beam in the electron beam direct writing apparatus is corrected. By that, P
Since it is possible to suppress the dimensional variation of the resist pattern due to the variation in the baking temperature of the EB process, etc.
A highly accurate resist pattern with small dimensional variations can be formed, and the dimensional accuracy of the fine pattern in the semiconductor wafer surface is improved.

(Embodiment 2) FIG. 7 shows steps 100 to 110 showing a method of correcting the dimension of a resist pattern according to another embodiment of the present invention. FIG. 7 is an example of data on the irradiation amount of the applied electron beam for each semiconductor chip.

In the second embodiment, first, steps 100 to 10 shown in FIG.
After forming a resist pattern on a semiconductor wafer in the same manner as in step 5, the dimensions of the resist pattern are measured (step 1).
05), dimensional data of the resist pattern in the semiconductor wafer surface is collected (Step 106). If the dimensional data of the resist pattern is within the standard, the position of the resist pattern is inspected for alignment (Step 107), and the process proceeds to the next step.

On the other hand, if the dimensional data of the resist pattern is out of the standard, a dimensional correction map of the resist pattern in the semiconductor wafer is created from the dimensional data of the resist pattern in the semiconductor wafer (step 108). ),
This dimension correction map is input to the electron beam direct drawing apparatus (step 109).

Next, from the dimension correction map of the resist pattern in the semiconductor wafer surface, the dose data of the electron beam for each semiconductor chip shown in FIG. 8 is created (step 110).
Thereafter, a resist having a uniform thickness is again applied to the surface of the semiconductor wafer (step 100), and then, based on the dose data of the electron beam for each semiconductor chip shown in FIG. The resist is irradiated with an electron beam at an appropriate dose (step 101).

Next, PEB treatment in step 102, step 10
After performing the cooling process 3 and the development process in step 104 on the semiconductor wafer, the dimensions of the formed resist pattern are measured (step 105).

As described above, according to the second embodiment, the dose data for each semiconductor chip of the electron beam is created from the dimension correction map of the resist pattern input to the direct electron beam drawing apparatus, Since the resist is irradiated with the electron beam at the optimal dose for the laser beam, the processing speed is improved as compared with the method in which the resist is irradiated with the electron beam at the optimal dose for each shot.

(Embodiment 3) FIG. 9 shows steps 100 to 110 showing a method of correcting the dimension of a resist pattern according to another embodiment of the present invention.

In the third embodiment, first, steps 100 to 10 shown in FIG.
After forming a resist pattern on a semiconductor wafer in the same manner as in step 5, the dimensions of the resist pattern are measured (step 1).
05), dimensional data of the resist pattern in the semiconductor wafer surface is collected (Step 106). If the dimensional data of the resist pattern is within the standard, the position of the resist pattern is inspected for alignment (Step 107), and the process proceeds to the next step.

On the other hand, when the dimensional data of the resist pattern is out of the standard, a dimensional correction map of the resist pattern in the semiconductor wafer surface is created from the dimensional data of the resist pattern in the semiconductor wafer surface (step 108). ),
This dimension correction map is input to the baking furnace control device (step 109).

Next, bake temperature data for the PEB process for each semiconductor chip is created from the dimension correction map of the resist pattern in the semiconductor wafer surface (step 110). Thereafter, a resist having a uniform thickness is applied again to the surface of the semiconductor wafer (step 100), and then the resist is irradiated with an electron beam at a substantially constant irradiation dose (step 101).

Next, a PEB process in step 102 is performed on the semiconductor wafer. In this PEB processing, the PEB processing is performed at the optimum baking temperature for each semiconductor chip based on the baking temperature data of the PEB processing for each semiconductor chip.
The dimensional variation of the resist pattern on the semiconductor wafer is reduced.

Next, after the cooling process in step 103 and the development process in step 104 are performed on the semiconductor wafer, the dimensions of the formed resist pattern are measured (step 10).
5).

As described above, according to the third embodiment, the bake temperature data of the PEB process is created for each semiconductor chip from the dimension correction map of the resist pattern input to the bake furnace control device, and the bake temperature data is created for each semiconductor chip. Since the PEB process is performed at the optimum baking temperature, the dimensional accuracy of the resist pattern is improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, in the first embodiment, the case where the method of correcting the dimension of the resist pattern is applied to the method of manufacturing the wiring of the second layer of the bipolar transistor has been described. The present invention can be applied to any method and also to any method for manufacturing a semiconductor integrated circuit device having a fine pattern.

[0068]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the dimensional accuracy of the resist pattern in the semiconductor wafer surface can be improved. It can be formed on a semiconductor wafer.

[Brief description of the drawings]

FIG. 1 is a process diagram illustrating a method for correcting a resist pattern according to an embodiment of the present invention.

FIG. 2 is a view showing dimension data of a resist pattern in a semiconductor wafer surface.

FIG. 3 shows a design dimension of a resist pattern of 0.22 μm.
FIG. 4 is a diagram showing a dimension correction map of a resist pattern in a semiconductor wafer surface with respect to FIG.

FIG. 4 is a diagram showing a correction map of an irradiation amount for each shot of an electron beam in a semiconductor wafer surface with respect to an optimum irradiation amount.

FIG. 5 is a view showing dimension data of a resist pattern in a semiconductor wafer after correcting an irradiation amount of each shot of an electron beam.

FIG. 6 is a cross-sectional view of a main part of a semiconductor substrate illustrating a bipolar transistor formed using one embodiment of the present invention.

FIG. 7 is a process chart illustrating a method of correcting a resist pattern according to another embodiment of the present invention.

FIG. 8 is a diagram showing an example of dose data of an electron beam for each semiconductor chip.

FIG. 9 is a process chart illustrating a method of correcting a resist pattern according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1a semiconductor substrate 1b silicon oxide film 1c support substrate 2 n-type epitaxial layer 3 buried n-type semiconductor region 4 silicon oxide film 4a collector opening 4b base opening 4c emitter opening 5 silicon oxide film 6 n-type for elevating Kokta potential Semiconductor region 7 p-type semiconductor region 8 p-type semiconductor region 9 n-type semiconductor region 10a tungsten wiring (first-layer wiring) 10b tungsten wiring (first-layer wiring) 10c tungsten wiring (first-layer wiring) DESCRIPTION OF SYMBOLS 11 Base extraction electrode 12a Insulation film 12b Insulation film 13 Connection hole 14 Emitter extraction electrode 15 Connection hole 16 First interlayer insulating film 17 First interlayer insulating film 18 First interlayer insulating film 19 Tungsten / aluminum / tungsten laminated Wiring (second-layer wiring) 20 Connection hole 21 Second layer Insulating film 22 Second interlayer insulating film 23 Second interlayer insulating film 24 Tungsten / Aluminum / Tungsten stacked wiring (third layer wiring) 25 Connection hole 26 Third interlayer insulating film 27 Third interlayer insulating film 28 Third interlayer insulating film 29 Tungsten / aluminum / tungsten laminated wiring (wiring of fourth layer) 30 Connection hole 31 Fourth interlayer insulating film 32 Fourth interlayer insulating film 33 Fourth interlayer insulating film 34 Tungsten / Aluminum / Tungsten laminated wiring (fifth layer wiring) 35 connection hole 36 fifth interlayer insulating film 37 fifth interlayer insulating film 38 fifth interlayer insulating film 39 aluminum wiring (sixth layer wiring) 40 connection hole 41 Final passivation film 42 Final passivation film 43 BLM film 44 External terminal (bonding pad) 45 Connection

Continued on the front page (72) Inventor Shigeki Mori 5-2-2-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. (72) Inventor Kazuhiko Sato Shinmachi, Ome-shi, Tokyo 6-chome-16 Device Development Center, Hitachi, Ltd.

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device in which a resist pattern is formed on a semiconductor wafer by using an electron beam direct writing technique, comprising: (a) applying a first resist on the semiconductor wafer; (B) drawing a pattern on the first resist with a substantially constant irradiation amount using an electron beam direct drawing apparatus; (b) performing a first baking process on the semiconductor wafer; Forming a first resist pattern on the semiconductor wafer by subjecting the semiconductor wafer to a first development process; and (d) measuring dimensions of the first resist pattern in the semiconductor wafer surface. Collecting dimension data of the resist pattern, and (e) creating a dimension correction map of the resist pattern in the semiconductor wafer surface from the dimension data of the resist pattern, (C) inputting a dimension correction map of a strike pattern into the electron beam direct writing apparatus; and (f) creating a correction map of an irradiation amount for each shot of the electron beam in the semiconductor wafer surface from the dimension correction map of the resist pattern. (G) after removing the first resist pattern, applying a second resist on the semiconductor wafer, and then using the electron beam direct writing apparatus for each shot of the electron beam. The second dose at the dose specified from the dose correction map of
Drawing a pattern on the resist, (h) performing a second baking process on the semiconductor wafer, and (i) performing a second development process on the semiconductor wafer to form a pattern on the semiconductor wafer. Forming a second resist pattern. 2. A method of manufacturing a semiconductor integrated circuit device in which a resist pattern is formed on a semiconductor wafer by using an electron beam direct writing technique, the method comprising: (a) after applying a first resist on the semiconductor wafer; Drawing a pattern on the first resist with a substantially constant shot size using an electron beam direct drawing apparatus; (b) performing a first baking process on the semiconductor wafer; (c) Forming a first resist pattern on the semiconductor wafer by subjecting the semiconductor wafer to a first development process; and (d) measuring dimensions of the first resist pattern in the semiconductor wafer surface. Collecting dimension data of the resist pattern, and (e) after creating a dimension correction map of the resist pattern in the semiconductor wafer surface from the dimension data of the resist pattern. Inputting the dimension correction map of the resist pattern to the electron beam direct writing apparatus; and (f) calculating a shot size correction map for each electron beam shot in the semiconductor wafer surface from the resist pattern dimension correction map. And (g) removing the first resist pattern, applying a second resist on the semiconductor wafer, and then using the electron beam direct writing apparatus to form a shot of the electron beam. (H) drawing a pattern on the second resist with a shot size specified from a correction map of each shot size; (h) performing a second baking process on the semiconductor wafer; Forming a second resist pattern on the semiconductor wafer by subjecting the semiconductor wafer to a second development process. Manufacturing method of the device. 3. A method of manufacturing a semiconductor integrated circuit device in which a resist pattern is formed on a semiconductor wafer by using an electron beam direct writing technique, the method comprising: (a) after applying a first resist on the semiconductor wafer; (B) drawing a pattern on the first resist with a substantially constant irradiation amount using an electron beam direct drawing apparatus; (b) performing a first baking process on the semiconductor wafer; Forming a first resist pattern on the semiconductor wafer by subjecting the semiconductor wafer to a first development process; and (d) measuring dimensions of the first resist pattern in the semiconductor wafer surface. Collecting dimension data of the resist pattern, and (e) creating a dimension correction map of the resist pattern in the semiconductor wafer surface from the dimension data of the resist pattern, (C) inputting a dimension correction map of a strike pattern to the electron beam direct writing apparatus; (f) calculating a correction map of an irradiation amount of each semiconductor chip of an electron beam in the semiconductor wafer surface from the dimension correction map of the resist pattern. (G) after removing the first resist pattern, applying a second resist on the semiconductor wafer, and then using the electron beam direct writing apparatus, the semiconductor of the electron beam (I) drawing a pattern on the second resist with an irradiation amount specified from a correction map of the irradiation amount for each chip; (h) performing a second baking process on the semiconductor wafer; Forming a second resist pattern on the semiconductor wafer by subjecting the semiconductor wafer to a second developing process. 4. A method of manufacturing a semiconductor integrated circuit device in which a resist pattern is formed on a semiconductor wafer by using an electron beam direct writing technique, the method comprising: (a) applying a first resist on the semiconductor wafer; Drawing a pattern on the first resist at a substantially constant dose using an electron beam direct drawing apparatus; and (b) using a baking furnace to apply a pattern on the semiconductor wafer at a substantially constant baking temperature. (C) forming a first resist pattern on the semiconductor wafer by subjecting the semiconductor wafer to a first development process; and (d) forming a first resist pattern on the semiconductor wafer. Collecting dimensions data of the resist pattern by measuring the dimensions of the first resist pattern within the resist pattern; and (e) resist pattern patterns in the semiconductor wafer surface from the dimension data of the resist pattern. Inputting the resist pattern dimensional correction map to the baking furnace after preparing the resist pattern dimensional correction map; and (f) baking each semiconductor chip in the semiconductor wafer surface from the resist pattern dimensional correction map. Creating a temperature correction map, and (g) applying a second resist on the semiconductor wafer after removing the first resist pattern, and then using the electron beam direct writing apparatus, Drawing a pattern on the second resist at a substantially constant dose, and (h) using the bake furnace at a bake temperature specified from a bake temperature correction map for each semiconductor chip. Performing a second baking process on the wafer; and (i) forming a second resist pattern on the semiconductor wafer by performing a second development process on the semiconductor wafer. The method of manufacturing a semiconductor integrated circuit device characterized by having a that step. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a first baking process is performed on the semiconductor wafer, and a first developing process is performed on the semiconductor wafer. Performing a cooling process on the semiconductor wafer between the performing the second baking process on the semiconductor wafer and performing the second developing process on the semiconductor wafer. A method for manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the dimension of the first resist pattern is measured at three to five points in the semiconductor chip. A method for manufacturing a semiconductor integrated circuit device. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first bake processing and said second bake processing are performed at a temperature of 100 ° C. or less. A method for manufacturing a semiconductor integrated circuit device, wherein the method is performed on a wafer. 8. A manufacturing apparatus of a semiconductor integrated circuit device for forming a resist pattern on a semiconductor wafer by using an electron beam direct writing technique, wherein the resist pattern is corrected from the dimension correction map of the resist pattern on the surface of the semiconductor wafer. A correction map of the irradiation amount for each shot or a correction map of a shot size for each shot of the electron beam is created, and the irradiation amount specified for each shot of the electron beam or the correction map for the shot of the electron beam. An apparatus for manufacturing a semiconductor integrated circuit device, wherein a pattern is drawn on a resist applied on a semiconductor wafer with a shot size specified from a shot size correction map. 9. A manufacturing apparatus for a semiconductor integrated circuit device for forming a resist pattern on a semiconductor wafer by using an electron beam direct writing technique, comprising: A correction map of the irradiation amount for each semiconductor chip is created, and a pattern is drawn on the resist applied on the semiconductor wafer with the irradiation amount specified from the correction map of the irradiation amount for each semiconductor chip of the electron beam. An apparatus for manufacturing a semiconductor integrated circuit device. 10. A semiconductor integrated circuit device manufacturing apparatus for performing a baking process on a semiconductor wafer after drawing a pattern on a resist applied on the semiconductor wafer, wherein the resist pattern dimension correction in the semiconductor wafer surface is performed. A semiconductor, wherein a bake temperature correction map for each semiconductor chip is created from the map, and the semiconductor wafer is baked at a bake temperature specified from the bake temperature correction map for each semiconductor chip. Manufacturing equipment for integrated circuit devices.