JPH03228345A - Semiconductor chip and inspection of the chip - Google Patents

Abstract

PURPOSE:To make an inspection of the external shape of a chip easily using a simple instrument by establishing a metal layer around an active area of a circuit pattern. CONSTITUTION:This element chip is provided with a circuit pattern and a metal layer 4 which is established around an active area 2 of the circuit pattern. In an inspection of the said semeconductor chip 1, the following three processes should be included; a contacting process in which electric contact devices are brought into contact with at least two points on the metal layer 4 established around the active area 2, a measuring process in which a resistance value is measured between the above electric contact devices and a process in which the external shape of the chip 1 is decided based on the resistance value measured in the said measuring process. Take the following as example. The width of the metal layer 4 is 20-30mum. On four corners of the metal layers 4, exposed sections 4a-4b are formed which is the metal layer a part of which is exposed from a protection film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor element chip and a method for testing the element chip.

[Conventional technology]

When forming a semiconductor circuit element, first, a plurality of circuit patterns are formed on a semiconductor substrate using photolithography technology, impurity ion implantation technology, etc., and after conducting electrical tests on each circuit pattern, A semiconductor wafer is pasted on an expandable tape and cut along scribe lines with a diamond blade or the like to separate each semiconductor element chip. The divided semiconductor element chips are then picked up from the expanding tape and mounted in a package.

During this element chip division, the active area of the element chip may be damaged, and in order to inspect whether such damage has occurred, the outer shape of the element chip is inspected immediately before pickup.

This external shape inspection is important from the point of view of securing the product yield afterwards. Conventionally, the external shape of the semiconductor element chip is input as an image of the divided semiconductor element chip using a TV monitor, etc., and the input image information is processed by a computer. However, by extracting the external shape, the condition of the external shape was determined and the external shape was inspected.

[Problem to be solved by the invention]

However, the above-mentioned external inspection method requires expensive equipment, which increases the equipment cost, and the illumination equipment must be adjusted because the reflectance of the semiconductor element chip varies depending on the type of element chip. This resulted in high work costs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element chip and an element chip testing method that solve the above-mentioned problems.

[Failure to solve the problem]

The semiconductor element chip of the present invention is characterized by comprising a circuit pattern and a metal layer provided around the outside of the active area of the circuit pattern so as to surround the active area.

Furthermore, the inspection method of the present invention is a method of inspecting the semiconductor element chip described above, comprising: bringing electrical contact means into contact with at least two points of the metal layer provided around the active area; The method is characterized in that the resistance value between the two is measured, and the external shape of the element chip is determined based on the resistance value measured in the measurement step.

[Effect]

As described above, in the semiconductor element chip of the present invention, a metal layer is formed so as to surround the outside of the active area. If chipping occurs at the periphery of the element chip during division during dicing, this metal layer will also be damaged. Therefore, by monitoring the state of this metal layer, it is possible to monitor the external shape of the element chip, and by extension, it is possible to determine whether the active area within the element chip is damaged.

Furthermore, the resistance value of the metal layer depends on its shape, and if the metal layer provided on the outer periphery of the semiconductor element chip is damaged, for example, when the outer periphery of the semiconductor element chip is damaged, When this occurs, the metal layer is also damaged, its width becomes narrower, and in the worst case, it is cut off, increasing its resistance value. Therefore, the resistance value of the metal layer is monitored,
By comparing with a predetermined value, the outer shape of the element chip can be inspected.

〔Example〕

Embodiments according to the present invention will be described below with reference to the drawings.

Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.

FIG. 1 shows a state before a semiconductor element chip, which is an embodiment according to the present invention, is divided into individual chips. As shown in FIG. 1, a plurality of semiconductor element chips 1 are formed on a semiconductor substrate via scribe lines 2 before being divided. Each semiconductor element chip 1 has a circuit pattern, that is, an active area 3 and a metal layer 4 surrounding the active area 2 in a ring shape. The width of this metal layer 4 is 20 to 30 μm.

Further, at the four corners of the metal layer 4, there are metal layer exposed portions 4 a s where a part of the metal layer is exposed from a protective film (not shown).
4b, 4c, and 4d are formed. The formation of the metal layer 4 is performed simultaneously with the formation of an electrical wiring layer and patterning, which are always carried out in circuit pattern formation. Furthermore, the metal layer 4 can be exposed from the protective film (not shown) at the same time as the step of exposing the bonding pads during the formation of the semiconductor element chip. In this way, the formation of the metal layer 4 and the exposure of a predetermined portion of the semiconductor element chip 1 of the above embodiment can be accomplished by simply changing the pattern of the photomask during the conventional semiconductor integrated circuit manufacturing process, thereby increasing the number of steps. It can be easily implemented.

Next, a method for inspecting the external shape of the semiconductor element chip of the above embodiment will be explained.

FIG. 2 shows the shape of a semiconductor element chip 1 divided from a semiconductor wafer. When dividing a semiconductor element chip, if the semiconductor element chip is divided normally and there is no chipping around the outer shape or the chipping does not damage the metal layer (Figure 2 (a)), There are cases where the metal layer 4 is not divided properly and a part of the metal layer 4 is damaged due to chipping or the like (FIG. 2(b)).

In the external shape inspection of the semiconductor element chip, which of the above two cases is detected is inspected by measuring the resistance value of the metal layer. First, 4 of the semiconductor element chips
Metal layer exposed parts 4a, 4b, 4c-, 4d provided at the corners
A probe for electrical measurement is brought into contact with the probe, and the resistance value between the probes is measured.

As shown in FIG. 2(a), each side of the metal layer 4 5a%5
The resistance values of b, 5c, and 5d are R and R, respectively.

2 R3 and R4, the electrical equivalent circuit between the exposed parts of the metal layer becomes a bridge circuit as shown in FIG. 3(a). Next, the resistance values R, R, and R of each side 5a s5b, 5c, and 5d of the metal layer 4 are calculated by calculating the resistance value between the measured exposed portions of each metal layer.

1 2 3 R4 is determined and compared with a predetermined value, that is, the resistance value before being divided into semiconductor element chips. If these values have a certain relationship with the resistance value before dividing into semiconductor element chips, for example, if they are less than twice the resistance value before dividing,
It is judged to be a good product.

On the other hand, as shown in FIG. 2(b), if chipping occurs on the sides 5C and 5d of the semiconductor element chip, and a part of the metal layer formed in those areas is damaged, As shown in FIG. 3(b), the resistance values RR of the sides 5c and 5d of the metal layer 4 are increased compared to the respective resistance values R3R4 before the semiconductor element chips are divided. This is because the metal layers on sides 5c and 5d are damaged, resulting in narrowing the width and increasing the resistance value, or in the worst case, breaking the wire and causing the resistance value to increase significantly. . And the resistance value of each side is
If the resistance value is more than double the resistance value before division, the metal layer corresponding to that side is damaged and the active area is considered to be affected in some way, and the product is determined to be defective. Then, this semiconductor element chip is not mounted on a package.

Further, in the above inspection method, as a method of bringing the probe into contact with the exposed portion of the metal layer, a collet used when picking up a semiconductor element chip from an expanded tape can be used. In this method, probes are built into a collet used for pickup, and configured so that these probes come into contact with the exposed portion of the metal layer when the collet is picked up. During pickup, the resistance value is measured and calculated, and if it is determined to be defective, the semiconductor element chip is discarded without die bonding to a lead frame or the like. However, instead of providing the probe inside the collet as described above, a probe card may be provided separately and the resistance value may be measured using this.

Then, by measuring at four points as in the above example,
The chip damage state of the semiconductor element chip can be seen on a weekly basis, making it possible to more precisely inspect the external shape of the element chip and systematically monitor in which direction chipping is more common.

The present invention is not limited to the above embodiments, and various modifications may be made.

Specifically, in the above embodiment, the metal layer is provided between the scribe line and the active area, but it may be provided on the scribe line. By doing so, it is possible to make the active area wider.

Further, in the above embodiment, four locations of the metal layer are exposed and measurements are performed at the four exposed locations, but the number of measurement points is not limited to this and may be larger or smaller. Note that measurement accuracy can be increased by increasing the number of measurement points.

〔Effect of the invention〕

In the semiconductor element chip of the present invention, as explained earlier,
The outer shape of an element chip can be inspected easily using a simple device.

Further, in the method for inspecting the external shape of an element chip of the present invention, damage to an element chip can be easily and easily detected, and the state of occurrence of chipping can be systematically determined.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a state before division of an embodiment of a semiconductor element chip according to the present invention, FIG. 2 is a diagram showing a state when the semiconductor element chip shown in FIG. 1 is divided, and FIG. FIG. 3 is a diagram showing an equivalent bridge circuit of the metal layer of the divided semiconductor element chip shown in FIG. 2; DESCRIPTION OF SYMBOLS 1... Semiconductor element chip, 2... Active area, 3... Scribe line, 4... Metal layer, 4 a
% 4 b -4Cs 4 d "'Metal layer exposed part,
5a, 5b, 5c. 5d...Each side of the metal layer.

Claims (1)

[Claims] 1. A semiconductor element chip comprising: a circuit pattern; and a metal layer provided around the outside of an active area of the circuit pattern so as to surround the active area. 2. The method for inspecting a semiconductor element chip according to claim 1, further comprising: a contacting step of abutting electrical contact means on at least two points of a metal layer provided around the active area; and a contacting step between the electrical contact means. A method for inspecting an element chip, comprising: a measuring step of measuring a resistance value of the element chip; and a step of determining an outer shape of the element chip based on the resistance value measured in the measuring step.