JPH04330762A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the fluctuation in the contact resistance to be measured with high precision by a method wherein a contact in the same size and shape as those of a contact to be inspected is formed on an emitter diffused layer while the emitter diffused layer in the size sufficiently larger than that of the contact is formed. CONSTITUTION:An emitter contact 10 in the same size and shape as those of a contact to be inspected is formed using the emitter contact 10 as an object of inspection. At this time, the plane size of an emitter diffused layer 8 wherein the emitter contact 10 is provided is made sufficiently larger than that of the contact 10 thereby enabling the contact 10 to be formed into a flat surface. Through these procedures, the contact 10 can be inspected measuring the emitter resistance thereby enabling the contact resistance to be inspected with high precision regardless of the variation in the contact resistance due to the variation in the size of lithography.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and more particularly to a structure for testing contact characteristics.

0002

2. Description of the Related Art In recent years, semiconductor integrated circuits have become faster and more highly integrated. Therefore, the pn junction is made shallower, and the plane dimension of the impurity diffusion layer is also reduced. In such high-performance, highly integrated semiconductor integrated circuits, various contact structures have been proposed to ensure high yield and reliability of the contact between the impurity diffusion layer and the wiring metal. There is. For example, a contact between an impurity diffusion layer and a metal wiring is required to have low contact resistance and ohmic characteristics, and to have barrier properties against the wiring metal such that junction breakdown does not occur as in the case of alloy spikes. In order to achieve such contact characteristics, a multilayer metal structure has conventionally been incorporated into the contact portion. As an example, a metal silicide layer, typically platinum silicide, is formed on the surface of the impurity diffusion layer for the purpose of improving ohmic properties, and a barrier metal layer, typically titanium nitride, is formed on top of the metal silicide layer to maintain barrier properties with the wiring metal. One example is a multilayer structure in which a layer is formed and a wiring metal, typically aluminum, is formed on the layer.

[0003] As a means of inspecting the electrical characteristics of such a contact portion during the manufacturing process or after the completion of the wafer process, conventionally the impurity diffusion layer and the wiring metal are connected in a chain via a contact, and the resistance value is determined. A commonly used method is to measure.

0004

[Problems to be Solved by the Invention] As mentioned above, when the contact portion becomes a multilayer structure and the contact dimensions become smaller due to higher integration, the interface between the silicide layer and the barrier metal layer or between the barrier metal layer and the wiring metal layer becomes Even the presence of a small amount of insulating layer at the interface can result in poor contact conduction. On the other hand, the above-mentioned inspection method using a pattern in which a conductivity type impurity diffusion layer and a wiring metal are connected in a chain via a contact always includes the resistance of the impurity diffusion layer, but generally the resistance of the impurity diffusion layer of a semiconductor integrated circuit is included. Sheet resistance is 10
The contact resistance is in the range of 0Ω/□ to several KΩ/□, whereas the contact resistance is on the order of several Ω, and it cannot be said that the sensitivity for detecting fluctuations in contact resistance is high. Furthermore, it is necessary to consider the tolerance of the impurity diffusion layer due to dimensional variations due to lithography, etc., and variations in contact resistance may be absorbed by this, leading to the risk of overlooking variations in contact resistance, which may affect the reliability of semiconductor integrated circuits. It will also have a significant impact. An object of the present invention is to provide a semiconductor integrated circuit that allows variation in contact resistance to be measured with high precision.

[0005]

[Means for Solving the Problems] In the semiconductor integrated circuit of the present invention, an emitter contact formed on an emitter diffusion layer is formed in the same size and shape as a contact for testing contact characteristics, and the emitter contact is formed on the emitter diffusion layer. The planar dimensions of the emitter contact are made sufficiently larger than those of the emitter contact.

[0006]

According to the present invention, by measuring the emitter resistance, it is possible to measure and test the required contact resistance, and it is possible to test the contact resistance with high accuracy.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows a first embodiment of the present invention.
) shows a plan view, and figure (b) shows a cross-sectional view taken along line A-A in figure (a). As shown in the figure, a bipolar transistor provided in a semiconductor integrated circuit is a semiconductor substrate 1.
A collector buried layer 2 is formed on the surface of the semiconductor device, an epitaxial layer 3 is grown thereon, and the epitaxial layer 3 is separated by a LOCOS oxide film 4 to define an element region. Then, a base diffusion layer 5, a collector diffusion layer 6, and a graft base diffusion layer 7 are formed in the epitaxial layer 3, an emitter diffusion layer 8 is formed in the base diffusion layer 5, and an insulating film 9 is formed on the entire surface. An emitter contact 10, a base contact 11, and a collector contact 12 are opened to each of the diffusion layers. These contacts 10
, 11, 12 have a silicide layer 13 and a barrier metal 14.
are formed, and a wiring metal 15 is connected to the probe pad 16 via these.

Here, the emitter contact 10 is used as a contact to be inspected in this semiconductor integrated circuit, and this emitter contact 10 is formed to have the same dimensions and the same shape as the contact to be inspected. The planar dimension of the emitter diffusion layer 8 is made sufficiently larger than the contact dimension so that the contact is opened in a flat surface. In this way, by making the planar dimensions of the emitter diffusion layer 8 sufficiently larger than the dimensions of the emitter contact 10, the influence of dimensional errors in lithography on fluctuations in the resistance component of the emitter resistance in the diffusion layer becomes extremely small. In addition, in the depth direction, the emitter of a bipolar transistor is generally formed with sufficient precision, so there is no large variation in the depth direction. Furthermore, 70 to 80% of the components constituting the emitter resistance can be considered to be contact resistance components. Therefore, by measuring the emitter resistance using the emitter contact 10 and evaluating the measured value, it is possible to accurately inspect the variation in contact resistance in this semiconductor integrated circuit.

FIG. 2 shows a method for testing emitter resistance.
As shown in , when base current Ib flows with the collector open, the potential VC at the collector terminal becomes VC
It is expressed as =ΔVCE+re Ib. Here, under conditions where ΔVCE can be regarded as constant, re = ΔVC /ΔIb.

FIG. 3 is a plan view showing a second embodiment of the present invention. In this embodiment, a plurality of contacts 10A and 10B of different sizes and shapes are formed on the emitter diffusion layer 8 of the same bipolar transistor, and each contact is connected to a probe pad 16. According to this configuration, it is possible to inspect a plurality of (two) contacts of different shapes using one emitter diffusion layer. This example also has the advantage that relative values of contact resistance due to differences in contact shape can be compared with high accuracy.

Incidentally, the sheet resistance ρS of the emitter diffusion layer in a conventional bipolar transistor is 100 Ω.
/□, the emitter diffusion layer dimension W (diffusion layer width) is 5 μm, the dimension L between contacts is 5 μm, and the dimensional fluctuations ΔW and ΔL in the lithography and etching processes are ±0.5, respectively.
μm, if the contact resistance RC is 5Ω, the maximum series resistance of the two contacts and one diffusion layer of this bipolar transistor is 132Ω and the minimum is 91.8Ω, and the contact resistance RC is constant. Despite this, there is a difference of 30%. In contrast, in the present invention, by making the emitter diffusion layer dimension W sufficiently large, the error due to variations in the emitter diffusion layer depth and impurity concentration is extremely small, and is less than 10% in the resistance component. Furthermore, the component of the measured value due to the diffusion layer can be reduced to about 3Ω by making the diffusion layer large for one contact, so the measured value is based on the contact resistance RC of 5Ω.
Assuming Ω, the maximum is 8.3 Ω and the minimum is 7.7 Ω, so the difference can be suppressed to about 7.8%.

0012

As explained above, the present invention forms a contact having the same size and shape as the contact to be inspected in the emitter diffusion layer, and also forms the emitter diffusion layer sufficiently larger than the contact. Therefore, the contact can be inspected by measuring the emitter resistance, and the contact resistance can be inspected with high precision regardless of the variation in the contact resistance due to dimensional variations in lithography.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the present invention, (a) is a plan view;
(b) is a sectional view taken along the line A-A.

FIG. 2 is a circuit diagram for explaining a method of measuring emitter resistance.

FIG. 3 is a plan view of a second embodiment of the invention.

[Explanation of symbols]

5 Base diffusion layer 6 Collector diffusion layer 7 Graft base diffusion layer 8 Emitter diffusion layer 10, 10A, 10B Emitter contact 13
Silicide 14 Barrier metal 15 Wiring metal

Claims (1)

[Claims] 1. In a semiconductor integrated circuit including a bipolar transistor, an emitter contact formed on an emitter diffusion layer is formed in the same size and shape as a contact for testing contact characteristics, and the planar dimensions of the emitter diffusion layer are A semiconductor integrated circuit characterized in that the emitter contact is formed sufficiently large in size relative to the size of the emitter contact.