JP2002141474A - Planar semiconductor chip, testing method therefor and semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a planar semiconductor chip of structure capable of surely finding the formation defect of an electrode. SOLUTION: This planar semiconductor chip is provided with a semiconductor formed on a silicon substrate and an annular guard ring electrode provided on the surface of the silicon substrate surrounding the semiconductor chip. The guard ring electrode is provided with a probing pad part for probe tests.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar type semiconductor chip, a test method therefor, and a semiconductor wafer, and more particularly, to a planar type semiconductor chip provided with a ring-shaped electrode such as a channel stopper around a semiconductor chip. INDUSTRIAL APPLICABILITY The present invention is effective for finding an abnormality of a surface electrode which is likely to occur near the outer periphery of a semiconductor wafer when manufacturing a semiconductor chip by a wafer test.

[0002]

2. Description of the Related Art FIG. 15 is a plan view showing only surface electrodes of a conventional semiconductor chip (planar type power transistor). FIG. 16 is a plan view of the semiconductor chip shown in FIG.
It is sectional drawing. As shown in FIGS. 15 and 16, a base electrode 2 and an emitter electrode 3 are provided on the surface of a silicon substrate 1. Further, a ring-shaped guard ring electrode 4 is provided around the base electrode 2 at the same potential as the collector electrode 21 on the back surface and in contact with the N ⁺ diffusion layer 24 as a channel stopper around the silicon substrate 1. I have.

Usually, a semiconductor chip 701 has an Al
An electrode and an Au electrode and a multilayer electrode for solder are provided on the back surface. Each of these electrodes is formed by an electron beam evaporation method or a sputtering method. Further, when the electrodes on the surface are separated into the base electrode 2, the emitter electrode 3, and the guard ring electrode 4, respectively, a photolithography step and an etching step are performed.

FIG. 17 is an explanatory view showing a semiconductor wafer 801 on which a plurality of the above-described semiconductor chips 701 shown in FIGS. 15 and 16 are formed. As shown in FIG. 17, a non-arranged portion 10 where the semiconductor chip 701 is not arranged exists around the semiconductor wafer 801. This is mainly due to the structure of a semiconductor manufacturing apparatus (not shown),
This is because normal processing cannot be performed for a few mm in the vicinity of 1, and various troubles such as damage to the wafer due to contact with a manufacturing apparatus or a carrier (not shown) are likely to occur.

[0005] Among various inconveniences, in particular, regarding an electrode, an electrode may not be formed or a film thickness may be reduced at a portion where a semiconductor wafer and a manufacturing apparatus are fixed. Furthermore, when the electrodes are separated into each electrode such as a base electrode and an emitter electrode, if the etching is performed by a batch type etching apparatus using a wafer carrier, the periphery of the semiconductor wafer in contact with the wafer carrier may not be properly etched. is there.

When the collector electrode is formed on the back surface of the silicon substrate, the electrode material of the collector electrode may reach the peripheral portion on the front surface side of the silicon substrate.
These defects are difficult to completely remove by a wafer test if the degree is small, and if they cannot be removed, defective semiconductor chips will be shipped.

Therefore, in order to prevent a defective semiconductor chip from being shipped, it is necessary to increase a portion where no semiconductor chip is formed around the semiconductor wafer.

[0008]

When the portion where no semiconductor chips are arranged around the semiconductor wafer is increased, the number of semiconductor chips that can be obtained from one semiconductor wafer decreases accordingly. In addition, as described above, defects related to electrodes are likely to occur around the semiconductor wafer, but scratches due to contact with the device and pinholes in the photoresist film due to the photolithography process also occur at the center of the semiconductor wafer. May be. However, it has been difficult for conventional wafer tests and appearance inspections to find these defects without omission.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a planar semiconductor chip having a structure capable of reliably detecting a defective formation of an electrode formed on the surface of a semiconductor chip, and a test method therefor. Is what you do.

[0010]

SUMMARY OF THE INVENTION The present invention comprises a semiconductor chip formed on a silicon substrate and a ring-shaped guard ring electrode provided on the surface of the silicon substrate and surrounding the semiconductor chip. And a planar type semiconductor chip provided with a probing pad portion.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a planar type semiconductor chip according to the present invention, the semiconductor chip is a power transistor, and the power transistor has a collector layer on the back side,
A silicon substrate having a base diffusion layer and an emitter diffusion layer on the front surface side, a collector electrode provided on the back surface of the silicon substrate, and a base electrode and an emitter electrode provided on the surface of the silicon substrate may be provided.

In the planar type semiconductor chip according to the present invention, the guard ring electrode may be square, and the probing pads may be provided at four corners of the guard ring electrode.

Further, in the planar type semiconductor chip according to the present invention, the guard ring electrode may be rectangular, and the probing pad portions may be provided at two opposing corners of the guard ring electrode.

Further, in the planar type semiconductor chip according to the present invention, the guard ring electrode may be rectangular and one corner thereof is separated, and a probing pad portion may be provided at two ends formed thereby.

Further, in the planar type semiconductor chip according to the present invention, the probing pad portion is substantially square,
One side thereof may be wider than the width of the guard ring electrode.

Further, in the planar type semiconductor chip according to the present invention, the guard ring electrode is provided with an insulating film between the guard ring electrode and the silicon substrate, and a contact portion for contacting the silicon substrate only at a predetermined position of the guard ring electrode is provided. You may.

In the planar type semiconductor chip according to the present invention, the guard ring electrode is square, and the probing pad portions are provided at four corners of the guard ring electrode.
The contact portion may be provided substantially at the center between two adjacent probing pad portions.

Further, in the planar type semiconductor chip according to the present invention, the contact portion may be rectangular, and one short side thereof may be wider than the width of the guard ring electrode.

Further, in the planar type semiconductor chip according to the present invention, the guard ring electrode is adjacent to the base electrode, and the guard ring electrode and the base electrode have such a distance that the breakdown voltage of the semiconductor chip is not affected. Good.

Further, in the method of testing a planar semiconductor chip according to the present invention, a probe needle is applied to a probing pad of a guard ring electrode to measure a resistance value, and a defective electrode formation of the semiconductor chip is estimated based on the measurement result. A test method may be used.

The present invention also provides a semiconductor wafer on which a plurality of semiconductor chips are formed, wherein each of the chips formed around the semiconductor wafer has the above-mentioned planar type semiconductor according to the present invention. It may be a chip.

This takes into account that, in a semiconductor wafer, electrode formation failure of each semiconductor chip formed on the semiconductor wafer is likely to occur at the periphery of the semiconductor wafer. With this configuration, a defective semiconductor chip can be efficiently found and removed without changing the structure of the semiconductor chip disposed near the center of the semiconductor wafer from the conventional one.

As described above, in the planar type semiconductor chip according to the present invention, the guard ring electrode is provided with the probing pad for the probe test. This makes it possible to measure the resistance value of the guard ring electrode by applying a probe needle to the probing pad during a wafer test.
If the guard ring electrode has a formation defect such as cutting, insufficient film thickness, or defective shape, the resistance value is higher than that of a normal guard ring electrode, and thus a formation defect of the guard ring electrode is found. Then, if a formation failure of the guard ring electrode is found, it is assumed that a formation failure has occurred in other electrodes provided on the surface of the semiconductor chip, and the chip is removed.

In the case where the electrode material of the electrode provided on the back surface of the semiconductor chip is formed around the surface of the semiconductor chip, the leakage current between the guard ring electrode and the electrode provided adjacent to the guard ring electrode is measured. Can be discovered by Further, a defective contact state between the silicon substrate and the guard ring electrode can be found by measuring a resistance value between the guard ring electrode and an electrode provided on the back surface of the semiconductor chip. If a defect in the contact state between the guard ring electrode and the silicon substrate is found, it is estimated that a similar contact state defect has occurred in the other electrodes provided on the surface of the semiconductor chip, and the chip is referred to. Remove.

According to the present invention, as described above, a defective formation of the electrode provided on the surface of the semiconductor chip can be reliably found and the semiconductor chip can be removed, so that the semiconductor chip is formed on the entire surface of the semiconductor wafer. Will be able to do it. Therefore, the number of semiconductor chips that can be obtained from one semiconductor wafer increases, and the cost of the semiconductor chips can be reduced.

The electrode structure according to the present invention is not limited to a power transistor but can be widely applied as an electrode structure of a semiconductor chip in which a ring-shaped electrode is formed around a semiconductor chip.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited by the embodiment.

Embodiment 1 A planar semiconductor chip (PNP power transistor) according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a semiconductor chip according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA of FIG.
FIG. 2 is an explanatory diagram showing a state where a probe test is performed on the semiconductor chip shown in FIG. 1.

As shown in FIG. 1, a planar semiconductor chip 101 according to the first embodiment of the present invention includes a semiconductor chip 101 formed on a silicon substrate 1 and a semiconductor chip 101 provided on the surface of the silicon substrate 1. And a ring-shaped guard ring electrode 4 surrounding the probe ring. The guard ring electrode 4 is provided with a probing pad section 5 for probe testing.

More specifically, as shown in FIGS. 1 and 2, the semiconductor chip 101 includes a base diffusion layer 22 formed by N-type impurity diffusion and an emitter diffusion layer formed by P ⁺ -type impurity diffusion on a P-type silicon substrate 1. 23 are formed. A channel stopper diffusion layer 24 is formed around the base diffusion layer 22.

Silicon substrate 1 after each diffusion layer is formed
An oxide film 25 is formed as an insulating film on the surface of the silicon substrate 1, and a contact window is provided in a portion that makes contact with each diffusion layer, and then an Al film is formed on the entire surface of the silicon substrate 1. Thereafter, the Al film is etched to separate into a base electrode 2, an emitter electrode 3, and a guard ring electrode 4, and a collector electrode 21 such as a solder electrode is formed on the back surface of the silicon substrate 1.

As shown in FIG. 1, probing pad portions 5 for probe testing are provided at the corners of the quadrangular guard ring electrode 4, respectively. Since the well-known technique has already been used for the above-described impurity diffusion and electrode forming steps, detailed description of the manufacturing steps will be omitted.

When performing the probe test on the semiconductor chip 101 shown in FIGS. 1 and 2, the probe needles 26 of the resistance value measuring circuit 13 are respectively connected to the two probing pads 5 as shown in FIG. Then, a current is applied to the guard ring electrode 4 to measure the resistance value.

As shown in FIG. 3, when the guard ring electrode 4 has a defective portion 12 due to a scratch or the like, the resistance 14 of the defective portion 12 becomes large, so that the resistance value of the entire guard ring electrode 4 is normal. Higher than the ones. The same applies when a defect such as disconnection or insufficient film thickness occurs in the guard ring electrode 4.

Second Embodiment Next, a planar semiconductor chip according to a second embodiment of the present invention will be described with reference to FIG. The members having the same names as those in the first embodiment will be described using the same reference numerals.

FIG. 4 shows a second embodiment of the present invention.
In the planar type semiconductor chip 201 according to (1), the probing pad portions 5 are arranged only at two opposing corners. Other configurations are the same as those of the semiconductor chip 101 according to the first embodiment (see FIGS. 1 and 2).

This takes into account the fact that alignment marks and identification marks (both not shown) used during photolithography are often provided around the semiconductor chip, especially near the corners. 2 facing as described above
When the probing pad portion 5 is provided only at one corner portion, an alignment mark or an identification mark can be provided at two corner portions where the probing pad portion 5 is not provided.

Third Embodiment Next, a planar type semiconductor chip according to a third embodiment of the present invention will be described with reference to FIGS. Note that members having the same names as those in the first and second embodiments will be described using the same reference numerals.

As shown in FIG. 5, in the planar type semiconductor chip 301 according to the third embodiment of the present invention, the guard ring electrode 4 is separated at one corner thereof, and is formed at two ends formed thereby. A probing pad section 5 is provided. Other configurations are the same as those of the above-described semiconductor chip 101 according to the first embodiment (see FIGS. 1 and 2). With this configuration, alignment marks and identification marks can be provided at three corners where the probing pad 5 is not provided.

The above-described semiconductor chip 301 shown in FIG.
When the probe test is performed, as shown in FIG.
The probe needles 26 of the resistance value measuring circuit 13 are respectively applied to two adjacent probing pad portions 5. In the semiconductor chip 301 according to the third embodiment, since the path of the current flowing between the two probing pad portions 5 is limited to one,
Even if the defective portion 12 occurs in any part of the guard ring electrode 4, the measured resistance value greatly changes, and a highly accurate probe test can be performed.

Embodiment 4 Next, a planar type semiconductor chip according to Embodiment 4 of the present invention will be described with reference to FIG. Note that members having the same names as those in the above-described first to third embodiments will be described using the same reference numerals. As shown in FIG. 7, in the planar type semiconductor chip 401 according to the fourth embodiment of the present invention, the electrode width W of the guard ring electrode 4 is changed to the semiconductor chip 101 according to the above-described first to third embodiments (see FIGS. 2 (see FIG. 2), 201 (see FIG. 4), and 301 (see FIG. 5). Other configurations are the same as those of the first embodiment.
1 (see FIGS. 1 and 2).

When the electrode width W of the guard ring electrode 4 is reduced, when the guard ring electrode 4 has a defective portion,
When the thickness of the guard ring electrode 4 is insufficiently formed, the rate of increase in the resistance value increases, and a highly accurate probe test can be performed. The guard ring electrode 4 has at least a channel stopper diffusion layer 24 (FIG. 2) so as not to lose the original purpose of the guard ring electrode.
(Refer to FIG. 3).

Therefore, when the guard ring electrode 4 is made thinner as in the fourth embodiment, only the outer portion of the guard ring electrode 4 having a normal electrode width (see FIGS. 1 and 2) is omitted. To do. Thus, the configuration in which the guard ring electrode 4 is made thin can be applied to any of the first to third embodiments.

Fifth Embodiment Next, a planar semiconductor chip according to a fifth embodiment of the present invention will be described with reference to FIGS. The members having the same names as those in the first to fourth embodiments are described using the same reference numerals.

As shown in FIGS. 8 and 9, a planar semiconductor chip 501 according to Embodiment 5 of the present invention
Guard ring electrode 4 and channel stopper diffusion layer 24
Is a contact portion 7 having a small area.

Then, the central portion 6 of the contact portion 7 (FIG. 8)
(Indicated by a broken line in FIG. 2) actually contacts the channel stopper diffusion layer 24. Other configurations are the same as those of the semiconductor chip 101 according to the first embodiment (FIG. 1).
And FIG. 2).

Semiconductor chip 501 according to the fifth embodiment
Is effective for detecting a defect in the film thickness of the guard ring electrode 4 and a defect in the contact state between the guard ring electrode 4 and the channel stopper diffusion layer 24. That is, as shown in FIG. 9, when the thickness of the contact portion 7 is normal, the contact portion 7 has no disconnection in the step portion 15 between the oxide film 25 and the channel stopper diffusion layer 24.

However, as shown in FIG. 10, when the thickness of the contact portion 7 is small, the contact portion 7
And the channel stopper diffusion layer 24 cannot be covered with the stepped portion 15, and a step break occurs. When the disconnection occurs, conduction between the guard ring electrode 4 (FIG. 8) and the channel stopper diffusion layer 24 is lost, or the resistance value is significantly increased.

For this reason, as shown in FIG. 11, one probe needle 26 is applied to the contact portion 7 and the other probe needle 26 is applied to the collector electrode 21 to measure the resistance value. 8) The defect of the film thickness and the defect of the contact state between the guard ring electrode 4 and the silicon substrate 1 can be reliably found.

The step portion 15 shown in FIGS. 10 and 11 is a portion where the channel stopper diffusion layer 24 is formed on the portion where the base diffusion layer 22 is not formed.
This is the portion with the largest step in the semiconductor chip 501.
Therefore, if it is confirmed that the contact portion 7 has no disconnection in the step portion 15, it can be assumed that no disconnection has occurred in the other electrodes provided on the surface of the semiconductor chip 501.

As shown in FIG. 8, in the above-described semiconductor chip 501 according to the fifth embodiment, in consideration of the easiness of the test and the contact between the guard ring electrode 4 and the channel stopper diffusion layer 24, the contact portion is formed. 7 were provided at four places. However, although not shown, the contact portion 7 may be provided only at one arbitrary corner portion in order to further increase the detection accuracy.

Embodiment 6 Next, a planar type semiconductor chip according to Embodiment 5 of the present invention will be described with reference to FIGS. The members having the same names as those in the first to fifth embodiments are described using the same reference numerals.

As shown in FIG. 12, in the planar semiconductor chip 601 according to the sixth embodiment of the present invention, the distance S between the guard ring electrode 4 and the base electrode 2 does not affect the withstand voltage and other characteristics. The range is narrow. Other configurations are the same as those of the semiconductor chip 101 according to the first embodiment (FIG. 1).
And FIG. 2).

With this configuration, as shown in FIG. 13, when the electrode material goes around the surface of the silicon substrate 1 when the collector electrode 21 (see FIG. 2) is formed, the wraparound electrode 16 is formed. Wraparound electrode 16
Can be surely found. That is, when the wraparound electrode 16 is formed, a leak current 17 is generated between the guard ring electrode 4 and the base electrode 2, and the current ICBO between the collector and the base, which is a characteristic of the transistor, is increased. Bad is found.

Although the semiconductor chip 701 having the conventional structure (see FIGS. 15 and 16) could be found when there was a large amount of wrapped electrode material, it was difficult to find when the area of the electrode material was small. Sometimes it was judged.

Seventh Embodiment Next, a semiconductor wafer according to a seventh embodiment of the present invention will be described with reference to FIG. In addition, the above-mentioned Examples 1 to 6
The members having the same names as those described above are denoted by the same reference numerals.

As shown in FIG. 14, the semiconductor wafer 8 according to the seventh embodiment of the present invention is different from the semiconductor chip 101 according to the first embodiment (see FIGS. 1 and 2) in the vicinity of the outer periphery of the semiconductor wafer 8. (A portion shown by oblique lines in FIG. 14 is a place where the semiconductor chip 101 is arranged). On the other hand, near the center of the semiconductor wafer 8 is a semiconductor chip 701 (see FIGS. 15 and 16) having a conventional structure.

As a result, the semiconductor chips 1 formed near the outer periphery of the semiconductor wafer 8 where electrode formation defects are likely to occur
For example, the probe test is performed for the semiconductor chip 701 formed near the center, and the probe test can be omitted. As a result, a wafer test can be performed efficiently, and a semiconductor chip can be formed near the outer periphery of a semiconductor wafer on which no semiconductor chip has been formed in order to prevent a defective product from being shipped in the past. Become.

[0059]

According to the present invention, a probing pad portion for a probe test is provided on a ring-shaped guard ring electrode surrounding a semiconductor chip, so that a probe test is performed by applying a probe needle to the probing pad. It is possible to provide a planar semiconductor chip having a structure in which a defective formation of an electrode provided on a surface can be reliably detected.

[Brief description of the drawings]

FIG. 1 is a plan view showing a planar semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of the semiconductor chip shown in FIG. 1;

FIG. 3 is an explanatory diagram showing a state where a probe test is performed on the semiconductor chip shown in FIG. 1;

FIG. 4 is a plan view showing a planar type semiconductor chip according to a second embodiment of the present invention.

FIG. 5 is a plan view showing a planar type semiconductor chip according to Embodiment 3 of the present invention.

FIG. 6 is an explanatory diagram showing a state in which a probe test is performed on the semiconductor chip shown in FIG. 5;

FIG. 7 is a plan view showing a planar semiconductor chip according to Embodiment 4 of the present invention.

FIG. 8 is a plan view showing a planar type semiconductor chip according to Embodiment 5 of the present invention.

FIG. 9 is a cross-sectional view of the semiconductor chip shown in FIG. 8, taken along the line BB, showing a case where the electrode has a normal thickness.

10 is a cross-sectional view of the semiconductor chip shown in FIG. 8, taken along line BB, showing a case where the electrode is formed to be thin.

11 is a cross-sectional view of the semiconductor chip shown in FIG. 8, taken along line CC, showing a state where a probe test is being performed;

FIG. 12 is a plan view showing a planar type semiconductor chip according to Embodiment 6 of the present invention.

FIG. 13 is an explanatory view showing a state in which the electrode material on the back surface has wrapped around the front surface side of the semiconductor chip shown in FIG. 12;

FIG. 14 is a plan view showing a semiconductor wafer according to a seventh embodiment of the present invention.

FIG. 15 is a plan view showing a conventional planar type semiconductor chip.

16 is a cross-sectional view of the semiconductor chip shown in FIG. 15 taken along the line DD.

FIG. 17 is a plan view showing a conventional semiconductor wafer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Base electrode 3 ... Emitter electrode 4 ... Guard ring electrode 5 ... Probing pad part 101 ... Semiconductor chip

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Claims (12)

[Claims] 1. A planar device comprising: a semiconductor chip formed on a silicon substrate; and a ring-shaped guard ring electrode provided on the surface of the silicon substrate and surrounding the semiconductor chip, wherein the guard ring electrode is provided with a probing pad for a probe test. Type semiconductor chip. 2. The semiconductor device according to claim 1, wherein the semiconductor chip is a power transistor, and the power transistor includes a collector layer provided on a back surface of the substrate, a base diffusion layer and an emitter diffusion layer provided on a front surface of the substrate, and a back surface of the substrate. 2. The planar semiconductor chip according to claim 1, further comprising: a collector electrode provided on the silicon substrate; and a base electrode and an emitter electrode provided on a surface of the silicon substrate. 3. The planar semiconductor chip according to claim 1, wherein the guard ring electrode is quadrangular, and the probing pad portions are provided at four corners or two opposing corners of the guard ring electrode. 4. The planar semiconductor chip according to claim 1, wherein the guard ring electrode has a quadrangular shape, one corner of which is separated, and a probing pad portion provided at two ends formed thereby. 5. The planar semiconductor chip according to claim 1, wherein the probing pad portion is substantially square, and one side thereof is wider than the width of the guard ring electrode. 6. The planar semiconductor chip according to claim 2, wherein the guard ring electrode is provided between the substrate and the substrate via an insulating film, and a contact portion is provided only at a predetermined position of the guard ring electrode to contact the substrate. 7. A guard ring electrode having a quadrangular shape, probing pad portions provided at four corners of the guard ring electrode, and a contact portion provided substantially at an intermediate point between two adjacent probing pad portions. 4. The planar semiconductor chip according to 1. 8. The planar semiconductor chip according to claim 6, wherein the contact portion is rectangular, and one short side thereof is wider than the width of the guard ring electrode. 9. The planar semiconductor chip according to claim 2, wherein the guard ring electrode is adjacent to the base electrode, and the guard ring electrode and the base electrode have an interval that does not affect the withstand voltage of the semiconductor chip. 10. A method for performing a probe test on a planar semiconductor chip according to claim 1, wherein a probe needle is applied to each of two probing pads of a guard ring electrode to measure a resistance value. And a test method for a planar semiconductor chip for estimating an electrode formation defect of the semiconductor chip based on the measurement result. 11. A method for performing a probe test on a planar type semiconductor chip according to claim 6, wherein a probe is applied to a contact portion of a guard ring electrode and a collector electrode on a back surface of the substrate. A method for testing a planar semiconductor chip, comprising measuring a resistance value and estimating a defective electrode formation of the semiconductor chip based on the measurement result. 12. A semiconductor wafer on which a plurality of semiconductor chips are formed, wherein each chip formed around the semiconductor wafer is the planar semiconductor chip according to claim 1.