JPWO2016046872A1 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

The first conductivity type semiconductor substrate (7) is provided with a surface (SF) having four corners (CN). The surface (SF) has a main part (PM) and a peripheral part (PP) surrounding the main part (PM). The peripheral part (PP) has an outer peripheral part (PPo) and a terminal part (PPt) surrounding the outer peripheral part (PPo). The terminal end (PPt) has four corners (PC) located at each of the corners (CN). The main impurity region (2) is provided in the main portion (PM), has the second conductivity type, and has one area. The plurality of sub-impurity regions (1) are separated from each other, provided at least two of the corner portions (PCs) away from the main impurity region (2), have a second conductivity type, and Having a total area smaller than one area. The main electrode (6) is in contact with the main impurity region (2) on the surface (SF) and is separated from the sub impurity region (1). The peripheral electrode (41) is in contact with each sub-impurity region (1).

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a main impurity region that functions under a large current during actual use of the device, and a function when performing measurement for estimating a large current characteristic of the device with a small current. The present invention relates to a power semiconductor device having a sub-impurity region and a manufacturing method thereof.

  It may be necessary to grasp the large current characteristics of the power semiconductor device for the purpose of selecting the device. For example, for a large capacity free-wheeling diode, it is important to grasp the voltage drop characteristics when a large current is applied in the forward direction. However, measurement with a large current is difficult for a semiconductor device in a chip state (that is, a semiconductor chip) before being incorporated into a package. For this reason, a monitor part having the same kind of function and having a smaller size may be provided in the semiconductor chip independently of the main part that functions as an element during actual use for measurement purposes. Thereby, the characteristic in the large current region applied at the time of actual use can be measured with a relatively small current. Therefore, it is possible to grasp the large current characteristics during actual use before the semiconductor chip is assembled.

  In order to suppress an increase in chip area due to the provision of the monitor portion, it is preferable to dispose the monitor portion in a portion of the semiconductor chip that is not effectively utilized. Therefore, it is preferable to dispose the monitor portion at the corner of the chip, which is an ineffective region that does not have a function as a diode element in actual use and does not have a special function for maintaining a withstand voltage.

  For example, according to Japanese Patent Laid-Open No. 2002-359377 (Patent Document 1), at least one second anode region is provided in the freewheeling diode so as to be electrically separated from the first anode region. Since an electrode independent of the anode electrode on the first anode region is formed on the upper surface of the second anode region, measurement at a current density equivalent to or close to the rated current can be performed with a relatively low current. As a result, it is possible to accurately grasp the performance of the large current capacity chip in the actual use current region, and it is possible to cope with feedback to the wafer manufacturing process and chip selection at the time of parallel connection.

JP 2002-359377 A

  In mass production of semiconductor devices, a plurality of semiconductor chips are usually formed on a wafer. Depending on the position of the chip in the wafer surface, the monitor portion may be located near the outer edge of the wafer. In this case, the influence on the monitor portion from the outside of the wafer is increased. For example, the forward voltage of the monitor portion may increase due to the influence of diffusion boat contamination. This increases the difference in characteristics between the monitor portion and the main portion. Thereby, the precision at the time of estimating the characteristic of a main part by the measurement using a monitor part becomes low. As a result, even when there is no problem in the characteristics during actual use of the device, the semiconductor device may be determined to be defective from the measurement result of the monitor portion. In addition, when a plurality of semiconductor devices are connected and incorporated in parallel, it is often required to align their characteristics. However, if the characteristics are not accurately grasped, an imbalance between the devices tends to occur. . As a result, the yield of the final product may be reduced, and usage conditions (such as current, voltage, and operating ambient temperature) may be limited.

  The present invention has been made to solve the above-described problems, and its purpose is to accurately grasp a large current characteristic in actual use in a chip state while suppressing an increase in chip area. A semiconductor device and a manufacturing method thereof are provided.

  The semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a main impurity region, a sub-impurity region, a main electrode, an interlayer insulating film, and a peripheral electrode. The semiconductor substrate is provided with a surface having four corners. The surface has a main part and a peripheral part surrounding the main part. The peripheral part has an outer peripheral part and a terminal part surrounding the outer peripheral part. The end portion has four corners located at each of the corners. The main impurity region is provided in the main part, has a second conductivity type different from the first conductivity type, and has one area on the surface. The plurality of sub-impurity regions are separated from each other, are provided apart from the main impurity region in each of at least two corners, have a second conductivity type, and have a total area smaller than one area on the surface. Has an area. The main electrode is in contact with the main impurity region on the surface and is separated from the sub impurity region. The interlayer insulating film covers a portion between the sub impurity regions on the peripheral portion. The peripheral electrode is provided apart from the main electrode on the peripheral portion where the interlayer insulating film is provided, and is in contact with each of the sub impurity regions.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a wafer and a step of cutting out each of a plurality of chip regions from the wafer. The wafer has an outer edge. The wafer is provided with a plurality of chip areas including the first chip area. Each of the chip regions includes a first conductivity type semiconductor substrate, a main impurity region, a sub-impurity region, a main electrode, an interlayer insulating film, and a peripheral electrode. The semiconductor substrate is provided with a surface having four corners. The surface has a main part and a peripheral part surrounding the main part. The peripheral part has an outer peripheral part and a terminal part surrounding the outer peripheral part. The end portion has four corners located at each of the corners. The main impurity region is provided in the main part, has a second conductivity type different from the first conductivity type, and has one area on the surface. The plurality of sub-impurity regions are separated from each other, and are provided apart from the main impurity region in each of at least two of the four corners, have the second conductivity type, and have a surface area larger than one area. Has a small total area. The main electrode is in contact with the main impurity region on the surface and is separated from the sub impurity region. The interlayer insulating film covers a portion between the sub impurity regions on the peripheral portion. The peripheral electrode is provided apart from the main electrode on the peripheral portion where the interlayer insulating film is provided, and is in contact with each of the sub impurity regions. Each of the sub-impurity regions of the first chip region is provided in at least two of the four corners of the first chip region other than those closest to the outer edge of the wafer.

  According to the semiconductor device of the present invention, the characteristics obtained by the measurement using the peripheral electrode are obtained by averaging the characteristics of the elements by the sub-impurity regions arranged at each of the plurality of corner portions. As a result, the characteristics obtained by the measurement are closer to the characteristics of the actual element due to the main impurity region. Therefore, by arranging the sub-impurity regions at the corners, it is possible to accurately grasp the large current characteristics in actual use while suppressing an increase in the chip area.

  According to the method for manufacturing a semiconductor device of the present invention, the characteristics of the elements due to the sub-impurity regions arranged at each of the plurality of corners are averaged, so that the large current characteristics during actual use can be accurately obtained in the chip state. I can grasp it. Further, according to the present invention, the sub-impurity region of the first chip region is provided other than the one closest to the outer edge of the wafer among the four corners of the first chip region. That is, as the position of the sub-impurity region, a position that is most susceptible to characteristic fluctuations caused by being close to the outer edge can be avoided. Thereby, it is possible to more accurately grasp the large current characteristics during actual use of the semiconductor device obtained by cutting out the first chip region.

1 is a plan view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a schematic sectional drawing in alignment with line II-II of FIG. It is a schematic sectional drawing in alignment with line III-III of FIG. FIG. 2 is a plan view schematically showing sections on the surface of a semiconductor substrate included in the semiconductor device of FIG. 1. FIG. 5 is a schematic partial sectional view taken along line VV in FIG. 4. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing in alignment with line VII-VII of FIG. It is a schematic sectional drawing in alignment with line VIII-VIII of FIG. FIG. 8 is a cross-sectional view schematically showing a configuration of a semiconductor device in a third embodiment of the present invention in the same field of view as FIG. 7. FIG. 9 is a cross sectional view schematically showing a configuration of a semiconductor device in a third embodiment of the present invention in the same field of view as FIG. FIG. 8 is a cross-sectional view schematically showing a configuration of a semiconductor device in a fourth embodiment of the present invention in the same field of view as FIG. 7. FIG. 9 is a cross sectional view schematically showing a configuration of a semiconductor device in a fourth embodiment of the present invention in the same field of view as FIG. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 5 of this invention. It is a schematic sectional drawing which follows the line XIV-XIV of FIG. It is a schematic sectional drawing in alignment with line | wire XV-XV of FIG. It is a flowchart which shows schematically the structure of the manufacturing method of the semiconductor device in Embodiment 5 of this invention. FIG. 17 is a partial plan view schematically showing a configuration of a semiconductor portion of the wafer in FIG. 16. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 6 of this invention. It is a fragmentary top view which shows schematically the structure of the semiconductor part of the wafer formed in the manufacturing method of the semiconductor device in Embodiment 6 of this invention. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 7 of this invention. It is a fragmentary top view which shows schematically the structure of the semiconductor part of the wafer formed in the manufacturing method of the semiconductor device in Embodiment 7 of this invention. It is a fragmentary top view which shows schematically the structure of the semiconductor part of the wafer formed in the manufacturing method of the semiconductor device in Embodiment 8 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
1 to 3, a diode 101 (semiconductor device) of the present embodiment includes an n-type (first conductivity type) semiconductor substrate 7, a main anode region 2 (main impurity region), and a sub-electrode. An anode region 1 (sub-impurity region), a main anode electrode 6 (main electrode), an interlayer insulating film 21, a peripheral electrode 41, a cathode region 8 (back surface impurity region), and a cathode electrode 9 (back surface electrode). Have.

  Further, referring to FIG. 4, the semiconductor substrate 7 is provided with a surface SF having four corners CN. The surface SF has a rectangular shape. Here, a rectangle is defined as a quadrangle having only right-angled corners, and thus a square is a kind of rectangle.

  The surface SF has a main part PM and a peripheral part PP surrounding the main part PM. The main part PM is a part where the main anode region 2 is provided in the surface SF. The peripheral part PP has an outer peripheral part PPo and a terminal part PPt surrounding the outer peripheral part PPo. The outer peripheral portion PPo is a portion for ensuring the withstand voltage characteristics of the diode 101. In order to ensure the withstand voltage characteristic, as shown in FIG. 5, a p-type (second conductivity type different from the first conductivity type) field limiting ring 30 (shown in FIGS. 1 to 3) is provided at the outer peripheral portion PPo. May be provided. The terminal end PPt has four corners PC (FIG. 4) located at each of the corners CN.

  The main anode region 2 and the sub anode region 1 have p-type. As shown in FIG. 1, the sub-anode regions 1 are separated from each other. The secondary anode region 1 is separated from the main anode region 2. The sub-anode region 1 is provided in each of at least two corner portions PC (FIG. 4). In the present embodiment, the sub-anode region 1 is provided in each of the four corner portions PC.

  The main anode region 2 has one area on the surface SF. This one area corresponds to an effective area when the diode 101 is actually used. The sub-anode region 1 has a total area smaller than this area on the surface SF.

  The main anode electrode 6 is in contact with the main anode region 2 on the surface SF and is separated from the sub anode region 1. The main anode electrode 6 is made of, for example, Al, an Al—Si alloy, or an Al—Si—Cu alloy. The interlayer insulating film 21 covers the portion between the sub-anode regions 1 on the peripheral portion PP (FIG. 4) as shown in FIG.

  The peripheral electrode 41 is provided on the peripheral portion PP where the interlayer insulating film 21 is provided. The interlayer insulating film 21 insulates the peripheral electrode 41 from the n-type portion of the peripheral portion PP. The peripheral electrode 41 is separated from the main anode electrode 6. The peripheral electrode 41 is in contact with each of the sub-anode regions 1 so that the four sub-anode regions 1 have the same potential.

  The cathode region 8 has n-type and has a higher impurity concentration than the impurity concentration of the semiconductor substrate 7. The cathode electrode 9 is provided on the cathode region 8 (on the back surface in FIGS. 2 and 3).

  According to the present embodiment, the characteristics obtained by the measurement using the peripheral electrode 41 are obtained by averaging the characteristics of the elements by the sub-anode regions 1 arranged in the corner portions PC. Thereby, the characteristic obtained by the measurement is closer to the characteristic of the actual element by the main anode region 2. Therefore, by arranging the sub-anode region 1 in the corner PC, it is possible to accurately grasp the large current characteristics in actual use while suppressing an increase in the chip area. At that time, no special wafer process or measurement method is required.

  In particular, when a semiconductor device is manufactured from a chip area close to the outer edge of the wafer, the element characteristics due to the sub-anode region 1 arranged in the four corner portions PC of the chip area that are particularly close to the outer edge of the wafer are the actual element characteristics. It is easy to make a big difference. According to the present embodiment, the influence of such a difference is suppressed by averaging the characteristics of the elements by the sub-anode regions 1 arranged at each of the plurality of corner portions PC.

  The sub-anode region 1 is provided at each of the four corners PC of the surface SF (FIG. 4) having a rectangular shape. By averaging the characteristics of the measuring element by these four corners PC, the characteristics of the element by the main anode region 2 located at the center of the rectangle can be grasped more accurately.

  In this embodiment, the peripheral electrode 41 has a closed shape along the four sides of the surface SF (FIG. 4) as shown in FIG. 1, but the wiring resistance between the sub-anode regions 1 is sufficiently low. For example, a substantially U-shaped shape along three sides may be used.

(Embodiment 2)
With reference to FIGS. 6 to 8, diode 102 (semiconductor device) of the present embodiment has a main front metal layer 11 (main metal layer) provided on main anode electrode 6.

  The diode 102 has a peripheral electrode 42 instead of the peripheral electrode 41 (FIGS. 1 to 3). Peripheral electrode 42 has sub-electrodes 5 provided at each corner PC (FIG. 4) of surface SF, and sub-front metal layer 10 (sub-metal layer) that electrically connects sub-electrodes 5 to each other.

  The main front metal layer 11 and the sub front metal layer 10 are made of a common material having higher solder wettability than the material of the main anode electrode 6. Therefore, the film formation for forming the main front metal layer 11 and the sub front metal layer 10 can be performed collectively. Further, the patterning for forming the main front metal layer 11 and the sub front metal layer 10 can be performed at once using a photoengraving process or a metal mask. As the material, a laminated material can be used. For example, Al / Ti / Ni / Au, Al / Mo / Ni / Au, Ti / Ni / Au, or Mo / Ni / Au is used.

  Interlayer insulating film 22 includes insulating film 17 and nitride film 12. The insulating film 17 insulates the sub-electrode 5 and the n-type portion of the semiconductor substrate 7 from each other at the corner PC (FIG. 4). The nitride film 12 insulates the sub-front metal layer 10 from the n-type portion of the peripheral portion PP (FIG. 4). In particular, the nitride film 12 insulates the sub front metal layer 10 and the outer peripheral portion PPo from each other. Thereby, the peripheral electrode 42 and the pressure | voltage resistant holding structure which has the field limiting ring 30 (FIG. 5) are electrically insulated from each other.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment, the description thereof will not be repeated.

  According to the present embodiment, the sub-front metal layer 10 included in the peripheral electrode 42 is provided on the outer peripheral portion PPo via the nitride film 12 of the interlayer insulating film 22. Therefore, a region on the outer peripheral portion PPo is used for connection between the sub-anode regions 1. Thereby, the chip area of the diode 102 can be further suppressed.

  Further, by providing the main front metal layer 11 on the main anode electrode 6, electrical connection to the main anode electrode 6 can be easily performed using solder. The sub-front metal layer 10 is made of a material suitable for connection using solder, but is not normally intended for connection by solder.

  Further, since the nitride film 12 is used as an insulating film between the sub-front metal layer 10 and the outer peripheral portion PPo, electrical insulation is more reliably ensured.

(Embodiment 3)
Referring to FIGS. 9 and 10, diode 103 (semiconductor device) of the present embodiment has interlayer insulating film 23 instead of interlayer insulating film 22 (FIGS. 7 and 8). Interlayer insulating film 23 includes polyimide film 13 instead of nitride film 12 (FIGS. 7 and 8). Since the configuration other than the above is substantially the same as the configuration of the second embodiment described above, description thereof will not be repeated.

  According to the present embodiment, the same effect as in the second embodiment can be obtained. In addition, since the polyimide film 13 is used as an insulating film between the sub-front metal layer 10 and the outer peripheral portion PPo, electrical insulation is more reliably ensured, and the semiconductor device of the present embodiment is sealed with a mold resin. When stopped and used, the stress caused by the mold resin can be relaxed.

(Embodiment 4)
Referring to FIGS. 11 and 12, diode 104 (semiconductor device) of the present embodiment has interlayer insulating film 24 instead of interlayer insulating film 22 (FIGS. 7 and 8). Interlayer insulating film 24 includes nitride film 12 and polyimide film 13 provided thereon. Since the configuration other than the above is substantially the same as the configuration of the second embodiment described above, description thereof will not be repeated.

  According to the present embodiment, the same effect as in the second embodiment can be obtained. In addition, since a laminate of the nitride film 12 and the polyimide film 13 is used as an insulating film between the sub-front metal layer 10 and the outer peripheral portion PPo, electrical insulation is more reliably ensured, and the present embodiment When the semiconductor device is used after being sealed with a mold resin, stress due to the mold resin can be relaxed.

(Embodiment 5)
Referring to FIGS. 13 to 15, in diode 105 (semiconductor device) of the present embodiment, each of secondary anode regions 1 is provided at three of four corner portions PC (FIG. 4). . The other one corner PC is not provided with the sub-anode region 1. Since the configuration other than the above is substantially the same as the configuration of diode 101 (Embodiment 1), description thereof will not be repeated.

  Next, a manufacturing method of the diode 105 will be described below with reference to the flowchart of FIG.

  Referring to FIG. 17, first, in step S10, a wafer 301 is formed. The wafer 301 has an outer edge EG. In the present embodiment, outer edge EG has a circular shape. A plurality of chip areas 200 including a chip area 205 (first chip area) are provided on the wafer 301.

  Note that FIG. 17 shows only the semiconductor portion to make the drawing easier to see, but the main anode electrode 6, the interlayer insulating film 21, and the peripheral electrode 41 are provided on the wafer 301. A cathode electrode 9 is provided on the back surface of the wafer 301 (the opposite surface in FIG. 17).

  Next, in step S20, each of the chip areas 200 is cut out from the wafer 301 by dicing. As a result, the diode 105 is obtained from the chip region 205.

  In each of the chip regions 200 of the wafer 301 formed in step S10, the sub-anode region 1 is provided apart from the main anode region 2 in each of at least two corner portions PC. In particular, in the chip region 205, each of the sub-anode regions 1 is provided at three corners PC other than the one closest to the outer edge EG of the wafer 301 among the four corners PC of the chip region 205.

  According to the present embodiment, the characteristics obtained by the measurement using the peripheral electrode 41 are the same as the characteristics of the first embodiment, and the characteristics of the elements by the sub-anode regions 1 arranged in each of the plurality of corner portions PC are averaged. Will be. Thereby, the large current characteristic at the time of actual use can be grasped more accurately in the chip state. Further, according to the present embodiment, the sub-anode region 1 of the chip region 205 is provided other than the one closest to the outer edge EG of the wafer 301 among the four corners PC of the chip region 205. That is, as the position of the sub-anode region 1, a position that is most susceptible to characteristic fluctuations caused by being close to the outer edge EG is avoided. As a result, the large current characteristic during actual use of the diode 105 obtained by cutting out the chip region 205 can be grasped more accurately.

(Embodiment 6)
Referring to FIG. 18, in diode 106 (semiconductor device) of the present embodiment, each of two sub-anode regions 1 is one of four corners PC on surface SF (FIG. 4). It is provided only at the two corners PC facing diagonally. Since the configuration other than the above is substantially the same as the configuration of diode 101 (Embodiment 1), description thereof will not be repeated.

  Next, a method for manufacturing the diode 106 will be described below.

  Referring to FIG. 19, first, in step S10 (FIG. 16), a wafer 302 is formed. The wafer 302 is provided with a plurality of chip areas 200 including a chip area 206 (first chip area). In the chip region 206, the sub-anode region 1 is provided only at two corners opposed to one diagonal line on the surface SF among the four corner portions PC (FIG. 4).

  Next, in step S20 (FIG. 16), each of the chip regions 200 is cut out from the wafer 302 by dicing. As a result, the diode 106 is obtained from the chip region 206.

  According to the present embodiment, the same effect as in the fifth embodiment can be obtained. Further, according to the present embodiment, the average position of the sub-anode region 1 can be brought closer to the center of the main anode region 1 than in the fifth embodiment.

(Embodiment 7)
Referring to FIG. 20, in diode 107 (semiconductor device) of the present embodiment, each of two sub-anode regions 1 has a rectangular shape among four corners PC on surface SF (FIG. 4). It is provided only at two corners PC facing each other along one side. Since the configuration other than the above is substantially the same as the configuration of diode 101 (Embodiment 1), description thereof will not be repeated.

  Next, a method for manufacturing the diode 107 will be described below.

  Referring to FIG. 21, first, in step S10 (FIG. 16), a wafer 303 is formed. The wafer 303 is provided with a plurality of chip areas 200 including the chip area 206 and the chip area 207 (second chip area) described above. In the chip region 207, the sub-anode region 1 is provided at two corners of the four corner portions PC other than the two corner portions closest to the outer edge EG of the wafer 303. Each of the two corner PCs of the chip region 207 where the sub-anode region 1 is not provided has a similar distance to the outer edge EG as indicated by an arrow WE in the drawing.

  Next, in step S20 (FIG. 16), each of the chip regions 200 is cut out from the wafer 303 by dicing. As a result, the diode 106 (FIG. 18) and the diode 107 (FIG. 20) are obtained from the chip regions 206 and 207, respectively.

  According to the present embodiment, in the case where there are two corner portions PC close to the outer edge EG, the sub-anode region 1 can be arranged avoiding both of them. Thereby, even in such a case, the large current characteristic at the time of actual use of the diode 107 can be grasped more accurately in a chip state.

(Embodiment 8)
Referring to FIG. 22, in the method for manufacturing a diode as a semiconductor device of the present embodiment, first, wafer 304 is formed in step S10 (FIG. 16). The wafer 304 is provided with a plurality of chip areas 200 including chip areas 201, 205 and 207. The number of sub-anode regions 1 included in each of the chip regions 201, 205, and 207 is four, three, and two. Therefore, in the present embodiment, there are a plurality of types of sub-anode regions 1 that each of the chip regions 200 has.

  Whether or not the sub-anode region 1 is provided in a specific corner PC can be determined by the relationship between the corner PC and the boundary line CL that is a predetermined distance away from the outer edge EG of the wafer 304. Specifically, if the corner portion PC is within the region surrounded by the boundary line CL, the sub-anode region 1 is provided, and if it is outside this region, the sub-anode region 1 is not provided. In FIG. 22, the boundary line CL is defined as the outer edge EG having a simple circular shape by ignoring the orientation flat OF of the wafer 304. However, the boundary line CL is defined as an orientation flat OF or notch (FIG. (Not shown) may be determined. Alternatively, a boundary line separated from the center of the wafer 304 by a certain distance may be used.

  The total area of the plurality of sub-anode regions 1 included in each chip region 200 is equal to each other. Specifically, the total area of the four sub-anode regions 1 included in the chip region 201, the total area of the three sub-anode regions 1 included in the chip region 205, and the total of the two sub-anode regions 1 included in the chip region 207. The area is equal to each other. Here, “the total areas are equal to each other” means that they are substantially equal to the extent that there is no problem in the measurement accuracy of the characteristics. For example, each total area is within the range of the reference value ± 10%. means.

  In each chip region 200, the individual areas of the plurality of sub-anode regions 1 are preferably equal to each other. In this case, if the area of one sub-anode region 1 included in the chip region 201 is 1, the area of one sub-anode region 1 included in the chip region 205 is 4/3, and one sub-anode included in the chip region 207 The area of the region 1 is 2.

  According to the present embodiment, the number of sub-anode regions 1 provided in the chip region 200 can be changed according to the position of each chip region 200 in the plane of the wafer 304. Thereby, the arrangement of the sub-anode region 1 can be made more suitable for each chip region 200. As a result, the large current characteristic during actual use of the diode can be grasped more accurately in the chip state.

  In the fifth to eighth embodiments, instead of the interlayer insulating film 21 and the peripheral electrode 41 (see the first embodiment), any one of the interlayer insulating films 22 to 24 (see the second to fourth embodiments) and the peripheral electrode are used. 42 may be used.

  In the first to eighth embodiments, the n-type and p-type as the first and second conductivity types may be interchanged. Correspondingly, the anode and cathode are switched.

  Within the scope of the present invention, the present invention can be freely combined with embodiments, appropriately modified, or omitted. Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

  EG outer edge, CL boundary line, PC corner, OF orientation flat, SF surface, PM main part, PP peripheral part, PPo outer peripheral part, PPt termination part, 1 sub anode area (sub impurity area), 7 semiconductor substrate, 2 main Anode region (main impurity region), 5 sub electrode, 6 main anode electrode (main electrode), 8 cathode region (back surface impurity region), 9 cathode electrode (back surface electrode), 10 sub front metal layer, 11 main front metal layer, 12 nitride film, 13 polyimide film, 17 insulating film, 21-24 interlayer insulating film, 30 field limiting ring, 41, 42 peripheral electrode, 101-107 diode (semiconductor device), 200, 201, 205-207 chip region, 301-304 Wafer.

Claims (12)

Semiconductor devices (101 to 107),
A first conductivity type semiconductor substrate (7) provided with a surface (SF) having four corners (CN) is provided, the surface comprising a main part (PM) and a peripheral part (PP) surrounding the main part. The peripheral portion has an outer peripheral portion (PPo) and a terminal portion (PPt) surrounding the outer peripheral portion, and the terminal portion has four corner portions (PC) located at each of the corners. The semiconductor device is further provided in the main part, has a second conductivity type different from the first conductivity type, and has a main impurity region (2) having an area on the surface;
At least two of the corner portions are provided apart from the main impurity region, have the second conductivity type, have a total area smaller than the one area on the surface, and are separated from each other A sub-impurity region (1);
A main electrode (6) in contact with the main impurity region on the surface and away from the sub impurity region;
An interlayer insulating film (21 to 24) covering a portion between the sub impurity regions on the peripheral portion;
A semiconductor device comprising: peripheral electrodes (41, 42) provided apart from the main electrode on the peripheral portion provided with the interlayer insulating film and in contact with each of the sub impurity regions.   The semiconductor device (101 to 104) according to claim 1, wherein the surface has a rectangular shape, and the sub-impurity region is provided in each of the four corners. A field limiting ring (30) of the second conductivity type provided on the outer periphery, and a main metal layer (11) provided on the main electrode;
The peripheral electrode (42) includes a plurality of sub-electrodes (5) provided at each of the corners of the surface, and a sub-metal layer (10) that electrically connects the sub-electrodes to each other.
The main metal layer and the sub metal layer are made of a common material having higher solder wettability than the material of the main electrode,
The semiconductor device (102 to 104) according to claim 1 or 2, wherein the interlayer insulating film (22 to 24) insulates the outer peripheral portion and the sub metal layer from each other.   The semiconductor device (102, 104) according to claim 3, wherein the interlayer insulating film (22, 24) includes a nitride film (12).   The semiconductor device (103, 104) according to claim 3 or 4, wherein the interlayer insulating film (23, 24) includes a polyimide film (13). Forming a wafer (301-304) having an outer edge (EG) and provided with a plurality of chip regions (200) including first chip regions (205-207);
Cutting each of the plurality of chip regions from the wafer,
Each of the plurality of chip regions is
A first conductivity type semiconductor substrate (7) provided with a surface (SF) having four corners, the surface having a main part (PM) and a peripheral part (PP) surrounding the main part; The peripheral part has an outer peripheral part (PPo) and a terminal part (PPt) surrounding the outer peripheral part, and the terminal part has four corner parts (PC) positioned at each of the corners. Each of the chip regions is further provided in the main part, has a second conductivity type different from the first conductivity type, and has a main impurity region (2) having an area on the surface,
At least two of the four corners are provided apart from the main impurity region, have the second conductivity type, and have a total area smaller than the one area on the surface, separated from each other A plurality of sub-impurity regions (1);
A main electrode (6) in contact with the main impurity region on the surface and away from the sub impurity region;
An interlayer insulating film (21) covering a portion between the sub impurity regions on the peripheral portion;
A peripheral electrode (41, 42) provided apart from the main electrode on the peripheral portion provided with the interlayer insulating film and in contact with each of the sub-impurity regions;
Each of the sub-impurity regions of the first chip region is provided in at least two of the four corners of the first chip region other than the one closest to the outer edge of the wafer.
Manufacturing method of semiconductor device (105-107).   The sub-impurity region of the first chip region (206) is provided only at two corners opposed to one diagonal line on the surface among the four corner portions. The manufacturing method of the semiconductor device of description.   The plurality of chip regions include a second chip region (207), and the sub-impurity region of the second chip region includes two corners closest to the outer edge of the wafer among the four corners. The method for manufacturing a semiconductor device according to claim 6, wherein the method is provided at two corners other than the above.   9. The device according to claim 6, wherein each of the plurality of chip regions has a plurality of types of sub-impurity regions, and the total area of the sub-impurity regions of each of the plurality of chip regions is equal to each other. A method for manufacturing the semiconductor device according to the item. Each of the plurality of chip regions has a field limiting ring (30) of the second conductivity type provided on the outer peripheral portion, and a main metal layer (11) provided on the main electrode. ,
The peripheral electrode (42) includes a plurality of sub-electrodes (5) provided at each of the corners of the surface, and a sub-metal layer (10) that electrically connects the sub-electrodes to each other.
The main metal layer and the sub metal layer are made of a common material having higher solder wettability than the material of the main electrode,
The method for manufacturing a semiconductor device according to claim 6, wherein the interlayer insulating film insulates the outer peripheral portion and the sub metal layer from each other.   The method of manufacturing a semiconductor device according to claim 10, wherein the interlayer insulating film includes a nitride film (12).   The method of manufacturing a semiconductor device according to claim 10, wherein the interlayer insulating film includes a polyimide film (13).

Images