TWI662683B - Transistor series device - Google Patents

Abstract

The present invention provides a series arrangement of transistors, comprising: a carrier plate and an electrode lead set of a lead frame, and the first carrier and the second carrier are included in the carrier plate, and the electrode lead set includes the first pin a second pin, a third pin and a fourth pin, the first pin is electrically connected to the first carrier; the chip unit comprises a first chip and a second chip which can be a tripolar transistor chip And the first electrode of the first chip and the second chip are respectively connected to the first carrier and the second carrier, and the second electrodes of the first and second transistors are electrically connected to the second pin respectively And a third lead, the third electrode of the first chip is electrically connected to the first electrode of the second carrier or the second chip, and the third electrode of the second chip is electrically connected to the fourth pin, The reverse withstand voltage is increased by connecting two tripolar transistors in series, and achieves the effects of automated production, high yield, low cost, and improved product consistency and reliability.

Description

Transistor series device

The invention provides a series arrangement of transistors, in particular, a first wafer and a second wafer provided with a wafer unit on a lead frame, and is produced by automatic solid crystal and solid line, and has two transistors in series. Increase the reverse withstand voltage to achieve high yield, low cost, and improve product consistency and reliability.

According to the current design, packaging and testing of power semiconductor devices, single devices and packaged devices used in parallel are mature and common, but serial applications are limited by devices that lack practical, automated production, low cost, and high reliability. The solution is therefore not common in series devices and the actual related applications, while the parallel operation is the current addition, and the series operation is the voltage withstand, but under the same power condition, the working voltage can effectively reduce the working current, and then Achieve energy efficiency and meet the trend of high power density, because at the same power, after increasing the voltage value, the current value can be reduced (because the power is equal to the product of voltage and current, ie P=V*I), thereby reducing the terminal The product uses current specifications for semiconductor components and increases the power density of the end product, as well as lowering costs (because smaller currents indicate smaller semiconductor components, lower cost, and smaller size).

Generally, various types of tripolar transistors have three electrodes, such as a collector (Corector, C), a gate (Gate, G), and an emitter ( Emitter, E), or drain (Drain, D), gate (Gate, G) and source (Source, S), because the traditional three-polar transistor lacks the technology of the series device, the existing old technology Among them, there are only power modules that are relatively bulky, cannot be automated, and have extremely low power density. Because it is difficult to use fully automatic processing methods, the processing process is cumbersome, and the product consistency and reliability are also poor. The industry is eager to study the key to improvement.

Therefore, in view of the above-mentioned problems and shortcomings of the above-mentioned applications, the inventors have collected and evaluated relevant data through various parties, and have used the trial and modification of many years of R&D experience in this industry to start the invention of such a series device of transistors. The patent was born.

The main purpose of the present invention is to provide a series arrangement of transistors, comprising: a carrier plate and an electrode lead set of the lead frame, and the first carrier plate and the second carrier plate are included in the crystal plate, and the electrode lead group comprises electricity. Is electrically connected to the first pin on the first carrier board, the second pin, the third pin and the fourth pin which are separately disposed; the chip unit includes the first chip and the second chip, and is composed of the first chip and the first chip The first electrodes of the two chips are respectively connected to the first carrier and the second carrier, and the second electrodes of the first and second wafers are electrically connected to the second pin and the third pin, respectively. When the wafer and the second wafer are respectively insulated gate bipolar transistor wafers of a tripolar transistor, the third electrode of the first wafer is electrically connected to the second carrier; and the first wafer and the second wafer are respectively metal oxide The third electrode of the first wafer is electrically connected to the first electrode of the second wafer, and the third electrode of the second wafer is electrically connected to the fourth pin. The reverse withstand voltage is increased by connecting two tripolar transistors in series, and further To automated production, good rate, low cost and can improve the effectiveness of product consistency and reliability.

The secondary object of the present invention is that the wafer unit can control the gate voltage or the gate of the two transistors simultaneously by using the second electrode of the first wafer and the second wafer, thereby multiplying the withstand voltage value of the working voltage for application. In a higher working voltage power supply circuit, since the power supply circuit increases the voltage value under the same power, the current value can be reduced. The integrated design of the two series of three-polar transistors can reduce the use of semiconductor elements in the terminal product. The current specifications of the device increase the power density and are smaller, which is more effective in reducing costs.

Another object of the present invention is to further include a third wafer and a fourth wafer which are respectively a freewheeling diode chip, and have first electrodes on the back sides of the third wafer and the fourth wafer, respectively, and the front side is respectively Having a second electrode, and the first electrode of the third wafer and the first electrode of the fourth wafer are respectively connected to the first carrier and the second carrier, and the second electrode of the third transistor is electrically connected to the first via the lead a second carrier, the second electrode of the fourth chip is electrically connected to the fourth pin of the electrode lead group through a wire, and the first chip and the second chip used to control the inductive load are turned on by the power supply circuit At the time of the cutoff, the third wafer and the fourth wafer of the freewheeling diode can be simultaneously connected in parallel with the first wafer and the second wafer, and the back electromotive force or the surge voltage can be consumed or released as a current to smooth the current. To prevent the occurrence of surge voltages and to protect the safety of tripolar transistors or other circuit components.

A further object of the present invention is that the electrode lead set of the lead frame further includes a fifth pin electrically connected to the second carrier, and is used as a test pole for serially dividing the two tripolar transistors. The first pin and the second pin are matched with the fifth pin as the first group of test pins, and the third pin, the fourth pin and the fifth pin are used as the second group of test pins, so that the test chips can be individually tested. The reliability of the product is excellent in the resistance and electrical characteristics of the first and second wafers in series, as well as the actual voltage distribution during operation.

Another object of the present invention is that when the automated device is used for solid-crystal and fixed-line production, the first wafer and the second wafer of the wafer unit packaged in the same module are taken from one wafer adjacent to each other. The two wafers have the closest resistance and electrical characteristics and the highest consistency, and have the highest reliability for the series-integrated withstand voltage characteristics, and can connect multiple module-packaged devices on the same connecting piece through the material. The structure is not scattered, and the automatic production can be facilitated. After the plastic sealing of the outer layer of the insulating protection is completed, the individual parts are cut by the cutting die, so that it can be widely applied to the automatic production of various types of tripolar transistors, thereby improving production. Efficiency and yield and cost are cheaper.

1‧‧‧ lead frame

10‧‧‧Materials

101‧‧‧Connecting piece

11‧‧‧A crystal plate

111‧‧‧First carrier

112‧‧‧Second carrier

113‧‧‧ Missing slots

12‧‧‧Electrode lead set

121‧‧‧First pin

122‧‧‧second pin

123‧‧‧ third pin

124‧‧‧fourth pin

125‧‧‧ fifth pin

2‧‧‧ wafer unit

21‧‧‧First chip

211‧‧‧First electrode

212‧‧‧second electrode

213‧‧‧ third electrode

214‧‧‧ lead

22‧‧‧second chip

221‧‧‧First electrode

222‧‧‧second electrode

223‧‧‧ third electrode

224‧‧‧ lead

23‧‧‧ Third chip

231‧‧‧First electrode

232‧‧‧second electrode

233‧‧‧ lead

24‧‧‧ fourth chip

241‧‧‧First electrode

242‧‧‧second electrode

243‧‧‧ lead

3‧‧‧Insulation protection outer layer

31‧‧‧Lock hole

A‧‧‧Anode

C‧‧‧ Collector

D‧‧‧Drain

E‧‧‧ emitter

G1‧‧‧Gate

G2‧‧‧Gate

G3‧‧‧ gate

G4‧‧‧ gate

K‧‧‧ cathode

S‧‧‧ source

The first figure is a schematic structural view of a preferred embodiment of the present invention.

The second figure is an equivalent circuit diagram of two insulated gate bipolar transistors in series according to the present invention.

The third figure is a schematic view of the arrangement of lead frames in accordance with a preferred embodiment of the present invention.

The fourth figure is a schematic diagram of the automatic production of the lead frame and the transistor of the present invention after plastic sealing.

Figure 5 is a schematic view showing the structure of another preferred embodiment of the present invention.

The sixth figure is an equivalent circuit diagram of a series of two insulated gate bipolar transistors simultaneously connected in parallel with the freewheeling diode.

Figure 7 is a schematic view showing the structure of still another preferred embodiment of the present invention.

The eighth figure is an equivalent circuit diagram of the two metal oxide semiconductor field effect transistors in series according to the present invention.

Figure 9 is a schematic view showing the structure of still another preferred embodiment of the present invention.

The tenth figure is an equivalent circuit diagram of the two parallel metal-oxide-semiconductor field-effect transistors in parallel with the parallel-connected diode.

In order to achieve the above objects and effects, the technical means and constructions of the present invention will be described in detail with reference to the preferred embodiments of the present invention.

Please refer to the first, second, third and fourth figures, which are respectively a schematic structural view of a preferred embodiment of the present invention, an equivalent circuit diagram of two insulated gate bipolar transistors in series, and a schematic diagram of a lead frame arrangement of a preferred embodiment. And the schematic diagram of the automatic production after the lead frame and the transistor are connected for plastic sealing. As is clear from the figure, the series device of the transistor of the present invention comprises a lead frame 1, a wafer unit 2 and an insulating protective outer layer 3, wherein: the lead The frame 1 is made of a conductor material and includes a crystal plate 11 and an electrode lead group 12 for arranging the wafer unit 2 thereon. The crystal plate 11 includes the first carrier 111 and is isolated from the first carrier 111. The second carrier 112, the electrode lead set 12 includes a first pin 121 directly extending or electrically connected to the first carrier 111, a second pin 122 disposed separately, a third pin 123, and a fourth lead The pin 124 and the fifth pin 125 directly extending or electrically connected to the second carrier 112. It should be noted that the fifth pin 125 is a test pin, if it is known that the test pin is not required. Under, can also be changed according to actual needs or applications The design, for example, originally designed a five-pin structure to cut off the fifth pin 125 into a four-pin structure, and the position of each pin can also be optimized according to the overall structure of the material 10 connection. In order to facilitate the subsequent automatic solid crystal and solid line production, so in the following description of the contents are all together, combined with Chen Ming.

The wafer unit 2 includes a first wafer 21 and a second wafer 22 which are respectively insulated gate bipolar transistor (IGBT) wafers, and includes collector electrodes as transistors on the back surfaces of the first wafer 21 and the second wafer 22, respectively. a first electrode 211, 221 of C, and a front surface of the first wafer 21 and the second wafer 22 respectively include second electrodes 212, 222 as gates G1, G2 of the transistor, and an emitter E of the transistor The first electrode 21 and the second wafer 22 are disposed on the crystal plate 11 and are connected to the first carrier 111 and the second carrier 112 through the same first electrodes 211 and 221, respectively. The second electrodes 212 and 222 are electrically connected to the second pin 122 and the third pin 123 of the electrode lead group 12 through the leads 214 and 224 respectively, and the two third electrodes 213 of the first wafer 21 pass through. The leads 214 are electrically connected to the second carrier 112, and the second electrodes 223 of the second wafer 22 are electrically connected to the fourth pins 124 of the electrode lead group 12 through the leads 224, respectively.

In this embodiment, the second electrodes 213 of the first wafer 21 are electrically connected to the first electrodes 221 of the second wafer 22 through the leads 214 and the second carrier 112 of the crystal substrate 11. The fifth pin 125 extending from the second carrier 112 can serve as the test pole T of the transistor, and the first pin 121 and the second pin 122 of the electrode lead group 12 are matched with the fifth pin 125 as the first group. Test pins, third pin 123, fourth pin 124 and fifth pin 125 as test pins of the second group, respectively, can test each of the first wafer 21 and the second wafer 22 in series The resistance and electrical characteristics, as well as the actual voltage distribution during operation, make the product extremely reliable.

The insulating protective outer layer 3 is integrally formed on the carrier plate 11 of the lead frame 1 by epoxy resin or other plastic and covers the wafer unit 2, which can be understood, in other embodiments. The lead frame 1 in the embodiment may also have an exposed heat sink without being covered by the insulating protective outer layer 3, so that the first wafer 21 and the second wafer 22 can be better dissipated, and the back of the crystal plate 11 can also be used. Or, a part of the structure excluding the electrode lead group 12 is not covered by the insulating protective outer layer 3, so that it can directly contact the outside air for heat dissipation.

As shown in the third and fourth figures, the material member 10 in the present embodiment is formed by processing a plurality of crystal plates 11 of the lead frame 1 and electrode lead groups 12 thereof, and is disposed at the electrode lead group 12 The connecting piece 101 having the lateral connection, when the present invention is produced by Die Bonding and Wire Bonding using an automated device, the device packaged in the same module is on the first wafer 21 of the wafer unit 2 The second wafer 22 is taken in series from two adjacent wafers on a wafer, and its resistance and electrical characteristics are the closest and the highest consistency, and for the characteristic application using series cumulative withstand voltage, the reliability is The device can be connected to the same connecting piece 101 through the material member 10, so that the overall structure is not scattered, and the automatic production can be facilitated, so that each group of the first carrier board 111 and the second carrier The pitch between the plates 112 remains the same. After the plastic sealing of the insulating protective outer layer 3 is completed, the cutting die is used to cut and form individual individuals, thereby achieving the effect of improving production efficiency and yield and cost.

However, the front projection area of the first carrier 111 and the second carrier 112 of the crystal carrying plate 11 are nearly identical, and the heat dissipation performance of the first carrier 111 to the first wafer 21 and the second carrier 112 may be second. The heat dissipation performance of the wafer 22 tends to be uniform to avoid the temperature difference between the first wafer 21 and the second wafer 22 during operation, resulting in differences in electrical characteristics due to temperature differences, and in each group of first carrier plates 111 and second. The carrier plate 112 has a curved notch 113 on the inner side of the inner side, and the surface of the insulating protective outer layer 3 is provided with a through hole 1 The locking hole 31 of the 13 is used for fixing the fasteners (such as screws) through the locking holes 31 to fix the series device of the transistors to other objects (such as a heat sink or a circuit board, etc.).

In this embodiment, the first wafer 21 and the second wafer 22 of the wafer unit 2 are connected in series to each other, and the second electrode 212 of the first wafer 21 and the second electrode 222 of the second wafer 22 are electrically connected to the electrodes, respectively. The second pin 122 and the third pin 123 of the pin group 12 are separately provided to control the gates G1 and G2 of the two insulated gate bipolar transistors to simultaneously switch, thereby multiplying the withstand voltage of the working voltage, for example, An insulated gate bipolar transistor with a withstand voltage of 1700V is used for the two first wafers 21 and the second wafer 22, and the withstand voltage can reach 3400V after being connected in series, thereby breaking the existing single package insulated gate bipolar electricity. The limit of the withstand voltage value of the crystal chip is applied to the power supply circuit with higher working voltage. Since the power supply circuit can increase the voltage value under the same power, the current value can be reduced. Therefore, the present invention has two insulated gate bipolar in series. The integrated design of the transistor can reduce the current specification of the semiconductor component used in the terminal product and increase the power density of the terminal product, and the semiconductor component used is smaller because of the smaller current, so it is more effective. low cost.

Please refer to the fifth and sixth figures, which are respectively a schematic structural view of another preferred embodiment of the present invention and an equivalent circuit diagram of two parallel insulated bipolar transistors simultaneously connected in parallel with the freewheeling diode. It can be clearly seen that the wafer unit 2 in this embodiment further includes a third wafer 23 and a fourth wafer 24, respectively, which are freewheeling diodes, and the freewheeling diode (or The flywheel diode is generally a fast recovery diode or a Schottky diode or the like, and has a first electrode 231 as a cathode K of the diode on the back surface of the third wafer 23 and the fourth wafer 24, respectively. , 241, and the front side respectively has the second electrodes 232, 242 of the anode A as a diode, and the third wafer 23 and the fourth The wafer 24 is connected to the first carrier 111 and the second carrier 112 through the same first electrodes 231 and 241, respectively, and the second electrode 232 of the third wafer 23 can be electrically connected to the second carrier through the lead 233. The board 112 is electrically connected to the first electrode 211 of the second wafer 22 through the second carrier 112, and the second electrode 242 of the fourth wafer 24 is electrically connected to the fourth lead of the electrode lead group 12 through the lead 243. The leg 124 has two parallel-connected insulated gate bipolar transistor two-terminal electrodes connected in parallel with a freewheeling diode.

When the applied power circuit is used to control the first wafer 21 and the second wafer 22 of the inductive load (such as a relay or an inductor, etc.) to be turned off by conduction, the back electromotive force generated at the two ends of the inductive load or the protrusion The wave voltage can be as high as 1000V or more, and it is easy to break through a tripolar transistor (such as an insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor) or other circuit components, so that the first wafer 21 and the first The second wafer 22 is simultaneously connected with the third wafer 23 and the fourth wafer 24 of the freewheeling diode, and consumes or releases the back electromotive force or the surge voltage in the form of current to smooth the current, thereby preventing the occurrence of the surge voltage. It also protects the safety of tripolar transistors or other circuit components.

Please refer to the seventh, eighth, ninth and tenth drawings, which are respectively a schematic structural view of another preferred embodiment of the present invention, an equivalent circuit diagram of two metal oxide semiconductor field effect transistors in series, and another preferred embodiment. The schematic diagram of the structure of the embodiment and the equivalent circuit diagram of the two parallel metal-oxide-semiconductor field-effect transistors simultaneously connected in parallel with the free-wheeling diode, as is clear from the figure, the present invention also provides a series arrangement of transistors, including The lead frame 1, the wafer unit 2, and the insulating protective outer layer 3 described in any of the above embodiments are different from the wafer unit 2 of the first embodiment in that the first wafer 21 and the second wafer 22 in this embodiment are A metal oxide semiconductor field effect transistor (MOSFET) wafer, respectively, and on the first wafer 21 and the second wafer 22 The front side respectively includes a first electrode 211, 221 as a drain D of the transistor, a second electrode 212, 222 of the gate G3, G4 of the transistor, and a third electrode 213, 223 of the source S of the transistor, and The back surface of the first wafer 21 and the second wafer 22 are disposed on the crystal plate 11 but are not connected, and the first electrode 211 of the first wafer 21 is electrically connected to the first carrier 111 through the wire 214, and is The second electrode 212 and the third electrode 213 are electrically connected to the second pin 122 of the electrode lead group 12 and the first electrode 221 of the second wafer 22 through the lead 214, respectively, and the first electrode 221 of the second wafer 22 is The second lead 123 and the fourth lead 124 are electrically connected to the second pin 123 and the fourth lead 124 of the electrode lead group 12 through the lead 224 respectively. .

In this embodiment, since the third electrode 213 of the first wafer 21 is electrically connected to the first carrier 221 of the second wafer 22 and the second carrier 112 of the crystal carrier 11 through the lead 214, The fifth pin 125 extending from the second carrier 112 can serve as the test electrode T of the transistor, and the first pin 121, the second pin 122 and the fifth pin 125 of the electrode lead group 12 are used as the first The test pins of the group, the third pin 123, the fourth pin 124 and the fifth pin 125 serve as test pins of the second group, and each of the first wafer 21 and the second wafer 22 connected in series can be individually tested. The resistance and electrical characteristics, as well as the actual voltage distribution during operation, make the product extremely reliable.

In this embodiment, the first wafer 21 and the second wafer 22 of the wafer unit 2 are connected in series to each other, and the second electrode 212 of the first wafer 21 and the second electrode 222 of the second wafer 22 are electrically connected to the electrodes, respectively. The second pin 122 and the third pin 123 are separately provided in the pin group 12 to control the gate G on the two metal oxide semiconductor field effect transistors 3, G4 switch at the same time, can multiply the withstand voltage value of the working voltage, break the limit of the withstand voltage value of the existing metal oxide semiconductor field effect transistor, and apply it to the power circuit with higher working voltage, but In practical applications, the first wafer 21 and the second wafer 22 may also be two bipolar junction transistors (BJT), junction field effect transistors (JEFT) or other series connected in series. The tripolar transistor can reduce the current value by increasing the voltage value at the same power of the power supply circuit. Therefore, the integrated structure design of the two tripolar transistors in series according to the present invention can reduce the current of the semiconductor component used in the terminal product. Specifications, and increase the power density of the end product, and the volume is smaller, which can effectively reduce the cost.

As shown in the ninth and tenth embodiments, the wafer unit 2 in the embodiment further includes the third wafer 23 and the fourth wafer 24, which are respectively the freewheeling diode chips described in any of the foregoing embodiments, and the continuation The current diode (or the flywheel diode) generally uses a fast recovery diode or a Schottky diode or the like, and has a diode as a diode on the back side of the third wafer 23 and the fourth wafer 24, respectively. a first electrode 231, 241 of the cathode K, and a second electrode 232, 242 of the anode A as a diode, respectively, on the front side, and the third wafer 23 and the fourth wafer 24 pass through the same first electrode 231, 241 is respectively connected to the first carrier 111 and the second carrier 112, and the second electrode 232 of the third wafer 23 can be electrically connected to the second carrier 112 through the lead 233 and passed through the second carrier 112. The first electrode 211 of the second wafer 22 is electrically connected, and the second electrode 242 of the fourth wafer 24 is electrically connected to the fourth pin 124 of the electrode lead group 12 through the lead 243 to make two metal oxides connected in series. The two-terminal electrodes of the semiconductor field effect transistor are simultaneously connected in parallel with a freewheeling diode.

When the applied power circuit controls the first wafer 21 and the second wafer 22 of the inductive load to be turned off by conduction, the back electromotive force generated by the two ends of the inductive load or the protrusion The third wafer 23 and the fourth wafer 24 of the freewheeling diode are respectively connected in parallel with the first wafer 21 and the second wafer 22, and are consumed or released in the form of current by the freewheeling diode. The electromotive force or the surge voltage acts to smooth the current, thereby effectively preventing the occurrence of a surge voltage and protecting the safety of the tripolar transistor or other circuit components.

Therefore, the present invention is mainly directed to the lead frame 1 including the crystal plate 11 and the electrode lead group 12, and the wafer unit 2 is disposed on the crystal plate 11 to make the first wafer 21 and the second wafer 22 first. The electrodes 211 and 221 are respectively connected to the first carrier 111 and the second carrier 112, and the electrode lead group 12 includes the first pin 121 electrically connected to the first carrier 111, and the first wafer 21 is The second electrodes 212 and 222 of the second wafer 22 are electrically connected to the second pin 122 and the third pin 123 of the electrode lead group 12, respectively, and the third electrode 213 of the first wafer 21 is electrically connected to the first electrode The first electrode 221 of the second carrier 112 or the second wafer 22, and the third electrode 223 of the second wafer 22 are electrically connected to the fourth pin 124 of the electrode lead group 12, and two tripolars can be connected in series. The integrated structure of the transistor is designed to increase the reverse withstand voltage, thereby achieving automated production, high yield, low cost and improved product consistency and reliability.

The detailed description of the present invention is intended to be a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and other equivalents and modifications may be made without departing from the spirit of the invention. Changes are intended to be included in the scope of the patents covered by the present invention.

In summary, the above-mentioned series arrangement of the transistor of the present invention can achieve its efficacy and purpose when used. Therefore, the invention is an invention with excellent practicability, and is in fact conforming to the application requirements of the invention patent, and submitting an application according to law. I hope that the trial committee will grant this case as soon as possible to protect the inventor. The hard work of inventing, if there is any doubt in the bureau, please do not hesitate to give instructions, the inventor will try his best to cooperate, and feel really good.

Claims (15)

A serial device for a transistor, comprising: a lead frame comprising a carrier plate and a set of electrode pins of a conductor material, and the carrier plate comprises a first carrier plate and a second carrier plate isolated from the first carrier plate, and the electrode The pin group includes a first pin, a separately disposed second pin, a third pin, and a fourth pin, the first pin is electrically connected to the first carrier; the chip unit includes the first chip and the first a second wafer, and a first electrode as a collector of the transistor, respectively, on the back side of the first wafer and the second wafer, and a front surface of the first wafer and the second wafer respectively comprising a second electrode as a gate of the transistor And a third electrode of the emitter of the transistor, and the first wafer and the second wafer are disposed on the crystal plate and are respectively connected to the first carrier and the second carrier through the first electrode, and the wafer unit The first wafer and the second wafer are insulated gate bipolar transistor wafers, and the second electrode of the first wafer and the second electrode of the second wafer are electrically connected to the second pin of the electrode lead group through leads respectively The third pin, the first chip contains two The electrode is electrically connected to the second carrier through the lead, the second electrode included in the second wafer is electrically connected to the fourth lead through the lead; and the insulating protective outer layer is disposed on the lead frame and covered The wafer unit and the electrode lead set are exposed to the insulating protective outer layer. The serial device of the transistor according to claim 1, wherein the electrode lead set further comprises a fifth pin extending directly or electrically connected to the second carrier, and is used as a test pole of the transistor. The first pin and the second pin are matched with the fifth pin as the first chip test pin of the first group, and the third pin and the fourth pin are matched with the fifth pin as the second group. The second wafer test pin. The tandem device of the transistor of claim 1, wherein the wafer unit further comprises a third wafer and a fourth wafer which are respectively a freewheeling diode wafer, and are applied to the third wafer and the fourth wafer. The back side has a first electrode as a cathode of the diode, and the front side has a second electrode as an anode of the diode, respectively, and the first electrode of the third wafer and the first electrode of the fourth wafer are respectively first and The carrier plate and the second carrier are connected, the second electrode of the third chip is electrically connected to the second carrier through the lead, and the second electrode of the fourth wafer is electrically connected to the fourth electrode set by the lead a pin for the third wafer and the fourth wafer to be connected in parallel to the first wafer and the second wafer, respectively. The tandem device of the transistor of claim 3, wherein the third wafer and the fourth wafer of the wafer unit are fast recovery diodes or Schottky diodes as freewheeling diodes. The tandem device of the transistor of claim 1, wherein the first carrier of the lead frame and the second carrier have a nearly equal projected area. The tandem device of the transistor according to claim 1, wherein the electrode lead group of the lead frame is a connecting piece having a lateral connection of the material member for connecting the plurality of lead frames on the connecting piece, and After automatic solid crystal and solid line production, and the outer layer of insulation protection is molded, it is cut into individual individuals by cutting die. The tandem device of the transistor of claim 6, wherein the first wafer and the second wafer of the wafer unit are taken from two adjacent wafers on one wafer. A serial device for a transistor, comprising: a lead frame comprising a carrier plate and a set of electrode pins of a conductor material, and comprising a first layer on the carrier plate a carrier board and a second carrier board separated from the first carrier board, and the electrode lead set includes a first pin, a separately disposed second pin, a third pin, and a fourth pin, the first pin system Electrically connected to the first carrier; the wafer unit includes a first wafer and a second wafer, and includes a first electrode as a drain of the transistor and a gate of the transistor on the front surface of the first wafer and the second wafer, respectively The second electrode and the third electrode of the source of the transistor, and the back surface of the first wafer and the second wafer are respectively disposed on the first carrier and the second carrier of the crystal plate, and the first of the first wafer The electrode is electrically connected to the first carrier, and is electrically connected to the second electrode and the first electrode of the second chip by the second electrode and the third electrode of the first chip, respectively, and the first electrode of the second chip Electrically connected to the second carrier, and electrically connected to the third pin and the fourth pin by the second electrode and the third electrode of the second chip respectively; and the insulating protective outer layer is disposed on the lead frame and The wafer unit is covered and the electrode lead set is exposed to the insulating protective outer layer. The tandem device of the transistor of claim 8, wherein the first wafer and the second wafer of the wafer unit are metal oxide semiconductor field effect transistor wafers, and the first electrode and the second electrode of the first wafer The first electrode of the chip is electrically connected to the first carrier and the second carrier of the crystal plate through the lead wires, and is electrically connected to the electrode by the second electrode and the third electrode of the first wafer through the lead respectively. The second pin of the pin group and the first electrode of the second chip, and the second electrode and the third electrode of the second chip are electrically connected to the third pin and the fourth pin respectively through the lead. The serial device of the transistor according to claim 9, wherein the electrode lead set further comprises a fifth pin extending directly or electrically connected to the second carrier, and is used as an electric The test pole of the crystal, and the first pin and the second pin are matched with the fifth pin as the first chip test pin of the first group, and the third pin and the fourth pin are matched with the fifth pin system. The second set of second wafer test pins. The tandem device of the transistor of claim 8, wherein the wafer unit further comprises a third wafer and a fourth wafer which are respectively a freewheeling diode wafer, and are on the third wafer and the fourth wafer. The back side has a first electrode as a cathode of the diode, and the front side has a second electrode as an anode of the diode, respectively, and the first electrode of the third wafer and the first electrode of the fourth wafer are respectively first and The carrier plate and the second carrier are connected, the second electrode of the third chip is electrically connected to the second carrier through the lead, and the second electrode of the fourth wafer is electrically connected to the fourth electrode set by the lead a pin for the third wafer and the fourth wafer to be connected in parallel to the first wafer and the second wafer, respectively. The tandem device of the transistor according to claim 11, wherein the third wafer and the fourth wafer of the wafer unit are fast recovery diodes or Schottky diodes as freewheeling diodes. The tandem device of the transistor of claim 8, wherein the first carrier of the lead frame and the second carrier have a nearly orthogonal projected area. The serial device of the transistor according to claim 8, wherein the electrode lead group of the lead frame is a connecting piece having a lateral connection of the material member for connecting the plurality of lead frames on the connecting piece, and After automatic solid crystal and solid line production, and the outer layer of insulation protection is molded, it is cut into individual individuals by cutting die. The tandem device of the transistor of claim 14, wherein the first wafer and the second wafer of the wafer unit are taken from two adjacent wafers on one wafer.