CN210837732U - Packaging structure of gallium nitride HEMT - Google Patents
Packaging structure of gallium nitride HEMT Download PDFInfo
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- CN210837732U CN210837732U CN201921898945.4U CN201921898945U CN210837732U CN 210837732 U CN210837732 U CN 210837732U CN 201921898945 U CN201921898945 U CN 201921898945U CN 210837732 U CN210837732 U CN 210837732U
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The utility model discloses a packaging structure of gallium nitride HEMT, treat that the grid of encapsulation gallium nitride HEMT chip is located between source electrode and the drain electrode, set up second electrically conductive pad, third electrically conductive pad and base plate pin district are located the chip and are close to one side of source electrode, first electrically conductive pad is located the chip and is close to the opposite side of drain electrode, connect drain electrode and first electrically conductive pad through first electric connecting part electricity, connect source electrode and base plate pin district through second electric connecting part electricity, connect source electrode and second electrically conductive pad through fourth electric connecting part electricity, connect grid and third electrically conductive pad through third electric connecting part electricity, can make and satisfy withstand voltage distance between each electrode of chip; electrically connecting the source electrode and the second conductive bonding pad through a fourth electric connection component to form a Kelvin source electrode so as to reduce the parasitic inductance of the driving loop; the to-be-packaged gallium nitride HEMT chip is fixed and electrically connected to the heat dissipation area, so that the heat dissipation performance of the packaging structure is improved.
Description
Technical Field
The utility model relates to a semiconductor chip packaging technology field, more specifically says, relates to a packaging structure of gallium nitride HEMT (high electron mobility transistor).
Background
As a typical representative of the third generation semiconductor material, the wide bandgap semiconductor gallium nitride (GaN) has excellent properties that many silicon materials do not have, is an excellent semiconductor material for high-frequency, high-voltage and high-power applications, and has wide application prospects in the civil and military fields.
Although the wide bandgap semiconductor material gallium nitride has great advantages in performance compared with silicon materials, the conventional power device packaging technology is designed based on the conventional silicon material power device, and when the conventional packaging technology is used for packaging a semiconductor device prepared from the wide bandgap semiconductor material gallium nitride, the performance of the semiconductor device is affected.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a gallium nitride HEMT's packaging structure has improved gallium nitride HEMT packaging structure's performance.
In order to achieve the above object, the present invention provides the following technical solutions:
a package structure of a gallium nitride HEMT, the package structure comprising:
the front surface of the gallium nitride HEMT chip to be packaged is provided with a grid electrode, a source electrode and a drain electrode; the grid electrode is positioned between the source electrode and the drain electrode;
the conductive base plate is provided with a heat dissipation area and a base plate pin area which are used for fixing the to-be-packaged gallium nitride HEMT chip;
the lead frame is provided with a first conductive bonding pad, a second conductive bonding pad and a third conductive bonding pad; the conductive base plate and the lead frame are relatively fixed;
the first conductive bonding pad is positioned on one side, provided with the drain, of the to-be-packaged gallium nitride HEMT chip, and the second conductive bonding pad and the third conductive bonding pad are positioned on one side, provided with the source, of the to-be-packaged gallium nitride HEMT chip; the back surface of the to-be-packaged gallium nitride HEMT chip is fixed and electrically connected with the heat dissipation area; the drain electrode is electrically connected with the first conductive bonding pad through a first electrical connecting part, the source electrode is electrically connected with the base plate pin area through a second electrical connecting part, the grid electrode is electrically connected with the third conductive bonding pad through a third electrical connecting part, and the source electrode is also electrically connected with the second conductive bonding pad through a fourth electrical connecting part.
Preferably, in the above package structure, the substrate pin area, the first conductive pad, the second conductive pad, and the third conductive pad each include a land and a pin integral with the land;
the connecting parts of the welding area and the pin of the first conductive welding disc, the second conductive welding disc and the third conductive welding disc are provided with bending parts, so that the welding area is higher than the pin.
Preferably, in the above package structure, the first conductive pad is electrically connected to the drain electrode through at least one of the first electrical connection members;
the first conductive pad includes: a drain bond pad and at least one drain lead integral with the drain bond pad;
wherein the drain pad is electrically connected to the drain through the first electrical connection member.
Preferably, in the above package structure, the pad lead region is electrically connected to the source electrode through at least one of the second electrical connection members, and the second conductive pad is electrically connected to the source electrode through one of the fourth electrical connection members;
the submount pin area includes: a source bonding pad and at least one source lead integral with the source bonding pad; wherein the source bonding pad is electrically connected to the source electrode through the second electrically connecting member;
the second conductive pad includes: a Kelvin source pad and a Kelvin source; wherein the Kelvin source pad is electrically connected to the source through the fourth electrical connection member.
Preferably, in the above package structure, the third conductive pad is electrically connected to the gate electrode through one third electrical connection member.
Preferably, in the above package structure, the third conductive pad includes: a gate pad and a gate lead;
wherein the gate pad is electrically connected to the gate through the third electrical connection member.
Preferably, in the above package structure, the back surface of the to-be-packaged gallium nitride HEMT chip is fixed to the heat dissipation region by soft solder.
Preferably, in the above package structure, the package further includes: and the packaging layer is used for sealing and protecting the gallium nitride HEMT chip to be packaged, and covers the gallium nitride HEMT chip to be packaged and each electrical connecting component.
Preferably, in the above encapsulation structure, the encapsulation layer is an epoxy resin layer.
As can be seen from the above description, in the packaging structure and the packaging method of the gallium nitride HEMT according to the present invention, the gallium nitride HEMT chip to be packaged is packaged using the lateral structure, and the gate thereof is located between the source and the drain, so that the second conductive pad, the third conductive pad, and the pad lead region can be located on the same side of the gallium nitride HEMT chip to be packaged and close to the source, the first conductive pad is located on the other side of the gallium nitride HEMT chip to be packaged and close to the drain, the drain and the first conductive pad are electrically connected by the first electrical connection member, the source and the pad lead region are electrically connected by the second electrical connection member, the source and the second conductive pad are electrically connected by the fourth electrical connection member, the gate and the third conductive pad are electrically connected by the third electrical connection member, the drain and the source are fully considered, and the current between the drain and the gate is large, and the current between the source electrode and the grid electrode is small, so that the voltage-resistant distance between the electrodes of the gallium nitride HEMT chip to be packaged is met, and the electrical performance index of the packaging structure is further met. And the source electrode and the second conductive bonding pad are electrically connected through the fourth electric connection part to form a Kelvin source electrode (Kelvin source), so that the parasitic inductance of the driving loop can be reduced, the loss caused by the parasitic inductance can be further reduced, and the electric performance index of the packaging structure is further improved. Meanwhile, the conductive base plate comprises a heat dissipation area and a base plate pin area, the to-be-packaged gallium nitride HEMT chip is fixed and electrically connected in the heat dissipation area, the base plate pin area is electrically connected with the source electrode through the semiconductor substrate of the chip on the back of the chip, the conductive base plate has the functions of a heat dissipation sheet and a base island, and the heat dissipation performance of the packaging structure is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a diagram of a typical PDFN (Power Dual Flat No-lead) package structure;
FIG. 2 is a top view of the package structure shown in FIG. 1 after being molded;
fig. 3 is a schematic view of a package structure of a gallium nitride HEMT according to an embodiment of the present invention;
FIG. 4 is a top view of the package structure shown in FIG. 3 after being molded;
fig. 5 is a schematic view of another packaging structure of a gallium nitride HEMT according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
At present, the conventional Power device packaging technology is designed based on a conventional silicon Power device, as shown in fig. 1 and fig. 2, fig. 1 is a schematic diagram of a typical PDFN (Power Dual Flat No-lead) packaging structure, fig. 2 is a top view of the packaging structure shown in fig. 1 after plastic packaging, a left view in fig. 1 is a front top view of the packaging structure before plastic packaging, a right view is a side view before plastic packaging, a left view in fig. 2 is a front top view after plastic packaging, and a right view is a back top view after plastic packaging.
The packaging structure comprises: a frame substrate having a lead frame 120 and a conductive substrate 121; the chip 130 to be packaged is fixed on the conductive base 121. The chip 130 to be packaged is a vertical structure device, and has a source 131 and a gate 132 on the front surface and a drain on the back surface. The frame substrate has a first conductive pad 122 and a second conductive pad 123 on the same side of the chip 130 to be packaged, the source electrode 131 is electrically connected to a bonding pad of the second conductive pad 123 through a corresponding electrical connection member 150 and is further electrically connected to a corresponding pin, and the gate electrode 132 is electrically connected to a bonding pad of the first conductive pad 122 through a corresponding electrical connection member 150 and is further electrically connected to a corresponding pin. The chip 130 to be packaged is fixed by soldering with soft solder 140 and the conductive base 121, so that the drain is electrically connected to the bonding area of the conductive base 121 to be electrically connected to the corresponding pin on the other side of the chip to be packaged. After each pole of the chip 130 to be packaged is electrically connected to the corresponding pin, the chip 130 to be packaged and the electrical connection component 150 are sealed and protected by the plastic package layer 160.
If the packaging mode shown in fig. 1 is adopted, the substrate and the conductive base plate 121 are welded and fixed, the source electrode is electrically connected with the conductive base plate 121 through the substrate and further electrically connected with a welding area, the drain electrode and the gate electrode are respectively and electrically connected with different welding areas on the other side of the conductive base plate of the lead frame, and due to the fact that large current exists between the drain electrode and the gate electrode, the mode cannot guarantee the withstand voltage distance between the drain electrode and the gate electrode. If the withstand voltage distance between the drain electrode and the gate electrode is ensured, the substrate needs to be insulated and then welded and fixed with the conductive base plate 121, so that the drain electrode is electrically connected with a welding area of the conductive base plate of the lead frame, and the source electrode and the gate electrode are electrically connected with different welding areas on one side of the conductive base plate of the lead frame respectively.
In view of this, the embodiment of the present invention provides a package structure and a package method of a gallium nitride HEMT, which improve the performance of the package structure of the gallium nitride HEMT.
In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 3 and fig. 4, fig. 3 is a schematic diagram of a package structure of a gallium nitride HEMT according to an embodiment of the present invention, fig. 4 is a top view of the package structure shown in fig. 3 after plastic package, a left view of fig. 3 is a front top view of the package structure before plastic package, a right view of the package structure before plastic package, a left view of fig. 4 is a front top view of the package structure after plastic package, and a right view of the package structure after plastic package.
The package structure includes: a to-be-packaged gallium nitride HEMT chip 70, the front side of the to-be-packaged gallium nitride HEMT chip 70 having a Gate (Gate)72, a Source (Source)73 and a Drain (Drain) 71; the gate 72 is located between the source 73 and the drain 71; a conductive base plate 92 having a heat dissipation region for fixing the to-be-packaged gallium nitride HEMT chip 70 and a base plate lead region 93; a lead frame 90, wherein a first conductive pad 91, a second conductive pad 94 and a third conductive pad 95 are arranged on the lead frame 90; the conductive base 92 is fixed relative to the lead frame 90 and is insulated therefrom. The first conductive pad 91, the second conductive pad 94, and the third conductive pad 95 are insulated from each other.
Wherein the first conductive pad 91 is located on the side of the to-be-packaged gallium nitride HEMT chip 70 having the drain 71, and the second conductive pad 94 and the third conductive pad 95 are located on the side of the to-be-packaged gallium nitride HEMT chip 70 having the source 73; the back surface of the to-be-packaged gallium nitride HEMT chip 70 is fixed and electrically connected with the heat dissipation area; the drain 71 is electrically connected to the first conductive pad 91 through a first electrical connection member 81, the source 73 is electrically connected to the pad lead region 93 through a second electrical connection member 82, the gate 72 is electrically connected to the third conductive pad 95 through a third electrical connection member 83, and the source 73 is also electrically connected to the second conductive pad 95 through a fourth electrical connection member 84.
Optionally, the back surface of the to-be-packaged gallium nitride HEMT chip is fixed to the heat dissipation region by soldering with soft solder 60. Wherein the soft solder 60 consists of the following components in percentage by mass: 95.5% of lead, 2% of tin and 2.5% of silver, so as to ensure better heat dissipation performance. The specific composition and mass percentage of the soft solder 60 are not limited to those described in the embodiments of the present invention, and may be set according to the requirement.
In the package structure according to the embodiment of the present invention, the second conductive pad 94, the third conductive pad 95 and the base pad lead region 93 are disposed on the same side of the gan HEMT chip 70 to be packaged and are close to the source electrode 73, the first conductive pad 91 is disposed on the other side of the gan HEMT chip 70 to be packaged and is close to the drain electrode 91, the drain electrode 71 and the first conductive pad 91 are electrically connected through the first electrical connection member 81, the source electrode 73 and the base pad lead region 93 are electrically connected through the second electrical connection member 82, the source electrode 73 and the second conductive pad 94 are electrically connected through the fourth electrical connection member 84, the gate electrode 72 and the third conductive pad 95 are electrically connected through the third electrical connection member 83, the current between the drain electrode 71 and the source electrode 73 is considered sufficiently, the current between the drain electrode 71 and the gate electrode 72 is large, and the current between the source electrode 73 and the gate electrode 72 is small, so that the voltage withstanding distance between the electrodes of, the electrical performance index of the packaging structure is met. And the source electrode 73 and the second conductive bonding pad 94 are electrically connected through the fourth electrical connection part 84 to form a kelvin source electrode, so that the parasitic inductance of a driving loop can be reduced, and the electrical performance index of the packaging structure can be further improved. Meanwhile, the conductive base plate 92 includes a heat dissipation area and a base plate pin area 93, the to-be-packaged gallium nitride HEMT chip 70 is fixed and electrically connected to the heat dissipation area, so that the base plate pin area 93 is electrically connected with the source electrode 73 through the chip substrate, the conductive base plate 92 has the functions of a heat dissipation sheet and a base island, and the heat dissipation performance of the packaging structure is improved.
In the package structure of the embodiment of the present invention, the first conductive pad 91, the second conductive pad 94 and the third conductive pad 95 include a bonding area and a pin integrated with the bonding area; the connecting part of the welding area and the pin is provided with a bending part, so that the welding area is higher than the pin. Therefore, each electrical connecting part 80 is conveniently welded with the corresponding conductive bonding pad in the subsequent routing process, the routing length is reduced, and the cost is reduced. Alternatively, the first conductive pad 91 is electrically connected to the drain electrode 71 through at least one first electrical connection member 81. Each first conductive pad 91 individually corresponds to one exposed pin and one first electrical connection part 81, and the number of the first electrical connection parts 81 is set according to the current required by the chip so as to be at least 1.
The first conductive pad 91 includes: a drain bond pad and at least one drain lead integral with the drain bond pad; wherein the drain pad is electrically connected to the drain 71 through the first electrical connection member 81. In the manner shown in fig. 3, there are four drain lands, one drain lead for each, each of which is electrically connected to the drain 71 by a first electrical connection member 81. The number of drain pads may be set based on the requirements and is not limited to the manner shown in fig. 3.
The substrate lead region 93 is electrically connected to the source electrode 73 through at least one of the second electrical connection members 82, and the second conductive pad 94 is electrically connected to the source electrode 73 through one of the fourth electrical connection members 84. Each of the land lead areas 93 individually corresponds to one of the exposed leads and one of the second electrical connection members 82, and the number of the second electrical connection members 82 is set to be at least 1 according to a current required by the chip. The second conductive pad 94 has an insulating gap with the conductive substrate and an insulating gap with the third conductive pad 95, forming a kelvin source. Since the kelvin source current requirement is low and it is usually enough to provide one corresponding electrical connection member, the second conductive pad 94 is electrically connected to the source electrode 73 by one fourth electrical connection member 84, and the third conductive pad 95 is electrically connected to the gate electrode 72 by one third electrical connection member 83.
The submount lead area 93 includes: a source bonding pad and at least one source lead integral with the source bonding pad; wherein the source pad is electrically connected to the source electrode 73 through the second electrical connection member 82; the second conductive pad 94 includes: a kelvin source pad KS and a kelvin source; wherein the kelvin source pad KS is electrically connected to the source electrode 73 through the fourth electrical connection member 84. In the manner shown in fig. 3, there are 2 source pads, one for each source lead, each source pad being electrically connected to source 73 by a fourth electrical connection 84. The number of the fourth electrical connection members 84 may be set based on the requirement, and is not limited to the manner shown in fig. 3.
In the mode shown in fig. 3, the third conductive pad 95 is electrically connected to the gate electrode 72 by one third electrical connection member 83. The third conductive pad 95 includes: a gate pad and a gate lead; wherein the gate pad is electrically connected to the gate electrode 72 through the third electrical connection member 83.
In the embodiment of the present invention, the gan HEMT chip 70 to be packaged is a lateral structure, and the drain 71 and the source 73 are respectively disposed on two opposite long edges of the front surface of the chip, and are rectangular areas. The gate 72 is located on the short side of the front side of the chip. Thus, the drain electrode 71 can be electrically connected to the first conductive pad 90 through the plurality of first electrical connection members 81, and the source electrode 73 can be electrically connected to the pad pin region 93 through the plurality of second electrical connection members 82, and can be electrically connected to the fourth electrical connection member 84 and the second conductive pad 94, thereby facilitating the kelvin source electrode while achieving a sufficient withstand voltage distance between the electrodes of the chip after being connected to the conductive pads of the frame.
As shown in fig. 3 and 4, the package structure further includes: and the packaging layer 50 is used for sealing and protecting the to-be-packaged gallium nitride HEMT chip 70, and the packaging layer 50 covers the to-be-packaged gallium nitride HEMT chip 70 and each electrical connecting component 80. Optionally, the encapsulation layer 50 is an epoxy layer.
In the embodiment shown in fig. 3 and 4, the first electrical connection member 81, the second electrical connection member 82, the third electrical connection member 83, and the fourth electrical connection member 84 of the electrical connection member 80 are all lead wires. It is easy to know that in the package structure according to the embodiment of the present invention, the implementation manner of the electrical connection component may be set based on requirements, and is not limited to the manner shown in fig. 3 and 4, such as the manner shown in fig. 5.
Referring to fig. 5, fig. 5 is a schematic view of another packaging structure of a gallium nitride HEMT according to an embodiment of the present invention, which is different from the manner shown in fig. 3 and 4 in that in the electrical connection component 100, the first electrical connection component 101 and the second electrical connection component 102 are both metal strips, and the third electrical connection component 83 and the fourth electrical connection component 84 are both wires. The metal strip may be an aluminium strip. The metal band has smaller impedance relative to the conducting wire, and the number of routing wires can be reduced.
Based on the above embodiment, the utility model discloses another embodiment still provides a gallium nitride HEMT's packaging method, packaging method includes:
step S11: a gallium nitride HEMT chip to be packaged is provided.
The front surface of the to-be-packaged gallium nitride HEMT chip is provided with a grid electrode, a source electrode and a drain electrode; the gate is located between the source and the drain. The grid, the source and the drain are positioned on the semiconductor substrate.
In this step, the providing a to-be-packaged gallium nitride HEMT chip includes: firstly, providing a wafer; and then, thinning the back of the wafer, and dividing the wafer into a plurality of gallium nitride HEMT chips to be packaged through a scribing process.
The wafer can be thinned by 20-300 μm, and the wafer can be thinned by etching or mechanical masking or a combination of the two. Dicing may be performed by laser grooving to the semiconductor substrate.
Step S12: and fixing the gallium nitride HEMT chip to be packaged on the frame base plate.
The gallium nitride HEMT chip to be packaged may be fixed on the frame base by soft solder. The frame base plate is provided with a relatively fixed conductive base plate and a lead frame; the conductive base plate is provided with a heat dissipation area and a base plate pin area which are used for fixing the gallium nitride HEMT chip to be packaged; the back surface of the packaging gallium nitride HEMT chip is fixed and electrically connected with the heat dissipation area; a first conductive bonding pad, a second conductive bonding pad and a third conductive bonding pad are arranged on the lead frame; the conductive base plate and the lead frame are relatively fixed; the first conductive bonding pad is positioned on one side, provided with the drain electrode, of the to-be-packaged gallium nitride HEMT chip, and the base plate pin area, the second conductive bonding pad and the third conductive bonding pad are positioned on one side, provided with the source electrode, of the to-be-packaged gallium nitride HEMT chip;
step S13: and electrically interconnecting the gallium nitride HEMT chip to be packaged with each conductive bonding pad and the base plate pin area through a routing process.
The wire bonding process is the same as the conventional PDFN process. The drain electrode is electrically connected with the first conductive bonding pad through a first electrical connecting part, the source electrode is electrically connected with the base plate pin area through a second electrical connecting part, the grid electrode is electrically connected with the third conductive bonding pad through a third electrical connecting part, and the source electrode is also electrically connected with the second bonding pad through a fourth electrical connecting part.
Optionally, the packaging method further includes: and the packaging layer is used for sealing and protecting the gallium nitride HEMT chip to be packaged through a plastic packaging process, so that the gallium nitride HEMT chip to be packaged and each electrical connecting component are covered by the packaging layer. The plastic packaging process is the same as the traditional plastic packaging process.
And as the traditional PDFN process, the final product packaging is finished through subsequent process flows of curing, glue grinding, tinning, printing, product separation, inspection, packaging and the like.
The embodiment of the utility model provides a packaging method can be used for preparing above-mentioned embodiment packaging structure, simple process, and is with low costs, can prepare the packaging structure that heat dispersion is good and high electrical property index moreover.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. As for the packaging method disclosed in the embodiment, since it corresponds to the packaging structure disclosed in the embodiment, the description is relatively simple, and the relevant points can be referred to the description of the corresponding parts of the packaging structure.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A package structure of a gallium nitride HEMT, comprising:
the front surface of the gallium nitride HEMT chip to be packaged is provided with a grid electrode, a source electrode and a drain electrode; the grid electrode is positioned between the source electrode and the drain electrode;
the conductive base plate is provided with a heat dissipation area and a base plate pin area which are used for fixing the to-be-packaged gallium nitride HEMT chip;
the lead frame is provided with a first conductive bonding pad, a second conductive bonding pad and a third conductive bonding pad; the conductive base plate and the lead frame are relatively fixed;
the first conductive bonding pad is positioned on one side, provided with the drain, of the to-be-packaged gallium nitride HEMT chip, and the second conductive bonding pad and the third conductive bonding pad are positioned on one side, provided with the source, of the to-be-packaged gallium nitride HEMT chip; the back surface of the to-be-packaged gallium nitride HEMT chip is fixed and electrically connected with the heat dissipation area; the drain electrode is electrically connected with the first conductive bonding pad through a first electrical connecting part, the source electrode is electrically connected with the base plate pin area through a second electrical connecting part, the grid electrode is electrically connected with the third conductive bonding pad through a third electrical connecting part, and the source electrode is also electrically connected with the second conductive bonding pad through a fourth electrical connecting part.
2. The package structure of claim 1, wherein the submount lead area, the first conductive pad, the second conductive pad, and the third conductive pad each comprise a land area and a lead integral with the land area;
the connecting parts of the welding areas and the pins of the first conductive welding disc, the second conductive welding disc and the third conductive welding disc are provided with bending parts, so that the welding areas are higher than the pins.
3. The package structure of claim 1, wherein the first conductive pad is electrically connected to the drain via at least one of the first electrical connection members;
the first conductive pad includes: a drain bond pad and at least one drain lead integral with the drain bond pad;
wherein the drain pad is electrically connected to the drain through the first electrical connection member.
4. The package structure of claim 1, wherein the submount lead area is electrically connected to the source by at least one of the second electrical connection members, and the second conductive pad is electrically connected to the source by one of the fourth electrical connection members;
the submount pin area includes: a source bonding pad and at least one source lead integral with the source bonding pad; wherein the source bonding pad is electrically connected to the source electrode through the second electrically connecting member;
the second conductive pad includes: a Kelvin source pad and a Kelvin source; wherein the Kelvin source pad is electrically connected to the source through the fourth electrical connection member.
5. The package structure of claim 1, wherein the third conductive pad is electrically connected to the gate by one of the third electrical connection members.
6. The package structure of claim 5, wherein the third conductive pad comprises: a gate pad and a gate lead;
wherein the gate pad is electrically connected to the gate through the third electrical connection member.
7. The package structure according to claim 1, wherein the back surface of the to-be-packaged gallium nitride HEMT chip is fixed to the heat dissipation region by soft solder.
8. The package structure of any one of claims 1-7, further comprising: and the packaging layer is used for sealing and protecting the gallium nitride HEMT chip to be packaged, and covers the gallium nitride HEMT chip to be packaged and each electrical connecting component.
9. The package structure of claim 8, wherein the encapsulation layer is an epoxy layer.
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| CN201921898945.4U CN210837732U (en) | 2019-11-05 | 2019-11-05 | Packaging structure of gallium nitride HEMT |
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| CN201921898945.4U CN210837732U (en) | 2019-11-05 | 2019-11-05 | Packaging structure of gallium nitride HEMT |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113169150A (en) * | 2021-03-10 | 2021-07-23 | 英诺赛科(苏州)半导体有限公司 | III-nitride-based semiconductor package structure and manufacturing method thereof |
| CN116093058A (en) * | 2023-02-28 | 2023-05-09 | 中科华艺(天津)科技有限公司 | Gallium nitride semiconductor anti-interference packaging structure |
| US12040259B2 (en) | 2021-03-10 | 2024-07-16 | Innoscience (suzhou) Semiconductor Co., Ltd. | III-nitride-based semiconductor packaged structure and method for manufacturing the same |
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2019
- 2019-11-05 CN CN201921898945.4U patent/CN210837732U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113169150A (en) * | 2021-03-10 | 2021-07-23 | 英诺赛科(苏州)半导体有限公司 | III-nitride-based semiconductor package structure and manufacturing method thereof |
| CN113169150B (en) * | 2021-03-10 | 2022-06-14 | 英诺赛科(苏州)半导体有限公司 | III-nitride-based semiconductor package structure and manufacturing method thereof |
| US12040259B2 (en) | 2021-03-10 | 2024-07-16 | Innoscience (suzhou) Semiconductor Co., Ltd. | III-nitride-based semiconductor packaged structure and method for manufacturing the same |
| CN116093058A (en) * | 2023-02-28 | 2023-05-09 | 中科华艺(天津)科技有限公司 | Gallium nitride semiconductor anti-interference packaging structure |
| CN116093058B (en) * | 2023-02-28 | 2024-01-09 | 中科华艺(天津)科技有限公司 | Gallium nitride semiconductor anti-interference packaging structure |
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