JP5512845B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP5512845B2
JP5512845B2 JP2013034315A JP2013034315A JP5512845B2 JP 5512845 B2 JP5512845 B2 JP 5512845B2 JP 2013034315 A JP2013034315 A JP 2013034315A JP 2013034315 A JP2013034315 A JP 2013034315A JP 5512845 B2 JP5512845 B2 JP 5512845B2
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Japan
Prior art keywords
pad
ribbon
semiconductor device
semiconductor chip
metal ribbon
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JP2013034315A
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Japanese (ja)
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JP2013102233A (en
Inventor
勅子 沼田
仁久 佐藤
徹 植栗
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of JP5512845B2 publication Critical patent/JP5512845B2/en
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Description

本発明は、半導体装置およびその製造技術に関し、特に、半導体チップのボンディングパッドとリードフレームを金属リボンで接続する半導体装置およびその製造に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device in which a bonding pad of a semiconductor chip and a lead frame are connected by a metal ribbon and a technique effective when applied to the manufacturing thereof.

携帯情報機器の電力制御スイッチや充放電保護回路スイッチなどに使用されるパワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）が形成された半導体チップは、フラットリードパッケージ(Flat Lead Package)やＳＯＰ−８などの小型面実装パッケージに封止されている。   Semiconductor chips on which power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) used for power control switches and charge / discharge protection circuit switches of portable information devices are formed include Flat Lead Package and SOP-8. Sealed in a small surface mount package.

上記半導体チップは、その裏面がパワーＭＯＳＦＥＴのドレインを構成しており、Ａｇペーストなどの導電性接着剤を介してリードフレームのダイパッド部上に接合されている。半導体チップの主面の最上層には、パワーＭＯＳＦＥＴのソースに接続されたソースパッドと、ゲート電極に接続されたゲートパッドが形成されている。ソースパッドは、パワーＭＯＳＦＥＴのオン抵抗を低減するために、ゲートパッドよりも広い面積で形成されている。   The back surface of the semiconductor chip constitutes the drain of the power MOSFET and is bonded onto the die pad portion of the lead frame via a conductive adhesive such as Ag paste. A source pad connected to the source of the power MOSFET and a gate pad connected to the gate electrode are formed on the uppermost layer of the main surface of the semiconductor chip. The source pad is formed in a larger area than the gate pad in order to reduce the on-resistance of the power MOSFET.

上記半導体チップが封止されたモールド樹脂の外部には、外部接続端子を構成する複数本のリードが露出している。これらのリードは、ソースリード、ドレインリードおよびゲートリードからなる。ドレインリードは、ダイパッド部と一体に形成されており、このダイパッド部上に搭載された半導体チップの裏面（パワーＭＯＳＦＥＴのドレイン）と電気的に接続されている。   A plurality of leads constituting external connection terminals are exposed outside the mold resin in which the semiconductor chip is sealed. These leads include a source lead, a drain lead, and a gate lead. The drain lead is formed integrally with the die pad portion, and is electrically connected to the back surface (the drain of the power MOSFET) of the semiconductor chip mounted on the die pad portion.

近年、上記のような構造の面実装パッケージにおいては、パワーＭＯＳＦＥＴのオン抵抗を低減するために、可撓性のある金属リボンを使ってソースパッドとソースリードを接続する技術が実用化されている。   In recent years, in a surface mount package having the above-described structure, a technique for connecting a source pad and a source lead using a flexible metal ribbon has been put into practical use in order to reduce the on-resistance of a power MOSFET. .

金属リボンは、例えば厚さが数百μｍ程度のＡｌ（アルミニウム）箔やＣｕ（銅）箔などで構成されており、その幅はソースパッドの幅によっても異なるが、一般的には１ｍｍ前後である。ソースパッドおよびソースリードに金属リボンを接続するには、超音波振動を利用したウェッジボンディング法が用いられる。   The metal ribbon is made of, for example, Al (aluminum) foil or Cu (copper) foil having a thickness of about several hundreds μm. The width varies depending on the width of the source pad, but is generally around 1 mm. is there. In order to connect the metal ribbon to the source pad and the source lead, a wedge bonding method using ultrasonic vibration is used.

上記金属リボンの利点は、リボンの幅がＡｕ（金）ワイヤの直径に比べて遙かに大きいので、１本の金属リボンでもソースパッドに対して十分な接続面積を確保でき、ソースパッドとソースリードを複数本のＡｕワイヤで接続した場合に比べてパワーＭＯＳＦＥＴのオン抵抗を大幅に低減できることにある。また、Ａｕよりも安価なＡｌでリボンを構成するので、パッケージの材料原価を低減できるという効果もある。   The advantage of the metal ribbon is that the width of the ribbon is much larger than the diameter of the Au (gold) wire, so even a single metal ribbon can secure a sufficient connection area to the source pad. The on-resistance of the power MOSFET can be greatly reduced as compared with the case where the leads are connected by a plurality of Au wires. Further, since the ribbon is made of Al which is cheaper than Au, there is an effect that the material cost of the package can be reduced.

特許文献１は、上記した金属リボンの接続に用いるウェッジツールの改良技術を開示している。この公報に記載されたウェッジツールの下面には、金属リボンの延在方向と平行な方向に沿って複数の溝または切り欠きが設けられている。そのため、半導体チップ上に配置した金属リボンにこのウェッジツールを圧接すると、ツールの下面の一部だけが金属リボンと接触する。これにより、ウェッジツールから半導体チップの表面に過大な超音波振動エネルギーが伝わるのを防止できるので、半導体チップに亀裂や割れなどの破損が生じる不具合が軽減される。   Patent document 1 is disclosing the improvement technique of the wedge tool used for connection of an above-mentioned metal ribbon. A plurality of grooves or notches are provided on the lower surface of the wedge tool described in this publication along a direction parallel to the extending direction of the metal ribbon. Therefore, when this wedge tool is pressed against a metal ribbon arranged on a semiconductor chip, only a part of the lower surface of the tool comes into contact with the metal ribbon. As a result, it is possible to prevent excessive ultrasonic vibration energy from being transmitted from the wedge tool to the surface of the semiconductor chip, thereby reducing problems that cause breakage such as cracks and cracks in the semiconductor chip.

特許文献２には、圧着面に複数の突起と前記突起の間の複数の溝とを設けたリボンボンディング用のウェッジツールが開示されている。   Patent Document 2 discloses a wedge tool for ribbon bonding in which a plurality of protrusions and a plurality of grooves between the protrusions are provided on the crimping surface.

特許文献３には、圧着面に複数の突起部が形成されたリボンボンディング用のウェッジツールが開示されている。複数の突起部の各々は、対向する二側面が前記圧着面に対して傾斜し、これら二側面に隣接する他の二側面が前記圧着面に対して略垂直となっている。   Patent Document 3 discloses a wedge tool for ribbon bonding in which a plurality of protrusions are formed on the crimping surface. Each of the plurality of protrusions has two opposite side surfaces inclined with respect to the pressure-bonding surface, and the other two side surfaces adjacent to the two side surfaces are substantially perpendicular to the pressure-bonding surface.

特許文献４には、リボンボンディング用のウェッジツールの圧着面にローレット加工で突起を形成しておき、超音波接合の際に前記突起を金属リボン上に押し当てて押圧荷重、超音波振動を印加し、ヒートスプレッダ／金属リボン間の重なり面域に分散して所要の通電容量に対応した超音波接合部を形成する技術が開示されている。   In Patent Document 4, a protrusion is formed by knurling on the crimping surface of a wedge tool for ribbon bonding, and the protrusion is pressed onto a metal ribbon during ultrasonic bonding to apply a pressing load and ultrasonic vibration. However, there is disclosed a technique for forming ultrasonic bonding portions corresponding to a required energization capacity by dispersing in an overlapping surface area between a heat spreader and a metal ribbon.

特許文献５には、金属リボンのボンディングに際し、金属リボンに１つまたは複数のループを形成する技術を開示している。   Patent Document 5 discloses a technique for forming one or a plurality of loops in a metal ribbon when bonding the metal ribbon.

特開２００６−１９６６２９号公報JP 2006-196629 A 特表２００８−５２９３０３号公報Special table 2008-529303 gazette 特開２００６−１６５５１８号公報JP 2006-165518 A 特開２００６−１３５２７０号公報JP 2006-135270 A 特開２００４−３３６０４３号公報JP 2004-336043 A

パワーＭＯＳＦＥＴが形成された半導体チップのソースパッドに金属リボンをボンディングするには、まず、金属リボンの先端部を半導体チップのソースパッド上に位置決めした後、ウェッジツールの底面（圧着面）を金属リボンに圧接し、超音波振動を印加する。これにより、ウェッジツールの底面と接している領域の金属リボンが潰されてソースパッドの表面に接合される。   To bond the metal ribbon to the source pad of the semiconductor chip on which the power MOSFET is formed, first position the tip of the metal ribbon on the source pad of the semiconductor chip, and then attach the bottom surface (crimp surface) of the wedge tool to the metal ribbon. Apply ultrasonic vibration. As a result, the metal ribbon in the region in contact with the bottom surface of the wedge tool is crushed and joined to the surface of the source pad.

ところがコスト低減のため、半導体ウエハからの取得数を向上させようとすると半導体チップの外形寸法が小さくなり、これに伴いソースパッドの面積も小さくなる。このような面積が小さくなったソースパッドに安定したループを形成しながらボンディングを行うためには、金属リボンの厚さを薄くしなければならない。   However, in order to reduce the cost, if an attempt is made to increase the number of acquisitions from the semiconductor wafer, the outer dimensions of the semiconductor chip are reduced, and accordingly, the area of the source pad is also reduced. In order to perform bonding while forming a stable loop on the source pad having such a small area, the thickness of the metal ribbon must be reduced.

しかし、金属リボンの厚さを薄くすると、ソースパッドの表面に金属リボンをボンディングした時に、ウェッジツールによって潰された箇所の厚さが極めて薄くなるために、金属リボンが断線し易くなる。   However, when the thickness of the metal ribbon is reduced, the thickness of the portion crushed by the wedge tool becomes extremely thin when the metal ribbon is bonded to the surface of the source pad, and therefore the metal ribbon is easily disconnected.

このような金属リボンの断線を防止するためには、ウェッジツールに何らかの工夫が必要となるが、前述した特許文献１〜５には、このような微細なパッドに安定して金属リボンをボンディングする技術については記載されていない。   In order to prevent such disconnection of the metal ribbon, some contrivance is required for the wedge tool. However, in Patent Documents 1 to 5 described above, the metal ribbon is stably bonded to such a fine pad. The technology is not described.

本発明の目的は、半導体チップのパッドに金属リボンをボンディングする工程を伴う半導体装置の製造において、半導体チップのサイズ縮小に伴って金属リボンの厚さが薄くなった場合においても、ボンディング強度を保ちながら、金属リボンの断線を防止することのできる技術を提供することにある。   The object of the present invention is to maintain the bonding strength even when the thickness of the metal ribbon is reduced as the size of the semiconductor chip is reduced in the manufacture of a semiconductor device including the step of bonding the metal ribbon to the pad of the semiconductor chip. However, an object of the present invention is to provide a technique capable of preventing disconnection of the metal ribbon.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

本願の一発明は、半導体チップと、前記半導体チップの近傍に配置された第１導体と、前記半導体チップの主面に形成されたパッドと前記第１導体とを電気的に接続する金属リボンとを有する半導体装置であって、前記半導体チップの前記パッドに接続された前記金属リボンは、その幅方向の両端部の厚さが前記両端部の内側の部分の厚さよりも厚いものである。   One invention of this application is a semiconductor chip, the 1st conductor arrange | positioned in the vicinity of the said semiconductor chip, the metal ribbon which electrically connects the pad formed in the main surface of the said semiconductor chip, and the said 1st conductor. The metal ribbon connected to the pad of the semiconductor chip has a thickness at both end portions in the width direction that is greater than a thickness at an inner portion of the both end portions.

本願の他の一発明は、半導体チップの主面に形成されたパッドに金属リボンをボンディングする工程を含む半導体装置の製造方法であって、前記ボンディング工程で用いるウェッジツールは、前記金属リボンの幅方向の両端部に対向する圧着面の両端部に凹部が設けられているものである。   Another invention of the present application is a method of manufacturing a semiconductor device including a step of bonding a metal ribbon to a pad formed on a main surface of a semiconductor chip, wherein the wedge tool used in the bonding step is a width of the metal ribbon. Concave portions are provided at both ends of the pressure-bonding surface facing both ends in the direction.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下の通りである。   The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

半導体チップのサイズ縮小に伴って金属リボンの厚さが薄くなった場合においても、ボンディング強度を保ちながら、金属リボンの断線を防止することが可能となる。   Even when the thickness of the metal ribbon is reduced as the size of the semiconductor chip is reduced, the disconnection of the metal ribbon can be prevented while maintaining the bonding strength.

（ａ）は、本発明の実施の形態１である半導体装置の上面を示す平面図、（ｂ）は、この半導体装置の短辺側の側面図である。(A) is a top view which shows the upper surface of the semiconductor device which is Embodiment 1 of this invention, (b) is a side view by the side of the short side of this semiconductor device. 本発明の実施の形態１である半導体装置の裏面（実装面）を示す平面図である。It is a top view which shows the back surface (mounting surface) of the semiconductor device which is Embodiment 1 of this invention. 本発明の実施の形態１である半導体装置の内部構造を示す平面図である。It is a top view which shows the internal structure of the semiconductor device which is Embodiment 1 of this invention. 図３のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 半導体チップに形成されたトレンチゲート型のｎチャネルパワーＭＯＳＦＥＴを示す要部断面図である。It is principal part sectional drawing which shows the trench gate type n channel power MOSFET formed in the semiconductor chip. 半導体チップに形成されたゲート引出し電極、ゲートパッドおよびソースパッドのレイアウトを示す平面図である。It is a top view which shows the layout of the gate extraction electrode, gate pad, and source pad which were formed in the semiconductor chip. 図６の符号Ｂで示す領域におけるゲート電極のレイアウトを示す斜視図である。It is a perspective view which shows the layout of the gate electrode in the area | region shown with the code | symbol B of FIG. 一般的なリボンボンディング装置のウェッジツールを使ったリボンボンディング方法を説明する斜視図である。It is a perspective view explaining the ribbon bonding method using the wedge tool of the general ribbon bonding apparatus. 一般的なリボンボンディング装置のウェッジツールを使ったリボンボンディング方法を説明する斜視図である。It is a perspective view explaining the ribbon bonding method using the wedge tool of the general ribbon bonding apparatus. （ａ）は、本発明の実施の形態１である半導体装置の製造方法で使用するウェッジツールを下方から見た平面図、（ｂ）は、このウェッジツールの圧着面を示す平面図である。(A) is the top view which looked at the wedge tool used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention from the bottom, (b) is a top view which shows the crimping | compression-bonding surface of this wedge tool. （ａ）は、本発明の実施の形態１である半導体装置の製造方法で使用するウェッジツールの先端部を示す斜視図、（ｂ）は、このウェッジツールの先端部を示す側面図である。(A) is a perspective view which shows the front-end | tip part of the wedge tool used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention, (b) is a side view which shows the front-end | tip part of this wedge tool. （ａ）は、本発明の実施の形態１である半導体装置の製造方法で使用するウェッジツールの先端部の別例を示す斜視図、（ｂ）は、このウェッジツールの先端部を示す側面図である。(A) is a perspective view which shows another example of the front-end | tip part of the wedge tool used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention, (b) is a side view which shows the front-end | tip part of this wedge tool It is. （ａ）は、本発明の実施の形態１である半導体装置の製造方法で使用するウェッジツールの先端部の別例を示す斜視図、（ｂ）は、このウェッジツールの先端部を示す側面図である。(A) is a perspective view which shows another example of the front-end | tip part of the wedge tool used with the manufacturing method of the semiconductor device which is Embodiment 1 of this invention, (b) is a side view which shows the front-end | tip part of this wedge tool It is. リボンボンディング装置に装着されたウェッジツールの先端部近傍を示す側面図である。It is a side view which shows the front-end | tip part vicinity of the wedge tool with which the ribbon bonding apparatus was mounted | worn. 本発明の実施の形態１である半導体装置の製造工程を示す全体フロー図である。1 is an overall flowchart showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１である半導体装置の製造工程を示す斜視図である。It is a perspective view which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. 本発明の実施の形態１である半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. 図１６に続く半導体装置の製造工程を示す斜視図である。FIG. 17 is a perspective view illustrating a manufacturing step of the semiconductor device following that of FIG. 16; 図１７に続く半導体装置の製造工程を示す断面図である。FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; 図１８に続く半導体装置の製造工程を示す斜視図である。FIG. 19 is a perspective view illustrating a manufacturing step of the semiconductor device following that of FIG. 18; 図１９に続く半導体装置の製造工程を示す断面図である。FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; （ａ）は、ソースパッドにボンディングされたＡｌリボンの平面図、（ｂ）は、ウェッジツールの先端部の形状を示す側面図と、（ａ）のＢ−Ｂ’線およびＣ−Ｃ’線に沿ったＡｌリボンの断面図である。(A) is a plan view of the Al ribbon bonded to the source pad, (b) is a side view showing the shape of the tip of the wedge tool, and (BB) and CC ′ lines in (a). It is sectional drawing of the Al ribbon along. 図２１に続く半導体装置の製造工程を示す断面図である。FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; 図２３に続く半導体装置の製造工程を示す断面図である。FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; 図２４に続く半導体装置の製造工程を示す斜視図である。FIG. 25 is a perspective view illustrating a manufacturing step of the semiconductor device following that of FIG. 24; 図２５に続く半導体装置の製造工程を示す斜視図である。FIG. 26 is a perspective view illustrating a manufacturing step of the semiconductor device following that of FIG. 25; 本発明の実施の形態２である半導体装置の内部構造を示す平面図である。It is a top view which shows the internal structure of the semiconductor device which is Embodiment 2 of this invention. 本発明の実施の形態３である半導体装置の製造方法を示す斜視図である。It is a perspective view which shows the manufacturing method of the semiconductor device which is Embodiment 3 of this invention. 本発明の他の実施の形態である半導体装置の上面を示す平面図である。It is a top view which shows the upper surface of the semiconductor device which is other embodiment of this invention. 図２９に示す半導体装置の内部構造を示す平面図である。FIG. 30 is a plan view showing an internal structure of the semiconductor device shown in FIG. 29. 本発明の他の実施の形態である半導体装置の内部構造を示す平面図である。It is a top view which shows the internal structure of the semiconductor device which is other embodiment of this invention.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

また、以下の実施の形態では、特に必要なときを除き、同一または同様な部分の説明を原則として繰り返さない。以下の実施の形態を説明する図面においては、構成を分かり易くするために、平面図であってもハッチングを付す場合がある。   Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. In the drawings for explaining the following embodiments, hatching may be given even in a plan view for easy understanding of the configuration.

また、以下の実施の形態において、Ａｌリボンとは、Ａｌを主成分とする導電材料で構成された帯状の結線材料を意味している。通常、Ａｌリボンは、スプールに巻かれた状態でボンディング装置に設置される。Ａｌリボンは、極めて薄いため、リードフレームや半導体チップのパッドに接続する際には、長さやループ形状を任意に設定することができるという特徴がある。   In the following embodiments, an Al ribbon means a strip-shaped connecting material made of a conductive material mainly composed of Al. Usually, the Al ribbon is installed in a bonding apparatus while being wound on a spool. Since the Al ribbon is extremely thin, the length and the loop shape can be arbitrarily set when connecting to a lead frame or a pad of a semiconductor chip.

（実施の形態１）
本実施の形態の半導体装置は、面実装パッケージの一種のフラットリードパッケージ(Flat Lead Package：以下、ＦＬＰという)に適用したものである。図１（ａ）は、このＦＬＰの上面を示す平面図、（ｂ）は、短辺側の側面図、図２は、裏面（実装面）を示す平面図、図３は、内部構造を示す平面図、図４は、図３のＡ−Ａ線に沿った断面図である。 (Embodiment 1)
The semiconductor device of the present embodiment is applied to a kind of flat lead package (hereinafter referred to as FLP) which is a surface mount package. 1A is a plan view showing the upper surface of the FLP, FIG. 1B is a side view of the short side, FIG. 2 is a plan view showing the back surface (mounting surface), and FIG. 3 shows the internal structure. 4 is a cross-sectional view taken along line AA in FIG.

ＦＬＰは、リードフレームのダイパッド部３Ｄ上に搭載した半導体チップ１をモールド樹脂２で封止した小型面実装パッケージであり、その外形寸法は、長辺＝６．１ｍｍ、短辺＝５．３ｍｍ、厚さ＝０．８ｍｍである。   FLP is a small surface-mount package in which a semiconductor chip 1 mounted on a die pad portion 3D of a lead frame is sealed with a mold resin 2, and its outer dimensions are long side = 6.1 mm, short side = 5.3 mm, Thickness = 0.8 mm.

シリコンフィラーを含浸させたエポキシ系樹脂からなるモールド樹脂２の短辺側の側面には、ＦＬＰの外部接続端子を構成する８本のリード３（♯１〜♯８）が露出している。これらのリード３のうち、図１および図２に示す１番リード（♯１）から３番リード（♯３）はソースリード、４番リード（♯４）はゲートリード、５番リード（♯５）から８番リード（♯８）はドレインリードである。また、モールド樹脂２の裏面には、半導体チップ１で発生した熱の放熱およびパッケージの放熱性向上のために、８本のリード３の裏面とダイパッド部３Ｄの裏面とが外部に露出している。ダイパッド部３Ｄおよび８本のリード３は、Ｃｕ（銅）またはＦｅ−Ｎｉ（鉄−ニッケル）合金からなり、その表面には、Ｎｉ（ニッケル）膜、Ｐｄ（パラジウム）膜およびＡｕ（金）膜を積層した３層構造のメッキが施されている。   Eight leads 3 (# 1 to # 8) constituting external connection terminals of the FLP are exposed on the side surface on the short side of the mold resin 2 made of epoxy resin impregnated with silicon filler. Of these leads 3, the first lead (# 1) to the third lead (# 3) shown in FIGS. 1 and 2 are the source lead, the fourth lead (# 4) is the gate lead, and the fifth lead (# 5). ) To No. 8 lead (# 8) is a drain lead. Further, the back surface of the eight leads 3 and the back surface of the die pad portion 3D are exposed to the outside on the back surface of the mold resin 2 in order to dissipate heat generated in the semiconductor chip 1 and improve heat dissipation of the package. . The die pad portion 3D and the eight leads 3 are made of Cu (copper) or Fe—Ni (iron-nickel) alloy, and Ni (nickel) film, Pd (palladium) film, and Au (gold) film are formed on the surface thereof. A three-layer structure in which is laminated is applied.

上記８本のリード３のうち、３本のソースリード（♯１〜♯３）は、モールド樹脂２の内部で互いに連結されている。すなわち、３本のソースリード（♯１〜♯３）は、電気的に接続されている。以下、モールド樹脂２の内部に位置するソースリードをソースポスト３Ｓと称する。また、ゲートリード（♯５）のうち、モールド樹脂２の内部に位置する部分をゲートポスト３Ｇと称する。一方、４本のドレインリード（♯５〜♯８）は、モールド樹脂２の内部でダイパッド部３Ｄと一体に構成されている。   Of the eight leads 3, three source leads (# 1 to # 3) are connected to each other inside the mold resin 2. That is, the three source leads (# 1 to # 3) are electrically connected. Hereinafter, the source lead located inside the mold resin 2 is referred to as a source post 3S. Further, a portion of the gate lead (# 5) located inside the mold resin 2 is referred to as a gate post 3G. On the other hand, the four drain leads (# 5 to # 8) are integrally formed with the die pad portion 3D inside the mold resin 2.

ダイパッド部３Ｄ上には、Ａｇペーストや半田などの導電性接着剤４を介して半導体チップ１が搭載されている。半導体チップ１は単結晶シリコンからなり、その主面には、例えば携帯情報機器の電力制御スイッチや充放電保護回路スイッチなどに使用される複数個のパワーＭＯＳＦＥＴ（パワー素子）が形成されている。半導体チップ１の裏面は、これらのパワーＭＯＳＦＥＴに共通のドレインを構成しており、導電性接着剤４およびダイパッド部３Ｄを介してドレインリード（♯５〜♯８）と電気的に接続されている。   The semiconductor chip 1 is mounted on the die pad portion 3D via a conductive adhesive 4 such as Ag paste or solder. The semiconductor chip 1 is made of single crystal silicon, and a plurality of power MOSFETs (power elements) used for, for example, a power control switch and a charge / discharge protection circuit switch of a portable information device are formed on the main surface. The back surface of the semiconductor chip 1 constitutes a drain common to these power MOSFETs, and is electrically connected to the drain leads (# 5 to # 8) via the conductive adhesive 4 and the die pad portion 3D. .

また、半導体チップ１の主面には、パワーＭＯＳＦＥＴのゲート電極と電気的に接続された１個のゲートパッド５と、パワーＭＯＳＦＥＴのソースと電気的に接続された２個のソースパッド６とが形成されている。そして、ゲートパッド５は、Ａｕワイヤ７を介してゲートポスト３Ｇと電気的に接続されている。一方、２個のソースパッド６のそれぞれは、パワーＭＯＳＦＥＴのオン抵抗を低減するために、ゲートパッド５よりも広い面積で構成されており、かつＡｕワイヤ７よりも広い面積を有するＡｌリボン８を介してソースポスト３Ｓと電気的に接続されている。   Also, on the main surface of the semiconductor chip 1, there are one gate pad 5 electrically connected to the gate electrode of the power MOSFET and two source pads 6 electrically connected to the source of the power MOSFET. Is formed. The gate pad 5 is electrically connected to the gate post 3G via the Au wire 7. On the other hand, each of the two source pads 6 has an Al ribbon 8 having a larger area than the gate pad 5 and a larger area than the Au wire 7 in order to reduce the on-resistance of the power MOSFET. And is electrically connected to the source post 3S.

図５は、半導体チップ１に形成されたトレンチゲート型のｎチャネルパワーＭＯＳＦＥＴを示す要部断面図である。   FIG. 5 is a cross-sectional view of a main part showing a trench gate type n-channel power MOSFET formed in the semiconductor chip 1.

ｎ＋型単結晶シリコン基板３０の主面には、ｎ−型単結晶シリコン層３１が形成されており、ｎ−型単結晶シリコン層３１の上部には、ｐ型半導体領域３２が形成されている。また、ｐ型半導体領域３２の表面には、ｎ＋型半導体領域３３が形成されている。ｎ＋型単結晶シリコン基板３０およびｎ−型単結晶シリコン層３１は、パワーＭＯＳＦＥＴのドレインを構成する半導体領域であり、ｎ＋型半導体領域３３は、パワーＭＯＳＦＥＴのソースを構成する半導体領域である。また、ｐ型半導体領域３２は、パワーＭＯＳＦＥＴのチャネルが形成される半導体領域である。 An n − type single crystal silicon layer 31 is formed on the main surface of the n + type single crystal silicon substrate 30, and a p type semiconductor region 32 is formed on the n − type single crystal silicon layer 31. Yes. An n + type semiconductor region 33 is formed on the surface of the p type semiconductor region 32. The n + type single crystal silicon substrate 30 and the n − type single crystal silicon layer 31 are semiconductor regions constituting the drain of the power MOSFET, and the n + type semiconductor region 33 is a semiconductor region constituting the source of the power MOSFET. . The p-type semiconductor region 32 is a semiconductor region where a channel of the power MOSFET is formed.

ｐ型半導体領域３２の一部には、底部がｎ−型単結晶シリコン層（ドレイン）３１に達する溝３４が形成されており、溝３４の内部には、パワーＭＯＳＦＥＴのゲート絶縁膜３５およびゲート電極３６が形成されている。ゲート絶縁膜３５は酸化シリコン膜からなり、ゲート電極３６はｎ型多結晶シリコン膜からなる。ゲート電極３６の上端部は溝３４の上方に突出しており、その両側には酸化シリコン膜からなるサイドウォールスペーサ３７が形成されている。また、ゲート電極３６の上部には、窒化シリコン膜３８および酸化シリコン膜３９が形成されている。 A trench 34 whose bottom reaches the n − -type single crystal silicon layer (drain) 31 is formed in a part of the p-type semiconductor region 32. Inside the trench 34, a gate insulating film 35 and a gate of a power MOSFET are formed. An electrode 36 is formed. The gate insulating film 35 is made of a silicon oxide film, and the gate electrode 36 is made of an n-type polycrystalline silicon film. An upper end portion of the gate electrode 36 protrudes above the groove 34, and sidewall spacers 37 made of a silicon oxide film are formed on both sides thereof. A silicon nitride film 38 and a silicon oxide film 39 are formed on the gate electrode 36.

酸化シリコン膜３９の上部には、ソース電極４１およびゲート引出し電極４２が形成されている。ソース電極４１およびゲート引出し電極４２は、Ｔｉ膜とＴｉＮ膜の積層膜からなるバリアメタル膜４３の上部にＡｌ合金膜４４を堆積した導電膜で構成されている。ソース電極４１は、窒化シリコン膜３８および酸化シリコン膜３９に形成された接続孔４５を通じてパワーＭＯＳＦＥＴのソース（ｎ＋型半導体領域３３）と電気的に接続されている。また、ゲート引出し電極４２は、図には示さない領域の窒化シリコン膜３８および酸化シリコン膜３９に形成された接続孔を通じて、パワーＭＯＳＦＥＴのゲート電極３６と電気的に接続されている。 A source electrode 41 and a gate lead electrode 42 are formed on the silicon oxide film 39. The source electrode 41 and the gate lead electrode 42 are composed of a conductive film in which an Al alloy film 44 is deposited on top of a barrier metal film 43 formed of a laminated film of a Ti film and a TiN film. The source electrode 41 is electrically connected to the source of the power MOSFET (n + type semiconductor region 33) through a connection hole 45 formed in the silicon nitride film 38 and the silicon oxide film 39. The gate lead electrode 42 is electrically connected to the gate electrode 36 of the power MOSFET through a connection hole formed in the silicon nitride film 38 and the silicon oxide film 39 in a region not shown in the drawing.

ソース電極４１およびゲート引出し電極４２の上部には、酸化シリコン膜と窒化シリコン膜との積層膜からなる表面保護膜４６が形成されている。ソース電極４１は、その上部を覆う表面保護膜４６の一部が除去され、半導体チップ１の表面に露出している。また、ゲート引出し電極４２は、その上部を覆う表面保護膜４６の一部が除去され、半導体チップ１の表面に露出している。ソース電極４１のうち、半導体チップ１の表面に露出した領域は、前記ソースパッド６を構成しており、ゲート引出し電極４２のうち、半導体チップ１の表面に露出した領域は、前記ゲートパッド５を構成している。図５には示さないが、ソースパッド６の表面には前記Ａｌリボン８がボンディングされており、ゲートパッド５の表面には前記Ａｕワイヤ７がボンディングされている。   A surface protection film 46 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the source electrode 41 and the gate lead electrode 42. The source electrode 41 is exposed on the surface of the semiconductor chip 1 by removing a part of the surface protection film 46 covering the upper portion of the source electrode 41. Further, the gate lead electrode 42 is exposed on the surface of the semiconductor chip 1 by removing a part of the surface protection film 46 covering the upper portion thereof. A region of the source electrode 41 exposed on the surface of the semiconductor chip 1 constitutes the source pad 6, and a region of the gate lead electrode 42 exposed on the surface of the semiconductor chip 1 defines the gate pad 5. It is composed. Although not shown in FIG. 5, the Al ribbon 8 is bonded to the surface of the source pad 6, and the Au wire 7 is bonded to the surface of the gate pad 5.

図６は、上記半導体チップ１に形成されたゲート引出し電極４２、ゲートパッド５およびソースパッド６のレイアウトを示す平面図である。   FIG. 6 is a plan view showing a layout of the gate extraction electrode 42, the gate pad 5 and the source pad 6 formed on the semiconductor chip 1.

この半導体チップ１の平面形状は、長辺＝１．６ｍｍ、短辺＝１．０ｍｍの長方形である。また、２個のソースパッド６（６ａ、６ｂ）のそれぞれの平面形状は、長辺＝１．０２ｍｍ、短辺＝０．２２５ｍｍの長方形であり、ゲートパッド５の平面形状は、１辺＝０．１２ｍｍの正方形である。   The planar shape of the semiconductor chip 1 is a rectangle having a long side = 1.6 mm and a short side = 1.0 mm. The planar shape of each of the two source pads 6 (6a, 6b) is a rectangle having a long side = 1.02 mm and a short side = 0.225 mm, and the planar shape of the gate pad 5 is 1 side = 0. .12 mm square.

ゲート引出し電極４２は、半導体チップ１の主面の外周部と中央部とに配置されており、ゲートパッド５は、半導体チップ１の中央部に配置されたゲート引出し電極４２の一端に配置されている。半導体チップ１の主面上でゲート引出し電極４２およびゲートパッド５をこのように配置した場合は、図７（図６の符号Ｂで示す領域におけるゲート電極３６のレイアウトを示す斜視図）に示すように、パワーＭＯＳＦＥＴのそれぞれのゲート電極３６の一端がゲート引出し電極４２に向かって直線状に延在し、ゲート引出し電極４２と電気的に接続される。これにより、半導体チップ１の全体でゲート電極３６の長さを最短化することができるので、例えば半導体チップ１の中央部に１個のソースパッド６を配置し、周辺部にゲートパッド５を配置したレイアウトに比べてゲート抵抗（Ｒｇ）が半分以下に低減され、パワーＭＯＳＦＥＴのスイッチング特性が向上する。   The gate extraction electrode 42 is disposed at the outer peripheral portion and the central portion of the main surface of the semiconductor chip 1, and the gate pad 5 is disposed at one end of the gate extraction electrode 42 disposed at the central portion of the semiconductor chip 1. Yes. When the gate extraction electrode 42 and the gate pad 5 are arranged in this manner on the main surface of the semiconductor chip 1, as shown in FIG. 7 (a perspective view showing the layout of the gate electrode 36 in the region indicated by reference numeral B in FIG. 6). Further, one end of each gate electrode 36 of the power MOSFET extends linearly toward the gate lead electrode 42 and is electrically connected to the gate lead electrode 42. Thereby, since the length of the gate electrode 36 can be minimized in the entire semiconductor chip 1, for example, one source pad 6 is disposed in the central portion of the semiconductor chip 1, and the gate pad 5 is disposed in the peripheral portion. Compared with the layout described above, the gate resistance (Rg) is reduced to half or less, and the switching characteristics of the power MOSFET are improved.

一方、半導体チップ１の中央部にゲート引出し電極４２を配置したことにより、このゲート引出し電極４２と同層の導電膜で構成されるソース電極４１は、このゲート引出し電極４２を挟んでその両側に形成される。従って、ソースパッド６もこのゲート引出し電極４２を挟んでその両側に１個ずつ配置される。   On the other hand, since the gate lead electrode 42 is disposed at the center of the semiconductor chip 1, the source electrode 41 composed of a conductive film in the same layer as the gate lead electrode 42 is disposed on both sides of the gate lead electrode 42. It is formed. Therefore, one source pad 6 is also arranged on each side of the gate extraction electrode 42.

このように、本実施の形態のＦＬＰは、パワーＭＯＳＦＥＴのスイッチング特性を向上させるために、半導体チップ１の中央部にゲート引出し電極４２を配置し、このゲート引出し電極４２に接続されるゲート電極３６の長さを最短化することによって、ゲート抵抗（Ｒｇ）の低減を図っている。また、これにより、ソースパッド６は、ゲート引出し電極４２を挟んでその両側に１個ずつ配置される。従って、ソースポスト３Ｓと半導体チップ１とを電気的に接続するＡｌリボン８の一端は、２個のソースパッド６のそれぞれの表面にボンディングされている。   As described above, in the FLP according to the present embodiment, in order to improve the switching characteristics of the power MOSFET, the gate lead electrode 42 is arranged in the central portion of the semiconductor chip 1, and the gate electrode 36 connected to the gate lead electrode 42. The gate resistance (Rg) is reduced by minimizing the length of. As a result, one source pad 6 is arranged on each side of the gate extraction electrode 42 with the gate extraction electrode 42 interposed therebetween. Therefore, one end of the Al ribbon 8 that electrically connects the source post 3S and the semiconductor chip 1 is bonded to the surface of each of the two source pads 6.

ここで、一般的なリボンボンディング装置のウェッジツールを使って、上記半導体チップ１の２個のソースパッド６にＡｌリボン８をボンディングする場合の問題点について説明する。   Here, a problem when the Al ribbon 8 is bonded to the two source pads 6 of the semiconductor chip 1 using a wedge tool of a general ribbon bonding apparatus will be described.

２個のソースパッド６にＡｌリボン８をボンディングするには、まず、図８に示すように、Ａｌリボン８の先端部を半導体チップ１の第１のソースパッド６上に位置決めした後、ウェッジツール２０の圧着面をＡｌリボン８に圧接し、数Ｗ程度のエネルギーの超音波振動を印加する。これにより、ウェッジツール２０の圧着面と接する領域のＡｌリボン８が潰されて第１のソースパッド６の表面にボンディングされる。次に、ウェッジツール２０を第２のソースパッド６上に移動させた後、図９に示すように、ウェッジツール２０の圧着面をＡｌリボン８に圧接し、数Ｗ程度のエネルギーの超音波振動を印加する。これにより、ウェッジツール２０の底面と接する領域のＡｌリボン８が潰されて第２のソースパッド６の表面にボンディングされる。   In order to bond the Al ribbon 8 to the two source pads 6, first, as shown in FIG. 8, after positioning the tip of the Al ribbon 8 on the first source pad 6 of the semiconductor chip 1, a wedge tool The pressure contact surface of 20 is pressed against the Al ribbon 8, and ultrasonic vibration having an energy of about several W is applied. As a result, the Al ribbon 8 in a region in contact with the crimping surface of the wedge tool 20 is crushed and bonded to the surface of the first source pad 6. Next, after moving the wedge tool 20 onto the second source pad 6, as shown in FIG. 9, the pressure contact surface of the wedge tool 20 is pressed against the Al ribbon 8, and ultrasonic vibration with an energy of about several W is performed. Apply. Thereby, the Al ribbon 8 in a region in contact with the bottom surface of the wedge tool 20 is crushed and bonded to the surface of the second source pad 6.

前述したように、２個のソースパッド６の間には、ゲートパッド５に接続されるゲート引出し電極４２が配置されている。従って、上記ウェッジツール２０を使って２個のソースパッド６にＡｌリボン８をボンディングする際は、図９に示すように、２個のソースパッド６の間のＡｌリボン８にループを形成し、ゲート引出し電極４２にボンディングダメージが及ばないようにする。なお、この時にループの高さを低くすると、半導体チップ１をモールド樹脂２で封止する際に、半導体チップ１の表面とＡｌリボン８との隙間にモールド樹脂２が入り込めず、空隙（ボイド）が生じる恐れがある。このようなボイドは、そこに水分が溜まり、本半導体装置を配線基板に実装する際の半田付けリフローで水分が体積膨張することで、パッケージクラック等の不具合を引き起こす原因となることが多い。従って、このような不具合を避けるためには、半導体チップ１とＡｌリボン８との間にモールド樹脂２が入り込めるように、ループの高さを調整する必要がある。   As described above, the gate lead electrode 42 connected to the gate pad 5 is disposed between the two source pads 6. Therefore, when bonding the Al ribbon 8 to the two source pads 6 using the wedge tool 20, a loop is formed in the Al ribbon 8 between the two source pads 6, as shown in FIG. Bonding damage is prevented from affecting the gate lead electrode 42. If the height of the loop is lowered at this time, when the semiconductor chip 1 is sealed with the mold resin 2, the mold resin 2 cannot enter the gap between the surface of the semiconductor chip 1 and the Al ribbon 8, and voids (voids) ) May occur. Such voids often cause moisture such as package cracks and the like due to volume expansion due to solder reflow when the semiconductor device is mounted on a wiring board. Therefore, in order to avoid such a problem, it is necessary to adjust the height of the loop so that the mold resin 2 can enter between the semiconductor chip 1 and the Al ribbon 8.

ところが、本実施の形態のＦＬＰは、半導体チップ１の外形寸法が非常に小さいために、２個のソースパッド６の間隔が非常に狭くなっている。従って、２個のソースパッド６を跨ぐＡｌリボン８にループを形成するためには、Ａｌリボン８の厚さを０．１ｍｍ以下、好ましくは０．０５ｍｍ程度まで薄くしなければならない。   However, in the FLP according to the present embodiment, since the external dimensions of the semiconductor chip 1 are very small, the distance between the two source pads 6 is very narrow. Therefore, in order to form a loop in the Al ribbon 8 straddling the two source pads 6, the thickness of the Al ribbon 8 must be reduced to 0.1 mm or less, preferably about 0.05 mm.

しかし、Ａｌリボン８をこのように薄くすると、ソースパッド６の表面にＡｌリボン８をボンディングした時に、ウェッジツール２０によって潰された箇所の厚さが極めて薄くなるために、Ａｌリボン８の幅方向の両端部（図９の矢印で示す箇所）に亀裂が発生し、この亀裂が両端部から内側に進行してＡｌリボン８が断線することがある。   However, when the Al ribbon 8 is thinned in this way, the thickness of the portion crushed by the wedge tool 20 becomes extremely thin when the Al ribbon 8 is bonded to the surface of the source pad 6. Cracks may occur at both ends (locations indicated by arrows in FIG. 9), and the cracks may progress inward from both ends to break the Al ribbon 8.

また、間隔が狭い２個のソースパッド６の間にループを形成すると、ループの立ち上がりが非常に急峻になるために、ループが立ち上がる領域のＡｌリボン８に強い曲げ応力が加わる。従って、近接して配置された２個のソースパッド６に極めて薄いＡｌリボン８をボンディングする場合は、特に、第１のソースパッド６上でＡｌリボン８が断線し易い。   In addition, when a loop is formed between two source pads 6 having a small interval, the rise of the loop becomes very steep, and a strong bending stress is applied to the Al ribbon 8 in the region where the loop rises. Therefore, when bonding an extremely thin Al ribbon 8 to two source pads 6 arranged close to each other, the Al ribbon 8 easily breaks on the first source pad 6 in particular.

そこで、本実施の形態では、次のようなウェッジツールを使ってＡｌリボン８のボンディングを行う。   Therefore, in the present embodiment, the Al ribbon 8 is bonded using the following wedge tool.

図１０（ａ）は、本実施の形態で使用するウェッジツールを下方から見た平面図、（ｂ）は、このウェッジツールの圧着面を示す平面図、図１１（ａ）は、このウェッジツールの先端部を示す斜視図、（ｂ）は、このウェッジツールの先端部を示す側面図である。また、図１１（ｂ）には、このウェッジツールが圧接された時のＡｌリボンの断面構造も示されている。   10A is a plan view of the wedge tool used in the present embodiment as viewed from below, FIG. 10B is a plan view showing the crimping surface of the wedge tool, and FIG. 11A is the wedge tool. The perspective view which shows the front-end | tip part of this, (b) is a side view which shows the front-end | tip part of this wedge tool. FIG. 11B also shows the cross-sectional structure of the Al ribbon when the wedge tool is pressed.

本実施の形態で使用するウェッジツール１０は、ステンレス鋼（ＳＵＳ３０４）などの金属で構成されており、その圧着面は、長方形の平面形状を有している。圧着面の長辺の長さはＡｌリボン８の幅よりも大きく、かつソースパッド６の長辺よりも短い（例えば０．８９ｍｍ〜０．９ｍｍ程度）。また、短辺の長さは、ソースパッド６の短辺よりも短い（例えば０．０９ｍｍ程度）。   The wedge tool 10 used in the present embodiment is made of a metal such as stainless steel (SUS304), and its crimping surface has a rectangular planar shape. The length of the long side of the crimping surface is larger than the width of the Al ribbon 8 and shorter than the long side of the source pad 6 (for example, about 0.89 mm to 0.9 mm). The short side is shorter than the short side of the source pad 6 (for example, about 0.09 mm).

また、本実施の形態で使用するウェッジツール１０は、圧着面の長辺方向の両端部に凹部１０ａ（第１の凹部）が設けられている。一方、圧着面の中央部には、２つの浅い凹溝１０ｂ（第２の凹部）を挟んで３つの凸部１０ｃが設けられている。ここで、図１１（ｂ）に示す凸部１０ｃと凹部１０ａとの段差Ｌａは、Ａｌリボン８の厚さよりも大きくなるように設定されており、例えばＡｌリボン８の厚さを０．０５ｍｍとした場合、凸部１０ｃと凹部１０ａとの段差は、０．０６ｍｍ程度である。従って、このウェッジツール１０の圧着面をＡｌリボン８に圧接した時に、圧着面の両端部は、Ａｌリボン８と接触しない。   Further, the wedge tool 10 used in the present embodiment is provided with recesses 10a (first recesses) at both ends in the long side direction of the crimping surface. On the other hand, three convex portions 10c are provided at the center of the crimping surface with two shallow concave grooves 10b (second concave portions) interposed therebetween. Here, the step La between the convex portion 10c and the concave portion 10a shown in FIG. 11B is set to be larger than the thickness of the Al ribbon 8, for example, the thickness of the Al ribbon 8 is 0.05 mm. In this case, the step between the convex portion 10c and the concave portion 10a is about 0.06 mm. Therefore, when the crimping surface of the wedge tool 10 is pressed against the Al ribbon 8, both ends of the crimping surface do not contact the Al ribbon 8.

つまり、図１１（ｂ）に示すように、ウェッジツール１０の圧着面の両端部に設けられている凹部１０ａは、Ａｌリボン８の幅方向の両端部（厚膜部８ａ）に対向する領域である。従って、ウェッジツール１０の圧着面をＡｌリボン８に圧接した時、Ａｌリボン８の幅方向の両端部（厚膜部８ａ）は、ウェッジツール１０と接触しないということになる。   That is, as shown in FIG. 11 (b), the recesses 10 a provided at both ends of the crimping surface of the wedge tool 10 are regions facing the both ends (thick film portion 8 a) in the width direction of the Al ribbon 8. is there. Therefore, when the crimping surface of the wedge tool 10 is pressed against the Al ribbon 8, both end portions (thick film portions 8 a) in the width direction of the Al ribbon 8 do not come into contact with the wedge tool 10.

ウェッジツール１０の圧着面の中央部に設けられた２つの浅い凹溝１０ｂは、この圧着面をＡｌリボン８に圧接した時に、Ａｌリボン８の中央部（薄膜部８ｃ）に加わる応力を周囲（厚膜部８ａ、８ｂ）に逃がすための溝である。この浅い凹溝１０ｂの溝の深さ、すなわち図１１（ｂ）に示す凸部１０ｃと凹部１０ｂとの段差Ｌｂは、前述の凸部１０ｃと凹部１０ａとの段差Ｌａよりも段差量が小さい（段差Ｌａ＞段差Ｌｂ）。すなわち、Ａｌリボン８の厚膜部８ｂおよび薄膜部８ｃは、それぞれウェッジツール１０の浅い凹溝１０ｂおよび凸部１０ｃによって形成された部分であり、Ａｌリボン８の厚さは、厚膜部８ａ＞厚膜部８ｂ＞薄膜部８ｃの順となっている。   The two shallow concave grooves 10b provided in the central portion of the crimping surface of the wedge tool 10 surround the stress applied to the central portion (thin film portion 8c) of the Al ribbon 8 when the crimping surface is pressed against the Al ribbon 8. It is a groove for escaping to the thick film portions 8a and 8b). The depth of the shallow concave groove 10b, that is, the step Lb between the convex portion 10c and the concave portion 10b shown in FIG. 11B is smaller than the step height La between the convex portion 10c and the concave portion 10a described above ( Step La> Step Lb). That is, the thick film portion 8b and the thin film portion 8c of the Al ribbon 8 are portions formed by the shallow concave groove 10b and the convex portion 10c of the wedge tool 10, respectively. The thickness of the Al ribbon 8 is thick film portion 8a>. The order is thick film portion 8b> thin film portion 8c.

なお、圧着面の浅い凹溝１０ｂは、必須のものではなく、例えば図１２に示すように、中央部全体を凸部１０ｃにしてもよい。あるいは、図１３に示すように、中央部に一箇所だけ浅い凹溝１０ｂを設けてもよい。いずれの場合においても、圧着面の両端部に凹部１０ａを設けることにより、Ａｌリボン８の両端部（厚膜部８ａ）に亀裂が入らなくなるので、亀裂がリボンの内側に進行して、Ａｌリボン８が断線することを防止することができる。   Note that the concave groove 10b having a shallow crimping surface is not essential, and for example, as shown in FIG. 12, the entire central portion may be a convex portion 10c. Or as shown in FIG. 13, you may provide the shallow ditch | groove 10b only in one place in the center part. In any case, by providing the concave portions 10a at both ends of the crimping surface, cracks do not occur at both ends (thick film portion 8a) of the Al ribbon 8, so that the crack progresses inside the ribbon and the Al ribbon It is possible to prevent 8 from being disconnected.

図１４は、リボンボンディング装置に装着された上記ウェッジツール１０の先端部近傍を示す側面図である。図１４に示すように、ウェッジツール１０の一方の側面には、Ａｌリボン８をウェッジツール１０の圧着面に送り出すためのリボンガイド１１が取り付けられる。また、ウェッジツール１０のもう一方の側面には、ボンディング完了後にＡｌリボン１０を切断するためのカッター１２が上下動可能に取り付けられる。   FIG. 14 is a side view showing the vicinity of the tip of the wedge tool 10 mounted on the ribbon bonding apparatus. As shown in FIG. 14, a ribbon guide 11 for sending the Al ribbon 8 to the crimping surface of the wedge tool 10 is attached to one side surface of the wedge tool 10. A cutter 12 for cutting the Al ribbon 10 after completion of bonding is attached to the other side surface of the wedge tool 10 so as to be movable up and down.

次に、上記ウェッジツール１０を使ったＡｌリボン８のボンディング工程を含むＦＬＰの製造方法を説明する。図１５は、ＦＬＰの製造工程を示す全体フロー図である。   Next, a method for manufacturing the FLP including the bonding process of the Al ribbon 8 using the wedge tool 10 will be described. FIG. 15 is an overall flowchart showing the manufacturing process of the FLP.

本実施の形態のＦＬＰを製造するには、まず、図１６および図１７に示すように、Ａｇペーストや半田などの導電性接着剤４を使用してリードフレームＬＦのダイパッド部３Ｄ上に半導体チップ１を搭載する（ダイボンディング）。   In order to manufacture the FLP of the present embodiment, first, as shown in FIGS. 16 and 17, a semiconductor chip is formed on the die pad portion 3D of the lead frame LF using a conductive adhesive 4 such as Ag paste or solder. 1 is mounted (die bonding).

次に、図１８および図１９に示すように、リボンガイド１１から送り出されたＡｌリボン８の先端部を半導体チップ１の第１のソースパッド６上に位置決めした後、ウェッジツール１０の圧着面をＡｌリボン８に圧接し、数Ｗ程度のエネルギーの超音波振動を印加する。これにより、ウェッジツール１０の圧着面に形成された凸部１０ｃと接する領域のＡｌリボン８が潰されて第１のソースパッド６の表面にボンディングされる。前述したように、ウェッジツール１０の圧着面の両端部には凹部１０ａが設けられているので、ソースパッド６にボンディングされたＡｌリボン８の幅方向の両端部は、ウェッジツール１０の圧着面と接触しない。そのため、Ａｌリボン８の両端部に亀裂が入らなくなるので、亀裂がリボンの内側に進行して、Ａｌリボン８が断線することを防止することができる。   Next, as shown in FIGS. 18 and 19, after the tip of the Al ribbon 8 fed from the ribbon guide 11 is positioned on the first source pad 6 of the semiconductor chip 1, the crimping surface of the wedge tool 10 is moved. An ultrasonic vibration having an energy of about several W is applied in pressure contact with the Al ribbon 8. As a result, the Al ribbon 8 in a region in contact with the convex portion 10 c formed on the crimping surface of the wedge tool 10 is crushed and bonded to the surface of the first source pad 6. As described above, since the concave portions 10 a are provided at both ends of the crimping surface of the wedge tool 10, both ends in the width direction of the Al ribbon 8 bonded to the source pad 6 are connected to the crimping surface of the wedge tool 10. Do not touch. Therefore, since cracks do not enter at both ends of the Al ribbon 8, it is possible to prevent the Al ribbon 8 from breaking due to the crack progressing to the inside of the ribbon.

次に、ウェッジツール１０を第２のソースパッド６上に移動させながら、２個のソースパッド６の間のＡｌリボン８にループを形成した後、図２０および図２１に示すように、ウェッジツール１０の圧着面をＡｌリボン８に圧接し、数Ｗ程度のエネルギーの超音波振動を印加する。これにより、ウェッジツール１０の圧着面に形成された凸部１０ｃと接する領域のＡｌリボン８が潰されて第２のソースパッド６の表面にボンディングされる。この時も、第２のソースパッド６にボンディングされたＡｌリボン８の幅方向の両端部は、ウェッジツール１０の圧着面と接触しない。そのため、第２のソースパッド６におけるボンディングにおいても、Ａｌリボン８の両端部に亀裂が入らなくなるので、亀裂がリボンの内側に進行して、Ａｌリボン８が断線することを防止することができる。   Next, while moving the wedge tool 10 onto the second source pad 6, a loop is formed in the Al ribbon 8 between the two source pads 6, and as shown in FIGS. The pressure contact surface of 10 is pressed against the Al ribbon 8, and ultrasonic vibration having an energy of about several W is applied. Thereby, the Al ribbon 8 in a region in contact with the convex portion 10 c formed on the crimping surface of the wedge tool 10 is crushed and bonded to the surface of the second source pad 6. Also at this time, both ends in the width direction of the Al ribbon 8 bonded to the second source pad 6 do not come into contact with the crimping surface of the wedge tool 10. For this reason, even when bonding is performed on the second source pad 6, cracks do not occur at both ends of the Al ribbon 8, so that it is possible to prevent the Al ribbon 8 from being broken due to the crack progressing to the inside of the ribbon.

前述したように、２個のソースパッド６の間でＡｌリボン８にループを形成すると、ループの立ち上がりが非常に急峻になるために、ループが立ち上がる領域のＡｌリボン８に強い曲げ応力が加わる。Ａｌリボン８は、この強い曲げ応力がかかることにより、断線する場合もある。この曲げ応力を緩和する対策として、図２２に示すように、ウェッジツール１０の圧着面に形成された凹溝１０ｂのうち、ソースポスト３Ｓに近い側（ループに近い側）に位置する角部の曲率半径（Ｒ１）を、Ａｌリボン８の先端側に位置する角部の曲率半径（Ｒ２）よりも大きくする（Ｒ１＞Ｒ２）ことが有効である。このようにした場合は、Ａｌリボン８の厚膜部８ｂの角部のうち、ソースポスト３Ｓに近い側（ループに近い側）に位置する角部の曲率半径が、対向する側（Ａｌリボン８の先端側）に位置する角部の曲率半径よりも大きくなるので、Ａｌリボン８に加わる曲げ応力が分散される。一方、Ａｌリボン８の先端側に位置する角部の曲率半径（Ｒ２）を小さくすることにより、Ａｌリボン８とソースパッド６の接合面積を確保することができる。   As described above, when a loop is formed on the Al ribbon 8 between the two source pads 6, the rise of the loop becomes very steep, so that a strong bending stress is applied to the Al ribbon 8 in the region where the loop rises. The Al ribbon 8 may be disconnected due to the strong bending stress. As a measure to alleviate this bending stress, as shown in FIG. 22, of the concave groove 10b formed on the crimping surface of the wedge tool 10, the corner portion located on the side close to the source post 3S (side close to the loop). It is effective to make the radius of curvature (R1) larger than the radius of curvature (R2) of the corner located on the tip side of the Al ribbon 8 (R1> R2). In this case, of the corners of the thick film portion 8b of the Al ribbon 8, the radius of curvature of the corner located on the side close to the source post 3S (side close to the loop) is the opposite side (Al ribbon 8). The bending stress applied to the Al ribbon 8 is dispersed. On the other hand, by reducing the radius of curvature (R2) of the corner located on the tip side of the Al ribbon 8, the bonding area between the Al ribbon 8 and the source pad 6 can be secured.

次に、図２３に示すように、ウェッジツール１０をリードフレームＬＦのソースポスト３Ｓ上に移動させた後、ウェッジツール１０の圧着面をＡｌリボン８に圧接し、上記の同様の方法でＡｌリボン８をソースポスト３Ｓの表面にボンディングする。続いて、図２４に示すように、Ａｌリボン８をカッター１２で切断することにより、ソースポスト３Ｓと２個のソースパッド６をＡｌリボン８によって電気的に接続するリボンボンディング工程が完了する。   Next, as shown in FIG. 23, after the wedge tool 10 is moved onto the source post 3S of the lead frame LF, the crimping surface of the wedge tool 10 is pressed against the Al ribbon 8, and the Al ribbon is formed in the same manner as described above. 8 is bonded to the surface of the source post 3S. Next, as shown in FIG. 24, the Al ribbon 8 is cut by the cutter 12, thereby completing the ribbon bonding step of electrically connecting the source post 3 </ b> S and the two source pads 6 by the Al ribbon 8.

このようにして、上記のリボンボンディング工程を繰り返し、図２５に示すように、リードフレームＬＦ上に搭載された全ての半導体チップ１のソースパッド６とソースポスト３ＳをＡｌリボン８によって電気的に接続した後、図２６に示すように、周知のボールボンディング装置を用いて、リードフレームＬＦ上に搭載された全ての半導体チップ１のゲートパッド５とゲートポスト３ＧとをＡｕワイヤ７によって電気的に接続する。   In this way, the above ribbon bonding process is repeated, and the source pads 6 and the source posts 3S of all the semiconductor chips 1 mounted on the lead frame LF are electrically connected by the Al ribbon 8 as shown in FIG. After that, as shown in FIG. 26, the gate pads 5 and the gate posts 3G of all the semiconductor chips 1 mounted on the lead frame LF are electrically connected by Au wires 7 using a known ball bonding apparatus. To do.

なお、Ａｌリボン８のボンディング工程とＡｕワイヤ７のボンディング工程は、上記と逆の順序で行うこともできる。すなわち、Ａｕワイヤ７のボンディング後にＡｌリボン８のボンディングを行うこともできる。ただし、Ａｌリボン８のリボン幅およびリボン厚は、Ａｕワイヤ７のワイヤ径よりも大きいので、Ａｌリボン８のボンディング時に半導体チップ１に加わる振動エネルギーは、Ａｕワイヤ７のボンディング時に半導体チップ１に加わる振動エネルギーよりも大きい。従って、Ａｕワイヤ７のボンディング後にＡｌリボン８のボンディングを行うと、Ａｌリボン８のボンディング時の振動エネルギーによって、Ａｕワイヤ７とゲートパッド５との接着強度が低下し、場合によっては、Ａｕワイヤ７がゲートパッド５から外れてしまう恐れがある。また、Ａｌリボン８のボンディングに使用するウェッジツール１０がＡｕワイヤ７に接触し、ワイヤに傷を付けたり、切断したりする恐れもある。従って、Ａｌリボン８とＡｕワイヤ７のボンディング順序は、Ａｌリボン８のボンディング後にＡｕワイヤ７のボンディングを行うことが望ましい。   The bonding process of the Al ribbon 8 and the bonding process of the Au wire 7 can also be performed in the reverse order. That is, the Al ribbon 8 can be bonded after the Au wire 7 is bonded. However, since the ribbon width and ribbon thickness of the Al ribbon 8 are larger than the wire diameter of the Au wire 7, the vibration energy applied to the semiconductor chip 1 during bonding of the Al ribbon 8 is applied to the semiconductor chip 1 during bonding of the Au wire 7. Greater than vibration energy. Therefore, when the Al ribbon 8 is bonded after the Au wire 7 is bonded, the bonding strength between the Au wire 7 and the gate pad 5 is reduced due to vibration energy at the time of bonding the Al ribbon 8. May come off from the gate pad 5. In addition, the wedge tool 10 used for bonding the Al ribbon 8 may come into contact with the Au wire 7, and the wire may be damaged or cut. Therefore, the bonding order of the Al ribbon 8 and the Au wire 7 is preferably performed after the Al ribbon 8 is bonded.

次に、半導体チップ１、Ａｌリボン８、Ａｕワイヤ７、リード３の一部、およびダイパッド部３Ｄの一部をモールド樹脂２で封止し、続いて、モールド樹脂２の表面にレーザーマーキング法で製品名などを印刷した後、モールド樹脂２の外部に露出した不要なリードフレームＬＦの切断と樹脂バリの除去を行い、最後に、製品の良・不良を判別する選別工程を経ることにより、前記図１〜図４に示す本実施の形態のＦＬＰが完成する。   Next, the semiconductor chip 1, the Al ribbon 8, the Au wire 7, a part of the lead 3 and a part of the die pad part 3 </ b> D are sealed with the mold resin 2, and then the surface of the mold resin 2 is laser-marked. After printing the product name, etc., the unnecessary lead frame LF exposed to the outside of the mold resin 2 is cut and the resin burrs are removed, and finally, through a selection process for determining whether the product is good or bad, The FLP of the present embodiment shown in FIGS. 1 to 4 is completed.

このように、本実施の形態では、ウェッジツール１０の圧着面の両端部に凹部１０ａを設け、Ａｌリボン８の幅方向の両端部がウェッジツール１０の圧着面と接触しないようにしたので、近接して配置された２個のソースパッド６に極めて薄いＡｌリボン８をボンディングした場合においても、Ａｌリボン８とソースパッド６との接続強度を保ちながら、Ａｌリボン８の断線を防止することが可能となる。   Thus, in this Embodiment, since the recessed part 10a was provided in the both ends of the crimping | compression-bonding surface of the wedge tool 10, and the both ends of the width direction of the Al ribbon 8 were made not to contact the crimping surface of the wedge tool 10, it adjoins. Even when an extremely thin Al ribbon 8 is bonded to two source pads 6 arranged in this manner, it is possible to prevent disconnection of the Al ribbon 8 while maintaining the connection strength between the Al ribbon 8 and the source pad 6. It becomes.

また、ウェッジツール１０の圧着面の角部の曲率半径（Ｒ１）を大きくしたことにより、ループの急峻な立ち上がりに起因してＡｌリボン８に加わる曲げ応力を抑制することができるので、Ａｌリボン８の断線をより確実に防止することができる。   In addition, since the radius of curvature (R1) of the corner of the crimping surface of the wedge tool 10 is increased, the bending stress applied to the Al ribbon 8 due to the steep rise of the loop can be suppressed. Can be more reliably prevented.

また、ウェッジツール１０の圧着面の両端部をＡｌリボン８と非接触にしたことにより、ウェッジツール１０を繰り返し使用した場合でも、Ａｌリボン８から発生するＡｌ粉末の付着に起因する圧着面の劣化が抑制されるので、ウェッジツール１０の長寿命化を図ることができる。   In addition, since both ends of the crimping surface of the wedge tool 10 are not in contact with the Al ribbon 8, even when the wedge tool 10 is repeatedly used, the degradation of the crimping surface due to adhesion of Al powder generated from the Al ribbon 8 occurs. Therefore, the life of the wedge tool 10 can be extended.

（実施の形態２）
図２７に示すように、本実施の形態のＦＬＰは、パワーＭＯＳＦＥＴのオン抵抗をさらに低減するために、半導体チップ１のソースパッド６とソースポスト３Ｓを複数本のＡｌリボン８で接続してもよい。ここでは、ソースパッド６とソースポスト３Ｓを２本のＡｌリボン８で接続した例を示している。なお、ソースパッド６とソースポスト３Ｓを接続するＡｌリボン８の本数は、３本以上であってもよい。 (Embodiment 2)
As shown in FIG. 27, in the FLP of this embodiment, the source pad 6 and the source post 3S of the semiconductor chip 1 are connected by a plurality of Al ribbons 8 in order to further reduce the on-resistance of the power MOSFET. Good. Here, an example in which the source pad 6 and the source post 3S are connected by two Al ribbons 8 is shown. The number of Al ribbons 8 connecting the source pad 6 and the source post 3S may be three or more.

ＦＬＰは、品種あるいは世代によって半導体チップ１の寸法が異なり、これに伴ってソースパッド６の寸法も異なってくる。しかし、ソースパッド６の寸法に応じて、その都度、幅の異なる複数種類のＡｌリボン８を用意すると、Ａｌリボン８の管理が煩雑になる。これに対して、本実施の形態のように、比較的幅の狭いＡｌリボン８を１種類用意し、ソースパッド６の寸法に応じてＡｌリボン８の接続本数を変えるようにした場合は、Ａｌリボン８の管理が煩雑になることはない。   In the FLP, the size of the semiconductor chip 1 varies depending on the type or generation, and the size of the source pad 6 varies accordingly. However, if a plurality of types of Al ribbons 8 having different widths are prepared each time according to the dimensions of the source pad 6, the management of the Al ribbon 8 becomes complicated. On the other hand, when one kind of relatively narrow Al ribbon 8 is prepared and the number of connected Al ribbons 8 is changed according to the dimensions of the source pad 6 as in the present embodiment, The management of the ribbon 8 is not complicated.

本実施の形態のＦＬＰを製造する場合でも、Ａｌリボン８のボンディング工程において前述したウェッジツール１０を使用することにより、前記実施の形態１と同様の効果を得ることができる。   Even when the FLP of the present embodiment is manufactured, the same effect as in the first embodiment can be obtained by using the wedge tool 10 described above in the bonding process of the Al ribbon 8.

（実施の形態３）
一般に、ＦＬＰを含む樹脂封止型半導体装置の製造工程では、前記図１６に示したような、複数のダイパッド部３Ｄを設けたリードフレームＬＦが使用される。 (Embodiment 3)
Generally, in a manufacturing process of a resin-encapsulated semiconductor device including FLP, a lead frame LF provided with a plurality of die pad portions 3D as shown in FIG. 16 is used.

このようなリードフレームＬＦに搭載された複数個の半導体チップ１のソースパッド６とソースポスト３ＰをＡｌリボン８で接続する際には、図２８に示すように、複数本のウェッジツール１０を連結し、複数個の半導体チップ１のソースパッド６に同時にＡｌリボン８を接続することにより、ボンディング時間を短縮することができる。   When the source pads 6 and the source posts 3P of the plurality of semiconductor chips 1 mounted on the lead frame LF are connected by the Al ribbon 8, a plurality of wedge tools 10 are connected as shown in FIG. The bonding time can be shortened by simultaneously connecting the Al ribbon 8 to the source pads 6 of the plurality of semiconductor chips 1.

この場合も、前記実施の形態１と同様、前述したウェッジツール１０を使用することにより、前記実施の形態１と同様の効果を得ることができる。   In this case as well, the same effect as in the first embodiment can be obtained by using the wedge tool 10 described above as in the first embodiment.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

前記実施の形態では、ソースパッドとソースポストを接続する導電材料としてＡｌリボンを用いたが、ＡｕあるいはＣｕ合金のような電気抵抗の小さい他の金属材料で構成されたリボンを用いる場合にも適用することができる。また、ゲートポストとゲートパッドを接続する導電材料として、Ａｕワイヤ以外の材料、例えばＡｌワイヤやＣｕワイヤを用いてもよい。   In the above embodiment, the Al ribbon is used as the conductive material for connecting the source pad and the source post. However, the present invention is also applicable to the case where a ribbon made of another metal material having a low electric resistance such as Au or Cu alloy is used. can do. Further, as a conductive material for connecting the gate post and the gate pad, a material other than the Au wire, for example, an Al wire or a Cu wire may be used.

また、前記実施の形態では、Ａｇペーストを使ってダイパッド部上に半導体チップを搭載したが、Ａｇペースト以外のペレット付け材料、例えば半田ペーストや半田リボンなどを使うこともできる。また、ダイパッド部３Ｄのチップを搭載する部分に、半田メッキを施してもよい。半田リボンや半田メッキで半田付けを行う場合は、フラックス等の活性剤を併用することで、半田濡れ性を確保できる。なお、半導体チップを半田で接続させる場合、半田付け面（チップの裏面）にＮｉ／Ａｕ等のメタライズを施しておくことにより、半田の濡れ性および半田との接続性を確保できる。   Moreover, in the said embodiment, although the semiconductor chip was mounted on the die pad part using Ag paste, pelletizing materials other than Ag paste, for example, a solder paste, a solder ribbon, etc. can also be used. Also, solder plating may be applied to the portion of the die pad portion 3D where the chip is mounted. When soldering with a solder ribbon or solder plating, solder wettability can be secured by using an activator such as flux together. In addition, when connecting a semiconductor chip with solder, wettability of solder and connectivity with solder can be ensured by performing metallization such as Ni / Au on the soldering surface (back surface of the chip).

前記実施の形態では、パワーＭＯＳＦＥＴが形成された半導体チップを封止する樹脂パッケージとしてＦＬＰを例示したが、例えばＳＯＰ−８などに適用することもできる。   In the embodiment, the FLP is exemplified as the resin package for sealing the semiconductor chip on which the power MOSFET is formed. However, the resin package may be applied to, for example, SOP-8.

図２９は、ＳＯＰ−８の上面を示す平面図である。ＳＯＰ−８は、ＦＬＰと同じく小型面実装パッケージの一種であり、モールド樹脂２２の外部に露出した８本のリード２３のピン配置もＦＬＰと同じであるが、リード２３のそれぞれがガルウィング状に成形されている。図３０は、前記実施の形態１で使用した半導体チップ１をモールド樹脂２２で封止したＳＯＰ−８の内部構造を示す平面図である。この場合も、ソースパッド６とソースポスト２３ＳをＡｌリボン８で接続する際に前記実施の形態のウェッジツールを使用することにより、Ａｌリボン８のボンディング強度を保ちつつ、Ａｌリボン８の断線を防止することができる。   FIG. 29 is a plan view showing the upper surface of SOP-8. SOP-8 is a kind of small surface mount package similar to FLP, and the pin arrangement of the eight leads 23 exposed to the outside of the mold resin 22 is the same as FLP, but each of the leads 23 is formed in a gull wing shape. Has been. FIG. 30 is a plan view showing the internal structure of SOP-8 in which the semiconductor chip 1 used in the first embodiment is sealed with the mold resin 22. Also in this case, by using the wedge tool of the above embodiment when the source pad 6 and the source post 23S are connected by the Al ribbon 8, the Al ribbon 8 is prevented from being disconnected while maintaining the bonding strength of the Al ribbon 8. can do.

また、前記実施の形態では、２個（複数個）のソースパッドを有する半導体チップにＡｌリボンをボンディングする場合について説明したが、図３１に示すように、１個のソースパッド６を有する半導体チップ１にＡｌリボン８をボンディングする場合にも適用することができる。すなわち、半導体チップのサイズが極めて小さくなると、ソースパッドとソースポストの間隔も狭くなり、かつソースパッドとソースポストの間に形成されるＡｌリボンのループも急峻になるので、Ａｌリボンのボンディング強度を保ちつつ、Ａｌリボンの断線を防止するためには、前記実施の形態のウェッジツールを使用することが有効である。   In the above embodiment, the case where the Al ribbon is bonded to the semiconductor chip having two (plural) source pads has been described. However, as shown in FIG. 31, the semiconductor chip having one source pad 6. The present invention can also be applied to the case where the Al ribbon 8 is bonded to 1. That is, when the size of the semiconductor chip is extremely small, the distance between the source pad and the source post is also narrowed, and the loop of the Al ribbon formed between the source pad and the source post becomes steep, so that the bonding strength of the Al ribbon is increased. In order to prevent disconnection of the Al ribbon while maintaining it, it is effective to use the wedge tool of the above embodiment.

また、前記実施の形態では、パワーＭＯＳＦＥＴが形成された半導体チップのソースパッドにＡｌリボンをボンディングしたが、Ａｌリボンをボンディングすることのできるパッドを有する半導体チップであれば、パワーＭＯＳＦＥＴ以外の素子が形成された半導体チップであっても使用することができる。例えば絶縁ゲートバイポーラトランジスタ(Insulated Gate Bipolar Transistor:ＩＧＢＴ）が形成された半導体チップの場合は、ＩＧＢＴのオン抵抗を低減するために、エミッタパッドをゲートパッドよりも広い面積で構成するので、エミッタパッドにＡｌリボンをボンディングする場合にも、本発明を適用することができる。   Moreover, in the said embodiment, although Al ribbon was bonded to the source pad of the semiconductor chip in which power MOSFET was formed, if it is a semiconductor chip which has a pad which can bond Al ribbon, elements other than power MOSFET will be used. Even a formed semiconductor chip can be used. For example, in the case of a semiconductor chip on which an insulated gate bipolar transistor (IGBT) is formed, the emitter pad is configured with a larger area than the gate pad in order to reduce the on-resistance of the IGBT. The present invention can also be applied when bonding an Al ribbon.

本発明は、半導体チップのボンディングパッドとリードフレームを金属リボンで接続する半導体装置に適用することができる。   The present invention can be applied to a semiconductor device in which a bonding pad of a semiconductor chip and a lead frame are connected by a metal ribbon.

１ 半導体チップ
２ モールド樹脂
３ リード
３Ｄ ダイパッド部
３Ｇ ゲートポスト
３Ｓ ソースポスト
４ 導電性接着剤
５ ゲートパッド
６ ソースパッド
７ Ａｕワイヤ
８ Ａｌリボン
８ａ 厚膜部
８ｂ 厚膜部
８ｃ 薄膜部
１０ ウェッジツール
１０ａ 凹部
１０ｂ 凹溝
１０ｃ 凸部
１１ リボンガイド
１２ カッター
２０ ウェッジツール
２２ モールド樹脂
２３ リード
２３Ｓ ソースポスト
３０ ｎ＋型単結晶シリコン基板
３１ ｎ−型単結晶シリコン層
３２ ｐ型半導体領域
３３ ｎ＋型半導体領域（ソース）
３４ 溝
３５ ゲート絶縁膜
３６ ゲート電極
３７ サイドウォールスペーサ
３８ 窒化シリコン膜
３９ 酸化シリコン膜
４１ ソース電極
４２ ゲート引き出し電極
４３ バリアメタル膜
４４ Ａｌ合金膜
４５ 接続孔
４６ 表面保護膜
ＬＦ リードフレーム
Ｌａ、Ｌｂ 段差 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Mold resin 3 Lead 3D Die pad part 3G Gate post 3S Source post 4 Conductive adhesive 5 Gate pad 6 Source pad 7 Au wire 8 Al ribbon 8a Thick film part 8b Thick film part 8c Thin film part 10 Wedge tool 10a Concave part 10b Concave groove 10c Convex portion 11 Ribbon guide 12 Cutter 20 Wedge tool 22 Mold resin 23 Lead 23S Source post 30 n + type single crystal silicon substrate 31 n − type single crystal silicon layer 32 p type semiconductor region 33 n + type semiconductor region ( Source)
34 Groove 35 Gate insulating film 36 Gate electrode 37 Side wall spacer 38 Silicon nitride film 39 Silicon oxide film 41 Source electrode 42 Gate lead electrode 43 Barrier metal film 44 Al alloy film 45 Connection hole 46 Surface protective film LF Lead frames La and Lb Steps

Claims (10)

主面と、前記主面とは反対側の裏面とを有する半導体チップと、
前記半導体チップの前記主面に形成された第１パッドと、
前記半導体チップの近傍に配置された第１導体部と、
前記第１パッドと前記第１導体部とを電気的に接続する金属リボンと、
を有し、
前記金属リボンが前記第１パッドから前記第１導体部に向かって延びる方向と直交する方向において、前記金属リボンと前記第１パッドとが接続された部分の前記金属リボンには、両端に第１厚膜部、前記第１厚膜部間に複数の薄膜部、および前記複数の薄膜部のそれぞれの間に第２厚膜部が形成され、
前記第２厚膜部の厚さは、前記複数の薄膜部のそれぞれの厚さよりも厚く、前記金属リボンの前記両端に形成された前記第１厚膜部のそれぞれの厚さは、前記第２膜厚部の厚さよりも厚い、半導体装置。 A semiconductor chip having a main surface and a back surface opposite to the main surface;
A first pad formed on the main surface of the semiconductor chip;
A first conductor portion disposed in the vicinity of the semiconductor chip;
A metal ribbon that electrically connects the first pad and the first conductor portion ;
I have a,
In the direction orthogonal to the direction in which the metal ribbon extends from the first pad toward the first conductor portion, the metal ribbon in a portion where the metal ribbon and the first pad are connected has first ends at both ends. A thick film portion, a plurality of thin film portions between the first thick film portions, and a second thick film portion between each of the plurality of thin film portions,
The thickness of the second thick film portion is greater than the thickness of each of the plurality of thin film portions, and the thickness of each of the first thick film portions formed at the both ends of the metal ribbon is the second thickness. A semiconductor device that is thicker than the thickness of the film thickness portion . 請求項１に記載の半導体装置において、The semiconductor device according to claim 1,
前記第１厚膜部の厚さは、前記金属リボンの中の最も厚い部分の厚さと等しい、半導体装置。The thickness of the first thick film portion is equal to the thickness of the thickest portion in the metal ribbon. 請求項１に記載の半導体装置において、
前記第２厚膜部の前記第１導体部に近い側の角部の曲率半径は、対向する角部の曲率半径よりも大きい、半導体装置。 The semiconductor device according to claim 1,
The second thick portion first radius of curvature on the side of the corner portion near the conductor portion of the larger than the radius of curvature of the corner portion opposite the semiconductor device. 請求項１に記載の半導体装置において、
前記半導体チップの前記主面には、さらに、第２パッドが形成され、
前記金属リボンは、前記第２パッドにも電気的に接続されている、半導体装置。 The semiconductor device according to claim 1,
A second pad is further formed on the main surface of the semiconductor chip ,
The metal ribbon is also electrically connected to the second pad, the semiconductor device. 請求項４に記載の半導体装置において、
前記半導体チップは、パワーＭＯＳＦＥＴを含み、
前記第１パッドおよび前記第２パッドのそれぞれは、前記パワーＭＯＳＦＥＴのソース電極と電気的に接続されている、半導体装置。 The semiconductor device according to claim 4,
The semiconductor chip includes a power MOSFET,
Each of the first pad and the second pad is a semiconductor device electrically connected to a source electrode of the power MOSFET. 請求項５に記載の半導体装置において、
前記半導体チップの前記主面には、前記第１パッドおよび前記第２パッドよりもパッド面積が小さく、前記パワーＭＯＳＦＥＴのゲート電極と電気的に接続された第３パッドがさらに形成され、
前記半導体チップの近傍には、第２導体部がさらに配置され、
前記第３パッドと前記第２導体部とは、金属ワイヤを介して電気的に接続されている、半導体装置。 The semiconductor device according to claim 5,
Wherein the said main surface of the semiconductor chip, the pad area than the first pad and the second pad rather small, third pads gate electrode electrically connected to the power MOSFET is further formed,
In the vicinity of the semiconductor chip, a second conductor portion is further arranged,
The semiconductor device , wherein the third pad and the second conductor portion are electrically connected via a metal wire. 請求項６に記載の半導体装置において、
前記第３パッドは、前記第１パッドおよび前記第２パッドの間に形成されたゲート引き出し配線を介して前記パワーＭＯＳＦＥＴの前記ゲート電極と電気的に接続されている、半導体装置。 The semiconductor device according to claim 6.
It said third pad, the first is the pad and connected the gate electrode and electrically of the second pad the power MOSFET via the gate lead wiring formed between the semiconductor device. 請求項４に記載の半導体装置において、
前記金属リボンの前記第１パッドと接続された部分と、前記金属リボンの前記第２パッドと接続された部分と、の間には、前記金属リボンのループが形成されている、半導体装置。 The semiconductor device according to claim 4,
Said first pad and the connecting portion of said metal ribbon, and the second pad and the connecting portion of said metal ribbon between the loop of the metal ribbon is formed, the semiconductor device. 請求項１に記載の半導体装置において、
前記半導体チップが搭載されたダイパッド部をさらに有し、
前記第１導体部は、リードであって、
前記半導体チップ、前記金属リボン、前記第１導体部の一部、および前記ダイパッド部の一部は、樹脂によって封止されている、半導体装置。 The semiconductor device according to claim 1,
A die pad portion on which the semiconductor chip is mounted;
The first conductive body is a lead,
It said semiconductor chip, said metal ribbon, before Symbol part of the first conductor portion, and a portion of the die pad portion is sealed by resin, the semiconductor device. 請求項１に記載の半導体装置において、
前記金属リボンは、アルミニウムからなる、半導体装置。 The semiconductor device according to claim 1,
The metal ribbon is a semiconductor device made of aluminum.
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