CN214378414U - Packaging structure and wafer structure of intelligent power level module - Google Patents

Packaging structure and wafer structure of intelligent power level module Download PDF

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Publication number
CN214378414U
CN214378414U CN202120529132.9U CN202120529132U CN214378414U CN 214378414 U CN214378414 U CN 214378414U CN 202120529132 U CN202120529132 U CN 202120529132U CN 214378414 U CN214378414 U CN 214378414U
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China
Prior art keywords
chip
insulating layer
area
cutting
welding pad
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Active
Application number
CN202120529132.9U
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Chinese (zh)
Inventor
黄水木
苏子龙
王光峰
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Lizhi Electronics Shenzhen Co ltd
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Lizhi Electronics Shenzhen Co ltd
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Priority to CN202120529132.9U priority Critical patent/CN214378414U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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Abstract

The utility model discloses a packaging structure and wafer structure of intelligent power level module, the packaging structure of intelligent power level module includes lead frame, first chip, second chip, conductive clip, first chip and second chip have first surface, second surface and lateral wall respectively, the second surface has subassembly district and cutting area, the cutting area is located the both sides of subassembly district; the second chip also comprises a welding pad and an insulating layer, wherein the welding pad is arranged in the component area of the second surface, and the insulating layer is arranged on the second surface of the second chip, covers the component area and the cutting area and exposes the welding pad; the side wall of the second chip exposes the insulating layer. The wafer structure has dicing streets between adjacent chips, and the insulating layer completely covers the dicing streets. The structure can avoid the problem of direct short circuit of the chip caused by welding beads or bulges formed by the welding flux, and improve the reliability and stability of finished products.

Description

Packaging structure and wafer structure of intelligent power level module
Technical Field
The utility model belongs to the technical field of the semiconductor package and specifically relates to an intelligent power level module's packaging structure and wafer structure.
Background
When the existing solder for the intelligent power module is used for jointing a chip welding pad and a lead frame, a welding bead or a bulge formed by conductive solder often exists, so that an electrode on the surface of a chip is directly short-circuited with a semiconductor substrate on the side edge of the chip, and the reliability of a finished product is reduced.
SUMMERY OF THE UTILITY MODEL
Based on this, one of the technical problems to be solved by the utility model is to provide an intelligent power level module's packaging structure, possess very high reliability, can avoid the electrode on chip surface and the semiconductor substrate direct short circuit of chip side.
In order to solve the above technical problem, a technical solution of the present invention is, a package structure of an intelligent power module, including a lead frame, a first chip, a second chip, and a conductive clip, wherein the first chip and the second chip are clamped between the lead frame and the conductive clip, the first chip and the second chip respectively have a first surface, a second surface, and a side wall, the second surface has a component area and a cutting area, and the cutting area is located around the component area;
the second chip also comprises a welding pad and an insulating layer; the welding pad is arranged in the component area of the second surface; the insulating layer is arranged on the second surface of the second chip, covers the assembly area and the cutting area and exposes the welding pad; the insulating layer is exposed on the side walls of the two sides of the second chip.
In one embodiment, a package ring is disposed between the device region and the dicing region and disposed on the second surface. The package ring is used for isolation and protection, and external cutting stress, moisture and external charge are brought into the package ring, so that the performance of the internal chip is affected. In addition, the cutting area is used as a boundary point of the assembly area and the cutting area for distinguishing the cutting area.
In one embodiment, the second surface of the second chip faces the lead frame, and the pad is electrically connected to the lead frame through the solder layer.
In one embodiment, the second surface of the first chip and the first surface of the second chip face the conductive clip and are electrically connected to each other.
In one embodiment, a pin portion extends from one end of the conductive clip, and the pin portion is electrically connected to the lead frame through a solder layer.
The second technical problem to be solved of the utility model is to provide a wafer structure, can not only improve the off-the-shelf reliability of intelligent power level module, ensure moreover that preparation efficiency is not influenced. In order to solve the above technical problem, another technical solution of the present invention is a wafer structure, wherein the wafer structure includes a plurality of chips and scribe lines, the chips have a first surface, a second surface and a sidewall, the second surface has a component area and a scribe area, and the scribe area is located around the component area; the chip also comprises a welding pad and an insulating layer, wherein the welding pad is arranged in the component area of the second surface, and the insulating layer is arranged on the second surface of the chip, covers the component area and the cutting area and exposes the welding pad; the cutting channels are located between the adjacent chips, wherein the insulating layer completely covers the cutting channels. The chip described herein is either the first chip or the second chip.
Compared with the prior art, the utility model beneficial effect who brings is through covering subassembly district and cutting area with the insulating layer and exposing the weld pad, and this structure can avoid the welding bead or the uplift that the solder formed in welding process to cause with the electrode on chip surface and the quality problems of the direct short circuit of semiconductor substrate in chip cutting area, improve off-the-shelf reliability and stability. In the wafer dicing process, before dicing the wafer, the dicing streets between adjacent chips are covered with an insulating layer. In the cutting procedure, the insulating layer is cut while cutting the cutting path between two adjacent chips, and the insulating layer structure is provided to improve the reliability and stability of a finished product under the condition of reducing the efficiency without increasing the working procedures.
Drawings
Fig. 1 is a front view of a package structure of an intelligent power stage module of embodiment 1.
Fig. 2 is a schematic diagram of a single chip of embodiment 2.
Fig. 3 is a schematic view of a wafer dicing process according to embodiment 2.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, as those skilled in the art will be able to make similar modifications without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 1, a package structure of an intelligent power stage module includes a lead frame 1, a first chip 21, a second chip 22, and a conductive clip 3. One end of the conductive clip 3 extends to form a pin portion 31, and the pin portion 31 is electrically connected to the lead frame 1 through a solder layer. The first chip 21 and the second chip 22 are sandwiched between the lead frame 1 and the conductive clip 3. The first chip 21 and the second chip 22 respectively have a first surface, a second surface and a sidewall, the second surface includes a component region and a cutting region, and the cutting region is located around the component region. The second chip 22 further includes a pad 23 and an insulating layer 24, wherein the pad 23 of the second chip 22 is disposed in the device region of the second surface; the insulating layer 24 of the second chip 22 is disposed on the second surface, covers the device region and the dicing region, and exposes the bonding pads 23. The insulating layer 24 is exposed on the side wall of the second chip 22. The second surface of the second chip 22 faces the lead frame 1, and the pad 23 is electrically connected to the lead frame 1 through a solder layer. The package rings 25 of the first chip 21 and the second chip 22 are disposed on the surface of the second surface, and the package rings 25 are located between the assembly region and the dicing region. The package ring 25 is used to isolate the protection from external cutting stress, moisture, external charge carry-in, and thus internal chip performance. In addition, the device area and the cutting area are used as boundary points of the device area and the cutting area for distinguishing the device area and the cutting area.
The insulating layer 24 of the chip is arranged on the second surface, the assembly area and the cutting area are covered, and the welding pad 23 is exposed, so that the structure can avoid welding beads or bulges formed by welding materials in a welding procedure, the quality problem of direct short circuit between the electrode on the surface of the chip and the semiconductor substrate in the cutting area of the chip is caused, and the reliability and the stability of a finished product are improved.
In the present embodiment, the second surface of the first chip 21 faces the conductive clip 3; the first chip 21 further includes a pad 23 and an insulating layer 24, the pad 23 of the first chip 21 is disposed in the device region of the second surface, the insulating layer 24 of the first chip 21 is disposed on the second surface, covers the device region and the dicing region, and exposes the pad 23; the insulating layer 24 is exposed on the side wall of the first chip 21. The second surface of the first chip 21 and the first surface of the second chip 22 face the conductive clip 3 and are electrically connected to each other.
Example 2
As shown in fig. 2 and 3, the present embodiment relates to a technical solution of a wafer structure, which includes a plurality of chips and scribe lines, where the chip in the present embodiment is specifically the second chip 22, and in other embodiments, may also be specifically the first chip 21. Dicing streets 6 are located between adjacent chips, and the insulating layer 24 completely covers the dicing streets. .
Referring to fig. 3, in the wafer slicing process for cutting a wafer to prepare the chips, in the present embodiment, the wafer is placed on a cutting station, the second surface of the chip includes a cutting street 6 covered with an insulating layer 24, the package ring 25 is used as a dividing point, a region of the package ring 25 near the edge of the chip is a cutting dividing line between the chip and the cutting street 6, the cutting street 6 between the chips is placed on the cutting street, and the cutting head 5 cuts the insulating layer 24 along the cutting line while cutting the cutting street 6, so as to form the second divided chips 22. According to the manufacturing process, the insulating layer 24 covers the cutting line 6, the insulating layer 24 is cut while the cutting line between two adjacent chips is cut by using a cutting program, and the reliability and the stability of a finished product are improved by providing the insulating layer structure under the conditions that the working procedures are not increased and the efficiency is reduced.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention should not be limited thereby, and all the simple equivalent changes and modifications made according to the present invention are still covered by the present invention. Moreover, it is not necessary for any embodiment or scope of the claims to achieve all of the objects, advantages, or features disclosed herein.

Claims (6)

1. The utility model provides an intelligent power level module's packaging structure, includes lead frame, first chip, second chip, electrically conductive clamp, first chip reach the second chip clamp is located the lead frame with electrically conductive between pressing from both sides its characterized in that:
the first chip and the second chip are respectively provided with a first surface, a second surface and a side wall, the second surface is provided with a component area and a cutting area, and the cutting area is positioned around the component area;
the second chip further comprises a welding pad and an insulating layer, the welding pad is arranged on the component area of the second surface, the insulating layer is arranged on the second surface of the second chip, covers the component area and the cutting area and exposes the welding pad;
wherein the sidewall of the second chip exposes the insulating layer.
2. The package structure of claim 1, wherein: and a packaging ring is arranged between the assembly area and the cutting area and is arranged on the second surface.
3. The package structure of claim 1, wherein: the second surface of the second chip faces the lead frame, and the welding pad is electrically connected with the lead frame through a welding material layer.
4. The package structure of claim 1, wherein: the second surface of the first chip and the first surface of the second chip face the conductive clip and are electrically connected to each other.
5. The package structure of claim 1, wherein: one end of the conductive clip is extended to be provided with a pin part, and the pin part is electrically connected with the lead frame through a solder layer.
6. A wafer structure, characterized by: the wafer structure comprises a plurality of chips and cutting channels, wherein each chip is provided with a first surface, a second surface and a side wall, the second surface is provided with a component area and a cutting area, and the cutting area is positioned around the component area; the chip also comprises a welding pad and an insulating layer, wherein the welding pad is arranged in the component area of the second surface, and the insulating layer is arranged on the second surface of the chip, covers the component area and the cutting area and exposes the welding pad;
the cutting channels are located between the adjacent chips, wherein the insulating layer completely covers the cutting channels.
CN202120529132.9U 2021-03-12 2021-03-12 Packaging structure and wafer structure of intelligent power level module Active CN214378414U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202120529132.9U CN214378414U (en) 2021-03-12 2021-03-12 Packaging structure and wafer structure of intelligent power level module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202120529132.9U CN214378414U (en) 2021-03-12 2021-03-12 Packaging structure and wafer structure of intelligent power level module

Publications (1)

Publication Number Publication Date
CN214378414U true CN214378414U (en) 2021-10-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202120529132.9U Active CN214378414U (en) 2021-03-12 2021-03-12 Packaging structure and wafer structure of intelligent power level module

Country Status (1)

Country Link
CN (1) CN214378414U (en)

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